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lizhongxiao
OpenXG-RAN
Commits
7ea52a11
Commit
7ea52a11
authored
Oct 25, 2023
by
Fang-WANG
Committed by
lfq
Nov 30, 2023
Browse files
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Plain Diff
spareSlot057
parent
90143da3
Changes
6
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Showing
6 changed files
with
30 additions
and
15 deletions
+30
-15
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+6
-5
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+3
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+7
-5
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2
-1
openair2/RRC/NR/nr_rrc_config.c
openair2/RRC/NR/nr_rrc_config.c
+10
-2
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
...ENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
+2
-0
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
7ea52a11
...
@@ -240,11 +240,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
...
@@ -240,11 +240,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
// This schedules the DCI for Uplink and subsequently PUSCH
// This schedules the DCI for Uplink and subsequently PUSCH
nr_schedule_ulsch
(
module_idP
,
frame
,
slot
,
&
sched_info
->
UL_dci_req
);
nr_schedule_ulsch
(
module_idP
,
frame
,
slot
,
&
sched_info
->
UL_dci_req
);
if
(
slot
%
10
!=
7
){
// This schedules the DCI for Downlink and PDSCH
// This schedules the DCI for Downlink and PDSCH
start_meas
(
&
gNB
->
schedule_dlsch
);
start_meas
(
&
gNB
->
schedule_dlsch
);
nr_schedule_ue_spec
(
module_idP
,
frame
,
slot
,
&
sched_info
->
DL_req
,
&
sched_info
->
TX_req
);
nr_schedule_ue_spec
(
module_idP
,
frame
,
slot
,
&
sched_info
->
DL_req
,
&
sched_info
->
TX_req
);
stop_meas
(
&
gNB
->
schedule_dlsch
);
stop_meas
(
&
gNB
->
schedule_dlsch
);
}
nr_sr_reporting
(
gNB
,
frame
,
slot
);
nr_sr_reporting
(
gNB
,
frame
,
slot
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
7ea52a11
...
@@ -446,7 +446,7 @@ static void nr_schedule_msg2(uint16_t rach_frame,
...
@@ -446,7 +446,7 @@ static void nr_schedule_msg2(uint16_t rach_frame,
uint8_t
tdd_period_slot
=
n_slots_frame
;
uint8_t
tdd_period_slot
=
n_slots_frame
;
if
(
tdd
)
{
if
(
tdd
)
{
last_dl_slot_period
=
tdd
->
nrofDownlinkSymbols
=
=
0
?
(
tdd
->
nrofDownlinkSlots
-
1
)
:
tdd
->
nrofDownlinkSlots
;
last_dl_slot_period
=
tdd
->
nrofDownlinkSymbols
!
=
0
?
(
tdd
->
nrofDownlinkSlots
-
1
)
:
tdd
->
nrofDownlinkSlots
;
tdd_period_slot
=
n_slots_frame
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
tdd_period_slot
=
n_slots_frame
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
}
}
else
{
else
{
...
@@ -914,7 +914,7 @@ static void nr_get_Msg3alloc(module_id_t module_id,
...
@@ -914,7 +914,7 @@ static void nr_get_Msg3alloc(module_id_t module_id,
startSymbolAndLength
=
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
startSymbolAndLength
;
startSymbolAndLength
=
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
startSymbolAndLength
;
SLIV2SL
(
startSymbolAndLength
,
&
StartSymbolIndex
,
&
NrOfSymbols
);
SLIV2SL
(
startSymbolAndLength
,
&
StartSymbolIndex
,
&
NrOfSymbols
);
k2
=
*
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
k2
;
k2
=
*
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
k2
;
LOG_
D
(
NR_MAC
,
"Checking Msg3 TDA %d for Msg3_slot %d Msg3_start %d Msg3_nsymb %d: k2 %d, sliv %d,S %d L %d
\n
"
,
LOG_
I
(
NR_MAC
,
"Checking Msg3 TDA %d for Msg3_slot %d Msg3_start %d Msg3_nsymb %d: k2 %d, sliv %d,S %d L %d
\n
"
,
i
,
msg3_slot
,
Msg3start
,
Msg3maxsymb
,
(
int
)
k2
,
(
int
)
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
startSymbolAndLength
,
StartSymbolIndex
,
NrOfSymbols
);
i
,
msg3_slot
,
Msg3start
,
Msg3maxsymb
,
(
int
)
k2
,
(
int
)
pusch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
startSymbolAndLength
,
StartSymbolIndex
,
NrOfSymbols
);
// we want to transmit in the uplink symbols of mixed slot or the first uplink slot
// we want to transmit in the uplink symbols of mixed slot or the first uplink slot
abs_slot
=
(
current_slot
+
k2
+
DELTA
[
mu
]);
abs_slot
=
(
current_slot
+
k2
+
DELTA
[
mu
]);
...
@@ -1852,6 +1852,7 @@ static void nr_generate_Msg4(module_id_t module_idP,
...
@@ -1852,6 +1852,7 @@ static void nr_generate_Msg4(module_id_t module_idP,
TX_req
->
SFN
=
frameP
;
TX_req
->
SFN
=
frameP
;
TX_req
->
Number_of_PDUs
++
;
TX_req
->
Number_of_PDUs
++
;
TX_req
->
Slot
=
slotP
;
TX_req
->
Slot
=
slotP
;
LOG_I
(
PHY
,
"Msg4 send %d.%d
\n
"
,
frameP
,
slotP
);
// Mark the corresponding symbols and RBs as used
// Mark the corresponding symbols and RBs as used
fill_pdcch_vrb_map
(
nr_mac
,
fill_pdcch_vrb_map
(
nr_mac
,
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
7ea52a11
...
@@ -67,6 +67,8 @@ int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *sc
...
@@ -67,6 +67,8 @@ int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *sc
const
int
nr_slots_period
=
tdd
->
nrofDownlinkSlots
+
tdd
->
nrofUplinkSlots
+
1
;
const
int
nr_slots_period
=
tdd
->
nrofDownlinkSlots
+
tdd
->
nrofUplinkSlots
+
1
;
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofDownlinkSlots
)
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofDownlinkSlots
)
return
2
;
return
2
;
else
if
((
slot
%
5
)
==
0
)
return
3
;
}
}
return
0
;
// if FDD or not mixed slot in TDD, for now use default TDA
return
0
;
// if FDD or not mixed slot in TDD, for now use default TDA
}
}
...
@@ -938,10 +940,10 @@ void nr_schedule_ue_spec(module_id_t module_id,
...
@@ -938,10 +940,10 @@ void nr_schedule_ue_spec(module_id_t module_id,
* Possible improvement: take the periodicity from input file.
* Possible improvement: take the periodicity from input file.
* If such UE is not scheduled now, it will be by the preprocessor later.
* If such UE is not scheduled now, it will be by the preprocessor later.
* If we add the CE, ta_apply will be reset */
* If we add the CE, ta_apply will be reset */
if
(
frame
==
(
sched_ctrl
->
ta_frame
+
10
)
%
1024
)
{
//
if (frame == (sched_ctrl->ta_frame + 10) % 1024) {
sched_ctrl
->
ta_apply
=
true
;
/* the timer is reset once TA CE is scheduled */
//
sched_ctrl->ta_apply = true; /* the timer is reset once TA CE is scheduled */
LOG_D
(
NR_MAC
,
"[UE %04x][%d.%d] UL timing alignment procedures: setting flag for Timing Advance command
\n
"
,
UE
->
rnti
,
frame
,
slot
);
//
LOG_D(NR_MAC, "[UE %04x][%d.%d] UL timing alignment procedures: setting flag for Timing Advance command\n", UE->rnti, frame, slot);
}
//
}
if
(
sched_pdsch
->
rbSize
<=
0
)
if
(
sched_pdsch
->
rbSize
<=
0
)
continue
;
continue
;
...
@@ -983,7 +985,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
...
@@ -983,7 +985,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
harq
->
feedback_slot
=
pucch
->
ul_slot
;
harq
->
feedback_slot
=
pucch
->
ul_slot
;
harq
->
is_waiting
=
true
;
harq
->
is_waiting
=
true
;
UE
->
mac_stats
.
dl
.
rounds
[
harq
->
round
]
++
;
UE
->
mac_stats
.
dl
.
rounds
[
harq
->
round
]
++
;
LOG_
D
(
NR_MAC
,
LOG_
I
(
NR_MAC
,
"%4d.%2d [DLSCH/PDSCH/PUCCH] RNTI %04x DCI L %d start %3d RBs %3d startSymbol %2d nb_symbol %2d dmrspos %x MCS %2d nrOfLayers %d TBS %4d HARQ PID %2d round %d RV %d NDI %d dl_data_to_ULACK %d (%d.%d) PUCCH allocation %d TPC %d
\n
"
,
"%4d.%2d [DLSCH/PDSCH/PUCCH] RNTI %04x DCI L %d start %3d RBs %3d startSymbol %2d nb_symbol %2d dmrspos %x MCS %2d nrOfLayers %d TBS %4d HARQ PID %2d round %d RV %d NDI %d dl_data_to_ULACK %d (%d.%d) PUCCH allocation %d TPC %d
\n
"
,
frame
,
frame
,
slot
,
slot
,
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
7ea52a11
...
@@ -2566,7 +2566,7 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
...
@@ -2566,7 +2566,7 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
if
((
frame
*
n_slots_frame
+
slot
-
offset
)
%
period
==
0
)
{
if
((
frame
*
n_slots_frame
+
slot
-
offset
)
%
period
==
0
)
{
LOG_
D
(
NR_MAC
,
"Scheduling CSI-RS in frame %d slot %d Resource ID %ld
\n
"
,
LOG_
I
(
NR_MAC
,
"Scheduling CSI-RS in frame %d slot %d Resource ID %ld
\n
"
,
frame
,
slot
,
nzpcsi
->
nzp_CSI_RS_ResourceId
);
frame
,
slot
,
nzpcsi
->
nzp_CSI_RS_ResourceId
);
UE_info
->
sched_csirs
|=
(
1
<<
dl_bwp
->
bwp_id
);
UE_info
->
sched_csirs
|=
(
1
<<
dl_bwp
->
bwp_id
);
...
@@ -2599,6 +2599,7 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
...
@@ -2599,6 +2599,7 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
csirs_pdu_rel15
->
csi_type
=
1
;
// NZP-CSI-RS
csirs_pdu_rel15
->
csi_type
=
1
;
// NZP-CSI-RS
csirs_pdu_rel15
->
symb_l0
=
resourceMapping
.
firstOFDMSymbolInTimeDomain
;
csirs_pdu_rel15
->
symb_l0
=
resourceMapping
.
firstOFDMSymbolInTimeDomain
;
LOG_I
(
PHY
,
"csirs_pdu_rel15->symb_l0 %d
\n
"
,
csirs_pdu_rel15
->
symb_l0
);
if
(
resourceMapping
.
firstOFDMSymbolInTimeDomain2
)
if
(
resourceMapping
.
firstOFDMSymbolInTimeDomain2
)
csirs_pdu_rel15
->
symb_l1
=
*
resourceMapping
.
firstOFDMSymbolInTimeDomain2
;
csirs_pdu_rel15
->
symb_l1
=
*
resourceMapping
.
firstOFDMSymbolInTimeDomain2
;
csirs_pdu_rel15
->
cdm_type
=
resourceMapping
.
cdm_Type
;
csirs_pdu_rel15
->
cdm_type
=
resourceMapping
.
cdm_Type
;
...
...
openair2/RRC/NR/nr_rrc_config.c
View file @
7ea52a11
...
@@ -367,7 +367,7 @@ static void config_csirs(const NR_ServingCellConfigCommon_t *servingcellconfigco
...
@@ -367,7 +367,7 @@ static void config_csirs(const NR_ServingCellConfigCommon_t *servingcellconfigco
default:
default:
AssertFatal
(
1
==
0
,
"Number of ports not yet supported
\n
"
);
AssertFatal
(
1
==
0
,
"Number of ports not yet supported
\n
"
);
}
}
resourceMapping
.
firstOFDMSymbolInTimeDomain
=
1
3
;
// last symbol of slot
resourceMapping
.
firstOFDMSymbolInTimeDomain
=
1
;
// last symbol of slot
resourceMapping
.
firstOFDMSymbolInTimeDomain2
=
NULL
;
resourceMapping
.
firstOFDMSymbolInTimeDomain2
=
NULL
;
resourceMapping
.
density
.
present
=
NR_CSI_RS_ResourceMapping__density_PR_one
;
resourceMapping
.
density
.
present
=
NR_CSI_RS_ResourceMapping__density_PR_one
;
resourceMapping
.
density
.
choice
.
one
=
(
NULL_t
)
0
;
resourceMapping
.
density
.
choice
.
one
=
(
NULL_t
)
0
;
...
@@ -808,6 +808,14 @@ void nr_rrc_config_dl_tda(struct NR_PDSCH_TimeDomainResourceAllocationList *pdsc
...
@@ -808,6 +808,14 @@ void nr_rrc_config_dl_tda(struct NR_PDSCH_TimeDomainResourceAllocationList *pdsc
}
}
}
}
}
}
// setting 0th,5th TDA for DL with TDA index 3
struct
NR_PDSCH_TimeDomainResourceAllocation
*
timedomainresourceallocation3
=
CALLOC
(
1
,
sizeof
(
NR_PDSCH_TimeDomainResourceAllocation_t
));
// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
//*timedomainresourceallocation->k0 = 0;
timedomainresourceallocation3
->
mappingType
=
NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA
;
timedomainresourceallocation3
->
startSymbolAndLength
=
get_SLIV
(
len_coreset
,
13
-
len_coreset
);
// basic slot configuration starting in symbol 1 til the end of the slot
asn1cSeqAdd
(
&
pdsch_TimeDomainAllocationList
->
list
,
timedomainresourceallocation3
);
}
}
...
@@ -855,7 +863,7 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
...
@@ -855,7 +863,7 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation_msg3
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation_msg3
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
pusch_timedomainresourceallocation_msg3
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
pusch_timedomainresourceallocation_msg3
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
int
no_mix_slot
=
ul_symb
<
3
?
1
:
0
;
// we need at least 2 symbols for scheduling Msg3
int
no_mix_slot
=
ul_symb
<
3
?
1
:
0
;
// we need at least 2 symbols for scheduling Msg3
*
pusch_timedomainresourceallocation_msg3
->
k2
=
nb_slots_per_period
-
DELTA
[
mu
]
+
no_mix_slot
;
*
pusch_timedomainresourceallocation_msg3
->
k2
=
nb_slots_per_period
-
DELTA
[
mu
]
+
no_mix_slot
+
1
;
if
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
min_fb_delay
)
if
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
min_fb_delay
)
*
pusch_timedomainresourceallocation_msg3
->
k2
+=
nb_slots_per_period
;
*
pusch_timedomainresourceallocation_msg3
->
k2
+=
nb_slots_per_period
;
AssertFatal
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
33
,
"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)
\n
"
,
AssertFatal
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
33
,
"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)
\n
"
,
...
...
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
View file @
7ea52a11
...
@@ -19,6 +19,8 @@ gNBs =
...
@@ -19,6 +19,8 @@ gNBs =
do_CSIRS
=
1
;
do_CSIRS
=
1
;
do_SRS
=
1
;
do_SRS
=
1
;
min_rxtxtime
=
5
;
firstOFDMSymbolInTimeDomain
=
12
;
servingCellConfigCommon
= (
servingCellConfigCommon
= (
{
{
...
...
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