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OpenXG-RAN
Commit 7fd1a1e2 authored by Raghavendra Dinavahi's avatar Raghavendra Dinavahi Committed by Marwan Hammouda
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Changes for enabling 32 HARQ processes in DL and UL

parent abf0444d
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Showing with 213 additions and 76 deletions
common/openairinterface5g_limits.h
View file @ 7fd1a1e2
#ifndef OPENAIRINTERFACE5G_LIMITS_H_
#define OPENAIRINTERFACE5G_LIMITS_H_
# define MAX_MOBILES_PER_GNB 16
# define MAX_MOBILES_PER_GNB 32
# define NUMBER_OF_eNB_MAX 1
# define NUMBER_OF_gNB_MAX 1
# define NUMBER_OF_RU_MAX 2
......
common/utils/nr/nr_common.h
View file @ 7fd1a1e2
......@@ -39,7 +39,7 @@
#define MAX_BWP_SIZE 275
#define NR_MAX_NUM_BWP 4
#define NR_MAX_HARQ_PROCESSES 16
#define NR_MAX_HARQ_PROCESSES 32
#define NR_NB_REG_PER_CCE 6
#define NR_NB_SC_PER_RB 12
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @ 7fd1a1e2
......@@ -3272,6 +3272,44 @@ uint16_t get_rb_bwp_dci(nr_dci_format_t format,
return N_RB;
}
int get_nrofHARQ_ProcessesForPDSCH(e_NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH n,
struct NR_PDSCH_ServingCellConfig__ext3 *ext3) {
//32 HARQ processes supported in rel17
if ((ext3 != NULL) &&
(ext3->nrofHARQ_ProcessesForPDSCH_v1700 != NULL) &&
(*ext3->nrofHARQ_ProcessesForPDSCH_v1700 == NR_PDSCH_ServingCellConfig__ext3__nrofHARQ_ProcessesForPDSCH_v1700_n32))
return 32;
switch (n) {
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n2:
return 2;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n4:
return 4;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n6:
return 6;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n10:
return 10;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n12:
return 12;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n16:
return 16;
default:
return 8;
}
}
int get_nrofHARQ_ProcessesForPUSCH(struct NR_PUSCH_ServingCellConfig__ext3 *ext3) {
//32 HARQ processes supported in rel17
if ((ext3 != NULL) &&
(ext3->nrofHARQ_ProcessesForPUSCH_r17 != NULL) &&
(*ext3->nrofHARQ_ProcessesForPUSCH_r17 == NR_PUSCH_ServingCellConfig__ext3__nrofHARQ_ProcessesForPUSCH_r17_n32))
return 32;
return 16;
}
uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
const NR_UE_UL_BWP_t *UL_BWP,
const NR_CellGroupConfig_t *cg,
......@@ -3289,6 +3327,8 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
uint16_t numRBG = 0;
long rbg_size_config;
int num_entries = 0;
// Default values of DL and UL HARQ processes
uint8_t num_dl_harq = 8, num_ul_harq = 16;
NR_PDSCH_Config_t *pdsch_Config = DL_BWP ? DL_BWP->pdsch_Config : NULL;
NR_PUSCH_Config_t *pusch_Config = UL_BWP ? UL_BWP->pusch_Config : NULL;
......@@ -3296,7 +3336,7 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
NR_SRS_Config_t *srs_config = UL_BWP ? UL_BWP->srs_Config : NULL;
uint16_t N_RB = cset0_bwp_size;
if (DL_BWP)
if (DL_BWP) {
N_RB = get_rb_bwp_dci(format,
ss_type,
cset0_bwp_size,
......@@ -3305,10 +3345,23 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
UL_BWP->initial_BWPSize,
DL_BWP->initial_BWPSize);
if (DL_BWP->pdsch_servingcellconfig &&
DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH) {
num_dl_harq = get_nrofHARQ_ProcessesForPDSCH(*DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH,
DL_BWP->pdsch_servingcellconfig->ext3);
}
}
if (UL_BWP && UL_BWP->pusch_servingcellconfig) {
num_ul_harq = get_nrofHARQ_ProcessesForPUSCH(UL_BWP->pusch_servingcellconfig->ext3);
}
LOG_D(MAC, "In %s, num_dl_harq:%d, num_ul_harq:%d\n",__FUNCTION__, num_dl_harq, num_ul_harq);
switch(format) {
case NR_UL_DCI_FORMAT_0_0:
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20;
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4/5, PUSCH TPC 2 Time Domain assgnmt 4 --20/21
size += (num_ul_harq == 32 ? 21 : 20);
dci_pdu->frequency_domain_assignment.nbits = (uint8_t)ceil(log2((N_RB * (N_RB + 1)) >>1)); // Freq domain assignment -- hopping scenario to be updated
size += dci_pdu->frequency_domain_assignment.nbits;
if(alt_size >= size)
......@@ -3321,8 +3374,8 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
break;
case NR_UL_DCI_FORMAT_0_1:
/// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, ULSCH indicator 1 --16
size += 16;
/// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4/5, PUSCH TPC 2, ULSCH indicator 1 --16/17
size += (num_ul_harq == 32 ? 17 : 16);
// Carrier indicator
if (cg->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
dci_pdu->carrier_indicator.nbits=3;
......@@ -3457,12 +3510,12 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
break;
case NR_DL_DCI_FORMAT_1_0:
/// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28
/// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4/5, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28/29
// 3GPP TS 38.212 Section 7.3.1.0: DCI size alignment
// Size of DCI format 1_0 is given by the size of CORESET 0 if CORESET 0 is configured for the cell and the size
// of initial DL bandwidth part if CORESET 0 is not configured for the cell
size = 28;
size = (num_dl_harq == 32 ? 29 : 28);
dci_pdu->frequency_domain_assignment.nbits = (uint8_t)ceil(log2((N_RB * (N_RB + 1)) >> 1)); // Freq domain assignment
size += dci_pdu->frequency_domain_assignment.nbits;
if(ss_type == NR_SearchSpace__searchSpaceType_PR_ue_Specific && alt_size >= size)
......@@ -3542,7 +3595,7 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
size += 8;
}
// HARQ PID
size += 4;
size += (num_dl_harq == 32 ? 5 : 4);
// DAI
if (DL_BWP->pdsch_HARQ_ACK_Codebook && *DL_BWP->pdsch_HARQ_ACK_Codebook == NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) { // FIXME in case of more than one serving cell
dci_pdu->dai[0].nbits = 2;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ 7fd1a1e2
......@@ -58,6 +58,10 @@
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
extern int get_nrofHARQ_ProcessesForPDSCH(e_NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH n,
struct NR_PDSCH_ServingCellConfig__ext3 *ext3);
extern int get_nrofHARQ_ProcessesForPUSCH(struct NR_PUSCH_ServingCellConfig__ext3 *ext3);
//#define DEBUG_MIB
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
//#define DEBUG_EXTRACT_DCI
......@@ -2127,6 +2131,7 @@ bool get_downlink_ack(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, PUCCH_sche
NR_UE_HARQ_STATUS_t *current_harq;
int sched_frame,sched_slot;
int slots_per_frame;
int num_harq_processes = 16;
NR_UE_DL_BWP_t *current_DL_BWP = &mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = &mac->current_UL_BWP;
......@@ -2136,6 +2141,14 @@ bool get_downlink_ack(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, PUCCH_sche
number_of_code_word = 2;
}
//Look for 32 harq processes only if numharq = 32
if (current_DL_BWP->pdsch_servingcellconfig &&
current_DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH &&
current_DL_BWP->pdsch_servingcellconfig->ext3) {
num_harq_processes = 32;
}
int scs = current_UL_BWP->scs;
slots_per_frame = nr_slots_per_frame[scs];
......@@ -2144,7 +2157,7 @@ bool get_downlink_ack(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, PUCCH_sche
/* look for dl acknowledgment which should be done on current uplink slot */
for (int code_word = 0; code_word < number_of_code_word; code_word++) {
for (int dl_harq_pid = 0; dl_harq_pid < 16; dl_harq_pid++) {
for (int dl_harq_pid = 0; dl_harq_pid < num_harq_processes; dl_harq_pid++) {
current_harq = &mac->dl_harq_info[dl_harq_pid];
......@@ -2826,7 +2839,10 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
NR_UE_DL_BWP_t *current_DL_BWP = &mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = &mac->current_UL_BWP;
int N_RB;
if(current_DL_BWP)
// Default values of DL and UL HARQ processes
uint8_t num_dl_harq = 8, num_ul_harq = 16;
if(current_DL_BWP) {
N_RB = get_rb_bwp_dci(dci_format,
ss_type,
mac->type0_PDCCH_CSS_config.num_rbs,
......@@ -2834,9 +2850,22 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
current_DL_BWP->BWPSize,
current_UL_BWP->initial_BWPSize,
current_DL_BWP->initial_BWPSize);
else
if (current_DL_BWP->pdsch_servingcellconfig && current_DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH) {
num_dl_harq = get_nrofHARQ_ProcessesForPDSCH(*current_DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH,
current_DL_BWP->pdsch_servingcellconfig->ext3);
}
} else
N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
if (current_UL_BWP && current_UL_BWP->pusch_servingcellconfig) {
num_ul_harq = get_nrofHARQ_ProcessesForPUSCH(current_UL_BWP->pusch_servingcellconfig->ext3);
}
LOG_D(MAC, "In %s, num_dl_harq:%d, num_ul_harq:%d\n",__FUNCTION__, num_dl_harq, num_ul_harq);
LOG_D(MAC,"nr_extract_dci_info : dci_pdu %lx, size %d\n",*dci_pdu,dci_size);
switch(dci_format) {
case NR_DL_DCI_FORMAT_1_0:
......@@ -2963,12 +2992,17 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
//LOG_I(MAC, "In %s, NR_DL_DCI_FORMAT_1_0 pos:%d, dci_size:%d\n",__FUNCTION__, pos, dci_size);
// HARQ process number 4bit/5bits
pos+= (num_dl_harq == 32 ? 5: 4);
//LOG_I(MAC, "In %s, NR_DL_DCI_FORMAT_1_0 pos:%d, dci_size:%d\n",__FUNCTION__, pos, dci_size);
if (num_dl_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,(num_dl_harq == 32)?5:4,dci_size-pos,*dci_pdu);
#endif
// Downlink assignment index 2bit
......@@ -3105,9 +3139,12 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number - 4 bits
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// HARQ process number - 4 bits/5bits
pos+= (num_dl_harq == 32 ? 5: 4);
if (num_dl_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
// Downlink assignment index - 2 bits
pos+=2;
......@@ -3192,9 +3229,12 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// HARQ process number 4bit/5bit
pos+= (num_ul_harq == 32 ? 5: 4);
if (num_ul_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
......@@ -3261,12 +3301,15 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
// HARQ process number 4bit/5bit
pos+= (num_ul_harq == 32 ? 5: 4);
if (num_ul_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
//#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
//#endif
// TPC command for scheduled PUSCH  E2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
......@@ -3331,9 +3374,12 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
// Redundancy version 2bit
pos+=dci_pdu_rel15->rv2.nbits;
dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rv2.nbits)-1);
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// HARQ process number 4bit/5bit
pos+= (num_dl_harq == 32 ? 5: 4);
if (num_dl_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
// Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
......@@ -3416,9 +3462,12 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// HARQ process number 4bit/5bit
pos+= (num_ul_harq == 32 ? 5: 4);
if (num_ul_harq == 32)
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x1f;
else
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0x0f;
// 1st Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 7fd1a1e2
......@@ -1142,6 +1142,9 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
*dci_pdu = 0;
uint16_t alt_size = 0;
uint16_t N_RB;
// Default values of DL and UL HARQ processes
uint8_t num_dl_harq = 8, num_ul_harq = 16;
if(current_DL_BWP) {
N_RB = get_rb_bwp_dci(dci_format,
ss->searchSpaceType->present,
......@@ -1151,6 +1154,12 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
current_UL_BWP->initial_BWPSize,
current_DL_BWP->initial_BWPSize);
if (current_DL_BWP->pdsch_servingcellconfig &&
current_DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH) {
num_dl_harq = get_nrofHARQ_ProcessesForPDSCH(*current_DL_BWP->pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH,
current_DL_BWP->pdsch_servingcellconfig->ext3);
}
// computing alternative size for padding
dci_pdu_rel15_t temp_pdu;
if(dci_format == NR_DL_DCI_FORMAT_1_0)
......@@ -1163,6 +1172,11 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
else
N_RB = cset0_bwp_size;
if (current_UL_BWP &&
current_UL_BWP->pusch_servingcellconfig) {
num_ul_harq = get_nrofHARQ_ProcessesForPUSCH(current_UL_BWP->pusch_servingcellconfig->ext3);
}
int dci_size = nr_dci_size(current_DL_BWP, current_UL_BWP, CellGroup, dci_pdu_rel15, dci_format, rnti_type, coreset, bwp_id, ss->searchSpaceType->present, cset0_bwp_size, alt_size);
pdcch_dci_pdu->PayloadSizeBits = dci_size;
AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported");
......@@ -1284,10 +1298,16 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
pos += 2;
*dci_pdu |= (dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
LOG_D(NR_MAC, "RV %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->rv, 2, dci_size - pos, *dci_pdu);
// HARQ process number 4bit
pos += 4;
*dci_pdu |= ((dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos));
LOG_D(NR_MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 4, dci_size - pos, *dci_pdu);
// HARQ process number 4bit/5bit
if (num_dl_harq == 32) {
pos += 5;
*dci_pdu |= ((dci_pdu_rel15->harq_pid & 0x1f) << (dci_size - pos));
LOG_D(NR_MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 5, dci_size - pos, *dci_pdu);
} else {
pos += 4;
*dci_pdu |= ((dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos));
LOG_D(NR_MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 4, dci_size - pos, *dci_pdu);
}
// Downlink assignment index 2bit
pos += 2;
*dci_pdu |= ((dci_pdu_rel15->dai[0].val & 3) << (dci_size - pos));
......@@ -1390,9 +1410,14 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// Redundancy version 2bit
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv >> (1 - i)) & 1) << (dci_size - pos++);
// HARQ process number 4bit
for (int i = 0; i < 4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid >> (3 - i)) & 1) << (dci_size - pos++);
// HARQ process number 4bit/5bit
if (num_dl_harq == 32) {
for (int i = 0; i < 5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid >> (4 - i)) & 1) << (dci_size - pos++);
} else {
for (int i = 0; i < 4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid >> (3 - i)) & 1) << (dci_size - pos++);
}
// Downlink assignment index – 2 bits
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val >> (1 - i)) & 1) << (dci_size - pos++);
......@@ -1450,9 +1475,14 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// Redundancy version 2bit
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
// HARQ process number 4bit
pos+=4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// HARQ process number 4bit/5bit
if (num_ul_harq == 32) {
pos += 5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0x1f) << (dci_size - pos);
} else {
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
}
// TPC command for scheduled PUSCH – 2 bits
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc & 0x3) << (dci_size - pos);
......@@ -1503,9 +1533,14 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// Redundancy version 2bit
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
// HARQ process number 4bit
pos+=4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// HARQ process number 4bit/5bit
if (num_ul_harq == 32) {
pos += 5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0x1f) << (dci_size - pos);
} else {
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
}
// Padding bits
for (int a = pos; a < dci_size; a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding & 1) << (dci_size - pos++);
......@@ -1524,7 +1559,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->ndi = %i\n", dci_pdu_rel15->ndi);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_I(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->padding = %i\n", dci_pdu_rel15->padding);
......@@ -1566,9 +1601,14 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// Redundancy version 2bit
pos += 2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
// HARQ process number 4bit
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// HARQ process number 4bit/5bit
if (num_ul_harq == 32) {
pos += 5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0x1f) << (dci_size - pos);
} else {
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
}
// 1st Downlink assignment index
pos += dci_pdu_rel15->dai[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val & ((1 << dci_pdu_rel15->dai[0].nbits) - 1)) << (dci_size - pos);
......@@ -1691,9 +1731,14 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// Redundancy version 2bit
pos += dci_pdu_rel15->rv2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val & ((1 << dci_pdu_rel15->rv2.nbits) - 1)) << (dci_size - pos);
// HARQ process number 4bit
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// HARQ process number 4bit/5bit
if (num_dl_harq == 32) {
pos += 5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0x1f) << (dci_size - pos);
} else {
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
}
// Downlink assignment index
pos += dci_pdu_rel15->dai[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val & ((1 << dci_pdu_rel15->dai[0].nbits) - 1)) << (dci_size - pos);
......@@ -1924,25 +1969,6 @@ int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP) {
return -1;
}
int get_nrofHARQ_ProcessesForPDSCH(e_NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH n)
{
switch (n) {
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n2:
return 2;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n4:
return 4;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n6:
return 6;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n10:
return 10;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n12:
return 12;
case NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH_n16:
return 16;
default:
return 8;
}
}
void delete_nr_ue_data(NR_UE_info_t *UE, NR_COMMON_channels_t *ccPtr, uid_allocator_t *uia)
{
......@@ -2364,7 +2390,7 @@ void set_sched_pucch_list(NR_UE_sched_ctrl_t *sched_ctrl,
void create_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl,
const NR_PDSCH_ServingCellConfig_t *pdsch) {
const int nrofHARQ = pdsch && pdsch->nrofHARQ_ProcessesForPDSCH ?
get_nrofHARQ_ProcessesForPDSCH(*pdsch->nrofHARQ_ProcessesForPDSCH) : 8;
get_nrofHARQ_ProcessesForPDSCH(*pdsch->nrofHARQ_ProcessesForPDSCH, pdsch->ext3) : 8;
// add all available DL HARQ processes for this UE
AssertFatal(sched_ctrl->available_dl_harq.len == sched_ctrl->feedback_dl_harq.len
&& sched_ctrl->available_dl_harq.len == sched_ctrl->retrans_dl_harq.len,
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ 7fd1a1e2
......@@ -284,7 +284,9 @@ int get_spf(nfapi_nr_config_request_scf_t *cfg);
int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot);
int get_nrofHARQ_ProcessesForPDSCH(e_NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH n);
int get_nrofHARQ_ProcessesForPDSCH(e_NR_PDSCH_ServingCellConfig__nrofHARQ_ProcessesForPDSCH n,
struct NR_PDSCH_ServingCellConfig__ext3 *ext3);
int get_nrofHARQ_ProcessesForPUSCH(struct NR_PUSCH_ServingCellConfig__ext3 *ext3);
void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
int x_overhead,
......
openair2/RRC/NR/nr_rrc_config.c
View file @ 7fd1a1e2
......@@ -2742,6 +2742,9 @@ NR_CellGroupConfig_t *get_default_secondaryCellGroup(const NR_ServingCellConfigC
pusch_scc->ext1->maxMIMO_Layers = calloc(1, sizeof(*pusch_scc->ext1->maxMIMO_Layers));
*pusch_scc->ext1->maxMIMO_Layers = 1;
pusch_scc->ext1->processingType2Enabled = NULL;
pusch_scc->ext3 = NULL; /*calloc(1, sizeof(*pusch_scc->ext3));
pusch_scc->ext3->nrofHARQ_ProcessesForPUSCH_r17 = calloc(1, sizeof(*pusch_scc->ext3->nrofHARQ_ProcessesForPUSCH_r17));
*pusch_scc->ext3->nrofHARQ_ProcessesForPUSCH_r17 = NR_PUSCH_ServingCellConfig__ext3__nrofHARQ_ProcessesForPUSCH_r17_n32;*/
secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink = NULL;
......@@ -2762,6 +2765,10 @@ NR_CellGroupConfig_t *get_default_secondaryCellGroup(const NR_ServingCellConfigC
pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1, sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers));
*pdsch_servingcellconfig->ext1->maxMIMO_Layers = NR_MAX_SUPPORTED_DL_LAYERS;
pdsch_servingcellconfig->ext1->processingType2Enabled = NULL;
pdsch_servingcellconfig->ext3 = NULL; /*calloc(1, sizeof(*pdsch_servingcellconfig->ext3));
pdsch_servingcellconfig->ext3->nrofHARQ_ProcessesForPDSCH_v1700 = calloc(1, sizeof(*pdsch_servingcellconfig->ext3->nrofHARQ_ProcessesForPDSCH_v1700));
*pdsch_servingcellconfig->ext3->nrofHARQ_ProcessesForPDSCH_v1700 = NR_PDSCH_ServingCellConfig__ext3__nrofHARQ_ProcessesForPDSCH_v1700_n32;*/
secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig = NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig =
......
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