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Commit 884cbc7c authored by Rangaswami's avatar Rangaswami
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Corrected indentation and removed GES macro

parent 02be147d
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Showing with 613 additions and 637 deletions
cmake_targets/CMakeLists.txt
View file @ 884cbc7c
...@@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs ...@@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs
add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace")
add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace")
add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering")
add_boolean_option(GES_SUPPORT True "To enable the GES Code")
set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti)
add_library(ITTI add_library(ITTI
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
View file @ 884cbc7c
...@@ -71,131 +71,129 @@ ...@@ -71,131 +71,129 @@
// R: Reserved bit, set to zero. // R: Reserved bit, set to zero.
typedef struct { typedef struct {
uint8_t LCID: 6; // octet 1 [5:0] uint8_t LCID: 6; // octet 1 [5:0]
uint8_t F: 1; // octet 1 [6] uint8_t F: 1; // octet 1 [6]
uint8_t R: 1; // octet 1 [7] uint8_t R: 1; // octet 1 [7]
uint8_t L: 8; // octet 2 [7:0] uint8_t L: 8; // octet 2 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT;
typedef struct { typedef struct {
uint8_t LCID: 6; // octet 1 [5:0] uint8_t LCID: 6; // octet 1 [5:0]
uint8_t F: 1; // octet 1 [6] uint8_t F: 1; // octet 1 [6]
uint8_t R: 1; // octet 1 [7] uint8_t R: 1; // octet 1 [7]
uint8_t L1: 8; // octet 2 [7:0] uint8_t L1: 8; // octet 2 [7:0]
uint8_t L2: 8; // octet 3 [7:0] uint8_t L2: 8; // octet 3 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG;
typedef struct { typedef struct {
uint8_t LCID: 6; // octet 1 [5:0] uint8_t LCID: 6; // octet 1 [5:0]
uint8_t R: 2; // octet 1 [7:6] uint8_t R: 2; // octet 1 [7:6]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED;
// BSR MAC CEs // BSR MAC CEs
// TS 38.321 ch. 6.1.3.1 // TS 38.321 ch. 6.1.3.1
// Short BSR for a specific logical channel group ID // Short BSR for a specific logical channel group ID
typedef struct { typedef struct {
uint8_t Buffer_size: 5; // octet 1 LSB uint8_t Buffer_size: 5; // octet 1 LSB
uint8_t LcgID: 3; // octet 1 MSB uint8_t LcgID: 3; // octet 1 MSB
} __attribute__ ((__packed__)) NR_BSR_SHORT; } __attribute__ ((__packed__)) NR_BSR_SHORT;
typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED;
// Long BSR for all logical channel group ID // Long BSR for all logical channel group ID
typedef struct { typedef struct {
uint8_t Buffer_size7: 8; uint8_t Buffer_size7: 8;
uint8_t Buffer_size6: 8; uint8_t Buffer_size6: 8;
uint8_t Buffer_size5: 8; uint8_t Buffer_size5: 8;
uint8_t Buffer_size4: 8; uint8_t Buffer_size4: 8;
uint8_t Buffer_size3: 8; uint8_t Buffer_size3: 8;
uint8_t Buffer_size2: 8; uint8_t Buffer_size2: 8;
uint8_t Buffer_size1: 8; uint8_t Buffer_size1: 8;
uint8_t Buffer_size0: 8; uint8_t Buffer_size0: 8;
uint8_t LcgID0: 1; uint8_t LcgID0: 1;
uint8_t LcgID1: 1; uint8_t LcgID1: 1;
uint8_t LcgID2: 1; uint8_t LcgID2: 1;
uint8_t LcgID3: 1; uint8_t LcgID3: 1;
uint8_t LcgID4: 1; uint8_t LcgID4: 1;
uint8_t LcgID5: 1; uint8_t LcgID5: 1;
uint8_t LcgID6: 1; uint8_t LcgID6: 1;
uint8_t LcgID7: 1; uint8_t LcgID7: 1;
} __attribute__ ((__packed__)) NR_BSR_LONG; } __attribute__ ((__packed__)) NR_BSR_LONG;
typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED;
// 38.321 ch. 6.1.3.4 // 38.321 ch. 6.1.3.4
typedef struct { typedef struct {
uint8_t TA_COMMAND: 6; // octet 1 [5:0] uint8_t TA_COMMAND: 6; // octet 1 [5:0]
uint8_t TAGID: 2; // octet 1 [7:6] uint8_t TAGID: 2; // octet 1 [7:6]
} __attribute__ ((__packed__)) NR_MAC_CE_TA; } __attribute__ ((__packed__)) NR_MAC_CE_TA;
// single Entry PHR MAC CE // single Entry PHR MAC CE
// TS 38.321 ch. 6.1.3.8 // TS 38.321 ch. 6.1.3.8
typedef struct { typedef struct {
uint8_t PH: 6; uint8_t PH: 6;
uint8_t R1: 2; uint8_t R1: 2;
uint8_t PCMAX: 6; uint8_t PCMAX: 6;
uint8_t R2: 6; uint8_t R2: 6;
} __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE;
#ifdef GES_SUPPORT
// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
// 38.321 ch. 6.1.3.19 // 38.321 ch. 6.1.3.19
typedef struct { typedef struct {
uint8_t BWPID: 2; // octet 1 [1:0] uint8_t BWPID: 2; // octet 1 [1:0]
uint8_t CELLID: 5; // octet 1 [6:2] uint8_t CELLID: 5; // octet 1 [6:2]
uint8_t A_D: 1; // octet 1 [7] uint8_t A_D: 1; // octet 1 [7]
uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0]
uint8_t R: 4 // octet 2 [7:4] uint8_t R: 4; // octet 2 [7:4]
} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; } __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET;
//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE //TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE
typedef struct { typedef struct {
uint8_t CoresetId1: 3; //Octect 1 [2:0] uint8_t CoresetId1: 3; //Octect 1 [2:0]
uint8_t ServingCellId: 5; //Octect 1 [7:3] uint8_t ServingCellId: 5; //Octect 1 [7:3]
uint8_t TciStateId: 7; //Octect 2 [6:0] uint8_t TciStateId: 7; //Octect 2 [6:0]
uint8_t CoresetId2: 1; //Octect 2 [7] uint8_t CoresetId2: 1; //Octect 2 [7]
} __attribute__ ((__packed__)) NR_TCI_PDCCH; } __attribute__ ((__packed__)) NR_TCI_PDCCH;
//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
typedef struct { typedef struct {
uint8_t BWP_Id: 2; //Octect 1 [1:0] uint8_t BWP_Id: 2; //Octect 1 [1:0]
uint8_t ServingCellId: 5; //Octect 1 [6:2] uint8_t ServingCellId: 5; //Octect 1 [6:2]
uint8_t R: 1; //Octect 1 [7] uint8_t R: 1; //Octect 1 [7]
uint8_t T[]; //Octects 2 to MAX TCI States/8 uint8_t T[]; //Octects 2 to MAX TCI States/8
} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; } __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI;
//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE //TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
typedef struct { typedef struct {
uint8_t BWP_Id: 2; //Octect 1 [1:0] uint8_t BWP_Id: 2; //Octect 1 [1:0]
uint8_t ServingCellId: 5; //Octect 1 [6:2] uint8_t ServingCellId: 5; //Octect 1 [6:2]
uint8_t R1: 1; //Octect 1 [7] uint8_t R1: 1; //Octect 1 [7]
uint8_t S0: 1; //Octect 2 [0] uint8_t S0: 1; //Octect 2 [0]
uint8_t S1: 1; //Octect 2 [1] uint8_t S1: 1; //Octect 2 [1]
uint8_t S2: 1; //Octect 2 [2] uint8_t S2: 1; //Octect 2 [2]
uint8_t S3: 1; //Octect 2 [3] uint8_t S3: 1; //Octect 2 [3]
uint8_t R2: 4; //Octect 2 [7:4] uint8_t R2: 4; //Octect 2 [7:4]
} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; } __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING;
//TS 38.321 sec 6.1.3.12 //TS 38.321 sec 6.1.3.12
//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
typedef struct { typedef struct {
uint8_t BWP_ID: 2; uint8_t BWP_ID: 2;
uint8_t SCID: 5; uint8_t SCID: 5;
uint8_t A_D: 1; uint8_t A_D: 1;
uint8_t SP_CSI_RSID: 6; uint8_t SP_CSI_RSID: 6;
uint8_t IM: 1; uint8_t IM: 1;
uint8_t R1: 1; uint8_t R1: 1;
uint8_t SP_CSI_IMID: 6; uint8_t SP_CSI_IMID: 6;
uint8_t R2: 2; uint8_t R2: 2;
struct TCI_S { struct TCI_S {
uint8_t TCI_STATE_ID: 6; uint8_t TCI_STATE_ID: 6;
uint8_t R: 2; uint8_t R: 2;
} __attribute__ ((__packed__)) TCI_STATE; } __attribute__ ((__packed__)) TCI_STATE;
} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; } __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE;
#endif
//* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *//
// - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU
...@@ -206,30 +204,30 @@ typedef struct { ...@@ -206,30 +204,30 @@ typedef struct {
/*!\brief RAR MAC subheader with RAPID */ /*!\brief RAR MAC subheader with RAPID */
typedef struct { typedef struct {
uint8_t RAPID: 6; uint8_t RAPID: 6;
uint8_t T: 1; uint8_t T: 1;
uint8_t E: 1; uint8_t E: 1;
} __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID;
/*!\brief RAR MAC subheader with Backoff Indicator */ /*!\brief RAR MAC subheader with Backoff Indicator */
typedef struct { typedef struct {
uint8_t BI: 4; uint8_t BI: 4;
uint8_t R: 2; uint8_t R: 2;
uint8_t T: 1; uint8_t T: 1;
uint8_t E: 1; uint8_t E: 1;
} __attribute__ ((__packed__)) NR_RA_HEADER_BI; } __attribute__ ((__packed__)) NR_RA_HEADER_BI;
// TS 38.321 ch. 6.2.3 // TS 38.321 ch. 6.2.3
typedef struct { typedef struct {
uint8_t TA1: 7; // octet 1 [6:0] uint8_t TA1: 7; // octet 1 [6:0]
uint8_t R: 1; // octet 1 [7] uint8_t R: 1; // octet 1 [7]
uint8_t UL_GRANT_1: 3; // octet 2 [2:0] uint8_t UL_GRANT_1: 3; // octet 2 [2:0]
uint8_t TA2: 5; // octet 2 [7:3] uint8_t TA2: 5; // octet 2 [7:3]
uint8_t UL_GRANT_2: 8; // octet 3 [7:0] uint8_t UL_GRANT_2: 8; // octet 3 [7:0]
uint8_t UL_GRANT_3: 8; // octet 4 [7:0] uint8_t UL_GRANT_3: 8; // octet 4 [7:0]
uint8_t UL_GRANT_4: 8; // octet 5 [7:0] uint8_t UL_GRANT_4: 8; // octet 5 [7:0]
uint8_t TCRNTI_1: 8; // octet 6 [7:0] uint8_t TCRNTI_1: 8; // octet 6 [7:0]
uint8_t TCRNTI_2: 8; // octet 7 [7:0] uint8_t TCRNTI_2: 8; // octet 7 [7:0]
} __attribute__ ((__packed__)) NR_MAC_RAR; } __attribute__ ((__packed__)) NR_MAC_RAR;
// 38.321 ch6.2.1, 38.331 // 38.321 ch6.2.1, 38.331
...@@ -273,9 +271,9 @@ typedef struct { ...@@ -273,9 +271,9 @@ typedef struct {
#define UL_SCH_LCID_L_BSR 0x3E #define UL_SCH_LCID_L_BSR 0x3E
#define UL_SCH_LCID_PADDING 0x3F #define UL_SCH_LCID_PADDING 0x3F
#define NR_MAX_NUM_LCID 32 #define NR_MAX_NUM_LCID 32
#define NR_MAX_NUM_LCGID 8 #define NR_MAX_NUM_LCGID 8
#define MAX_RLC_SDU_SUBHEADER_SIZE 3 #define MAX_RLC_SDU_SUBHEADER_SIZE 3
#endif /*__LAYER2_MAC_H__ */ #endif /*__LAYER2_MAC_H__ */
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ 884cbc7c
...@@ -47,12 +47,10 @@ ...@@ -47,12 +47,10 @@
//////////////////////////////////////////////////////// ////////////////////////////////////////////////////////
/////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) */////
//////////////////////////////////////////////////////// ////////////////////////////////////////////////////////
#ifdef GES_SUPPORT
#define OCTET 8 #define OCTET 8
#define HALFWORD 16 #define HALFWORD 16
#define WORD 32 #define WORD 32
//#define SIZE_OF_POINTER sizeof (void *) //#define SIZE_OF_POINTER sizeof (void *)
#endif
int nr_generate_dlsch_pdu(module_id_t module_idP, int nr_generate_dlsch_pdu(module_id_t module_idP,
unsigned char *sdus_payload, unsigned char *sdus_payload,
...@@ -63,299 +61,284 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, ...@@ -63,299 +61,284 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
unsigned char drx_cmd, unsigned char drx_cmd,
unsigned char *ue_cont_res_id, unsigned char *ue_cont_res_id,
unsigned short post_padding) { unsigned short post_padding) {
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu;
unsigned char *dlsch_buffer_ptr = sdus_payload;
NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; uint8_t last_size = 0;
unsigned char * dlsch_buffer_ptr = sdus_payload; int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0;
uint8_t last_size = 0; // MAC CEs
int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; uint8_t mac_header_control_elements[16], *ce_ptr;
// MAC CEs ce_ptr = &mac_header_control_elements[0];
uint8_t mac_header_control_elements[16], *ce_ptr; uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI
ce_ptr = &mac_header_control_elements[0]; gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
#ifdef GES_SUPPORT NR_UE_list_t *UE_list = &gNB_mac->UE_list;
uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI NR_UE_sched_ctrl_t *ue_sched_ctl = NULL;
gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id];
NR_UE_list_t *UE_list = &gNB_mac->UE_list; ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]);
NR_UE_sched_ctrl_t *ue_sched_ctl = NULL;
//NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; // 1) Compute MAC CE and related subheaders
ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]);
#endif // DRX command subheader (MAC CE size 0)
if (drx_cmd != 255) {
// 1) Compute MAC CE and related subheaders mac_pdu_ptr->R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_DRX;
// DRX command subheader (MAC CE size 0) //last_size = 1;
if (drx_cmd != 255) { mac_pdu_ptr++;
mac_pdu_ptr->R = 0; }
mac_pdu_ptr->LCID = DL_SCH_LCID_DRX;
//last_size = 1; // Timing Advance subheader
mac_pdu_ptr++; /* This was done only when timing_advance_cmd != 31
} // now TA is always send when ta_timer resets regardless of its value
// this is done to avoid issues with the timeAlignmentTimer which is
// Timing Advance subheader // supposed to monitor if the UE received TA or not */
/* This was done only when timing_advance_cmd != 31 if (gNB->ta_len) {
// now TA is always send when ta_timer resets regardless of its value mac_pdu_ptr->R = 0;
// this is done to avoid issues with the timeAlignmentTimer which is mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND;
// supposed to monitor if the UE received TA or not */ //last_size = 1;
if (gNB->ta_len) { mac_pdu_ptr++;
mac_pdu_ptr->R = 0; // TA MAC CE (1 octet)
mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; timing_advance_cmd = gNB->ta_command;
//last_size = 1; AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd);
mac_pdu_ptr++; ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f;
// TA MAC CE (1 octet) if (gNB->tag->tag_Id != 0) {
timing_advance_cmd = gNB->ta_command; tag_id = gNB->tag->tag_Id;
AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id;
((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f;
if (gNB->tag->tag_Id != 0) {
tag_id = gNB->tag->tag_Id;
((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id;
}
LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id);
mac_ce_size = sizeof(NR_MAC_CE_TA);
// Copying bytes for MAC CEs to the mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
ce_ptr += mac_ce_size;
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
// Contention resolution fixed subheader and MAC CE
if (ue_cont_res_id) {
mac_pdu_ptr->R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID;
mac_pdu_ptr++;
//last_size = 1;
// contention resolution identity MAC ce has a fixed 48 bit size
// this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits,
// it contains the first 48 bits of the UL CCCH SDU
LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n",
ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2],
ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]);
// Copying bytes (6 octects) to CEs pointer
mac_ce_size = 6;
memcpy(ce_ptr, ue_cont_res_id, mac_ce_size);
// Copying bytes for MAC CEs to mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
ce_ptr += mac_ce_size;
mac_pdu_ptr += (unsigned char) mac_ce_size;
} }
#ifdef GES_SUPPORT LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id);
mac_ce_size = sizeof(NR_MAC_CE_TA);
//TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation // Copying bytes for MAC CEs to the mac pdu pointer
if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
//filling subheader ce_ptr += mac_ce_size;
mac_pdu_ptr->R = 0; mac_pdu_ptr += (unsigned char) mac_ce_size;
mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; }
mac_pdu_ptr++;
//Creating the instance of CE structure // Contention resolution fixed subheader and MAC CE
NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; if (ue_cont_res_id) {
//filling the CE structre mac_pdu_ptr->R = 0;
nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID;
nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits mac_pdu_ptr++;
nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits //last_size = 1;
nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit // contention resolution identity MAC ce has a fixed 48 bit size
LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits,
mac_ce_size = sizeof(NR_TCI_PDCCH); // it contains the first 48 bits of the UL CCCH SDU
// Copying bytes for MAC CEs to the mac pdu pointer LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n",
memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2],
//incrementing the PDU pointer ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]);
mac_pdu_ptr += (unsigned char) mac_ce_size; // Copying bytes (6 octects) to CEs pointer
mac_ce_size = 6;
memcpy(ce_ptr, ue_cont_res_id, mac_ce_size);
// Copying bytes for MAC CEs to mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
ce_ptr += mac_ce_size;
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
//TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation
if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) {
//filling subheader
mac_pdu_ptr->R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH;
mac_pdu_ptr++;
//Creating the instance of CE structure
NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH;
//filling the CE structre
nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble
nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits
nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits
nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit
LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId);
mac_ce_size = sizeof(NR_TCI_PDCCH);
// Copying bytes for MAC CEs to the mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size);
//incrementing the PDU pointer
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
//TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) {
//filling the subheader
mac_pdu_ptr->R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT;
mac_pdu_ptr++;
//creating the instance of CE structure
NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact;
//filling the CE structure
nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs
nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits
nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0];
nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1];
nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2];
nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3];
nr_PUCCH_CSI_reportingActDeact.R2 = 0;
mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING);
// Copying MAC CE data to the mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size);
//incrementing the PDU pointer
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) {
//Computing the number of octects to be allocated for Flexible array member
//of MAC CE structure
uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory
//filling the subheader
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
last_size = 2;
//Incrementing the PDU pointer
mac_pdu_ptr += last_size;
//allocating memory for CE Structure
NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//initializing to zero
memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//filling the CE Structure
nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits
nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits
for(i = 0; i < (num_octects * 8); i++) {
if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i])
nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8));
} }
//TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { //Copying bytes for MAC CEs to the mac pdu pointer
//filling the subheader memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size);
mac_pdu_ptr->R = 0; //incrementing the mac pdu pointer
mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; mac_pdu_ptr += (unsigned char) mac_ce_size;
mac_pdu_ptr++; //freeing the allocated memory
//creating the instance of CE structure free(nr_UESpec_TCI_StateInd_PDSCH);
NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; }
//filling the CE structure
nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE
nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) {
nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; //Computing the number of octects to be allocated for Flexible array member
nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; //of MAC CE structure
nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory
nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; //filling the subheader
nr_PUCCH_CSI_reportingActDeact.R2 = 0; ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
// Copying MAC CE data to the mac pdu pointer ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL;
memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
//incrementing the PDU pointer last_size = 2;
mac_pdu_ptr += (unsigned char) mac_ce_size; //Incrementing the PDU pointer
mac_pdu_ptr += last_size;
//allocating memory for CE structure
NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//initializing to zero
memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//filling the CE Structure
nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits
nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits
nr_Aperiodic_CSI_Trigger->R = 0;
for(i = 0; i < (num_octects * 8); i++) {
if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i])
nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8));
} }
//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { // Copying bytes for MAC CEs to the mac pdu pointer
//Computing the number of octects to be allocated for Flexible array member memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size);
//of MAC CE structure //incrementing the mac pdu pointer
uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory mac_pdu_ptr += (unsigned char) mac_ce_size;
//freeing the allocated memory
//filling the subheader free(nr_Aperiodic_CSI_Trigger);
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; }
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) {
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
last_size = 2; ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT;
//Incrementing the PDU pointer mac_pdu_ptr++;
mac_pdu_ptr += last_size; ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact;
//allocating memory for CE Structure ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits
NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits
//initializing to zero ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits
memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0;
//filling the CE Structure LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid,
nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id);
nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET);
for(i = 0; i < (num_octects * 8); i++) { mac_pdu_ptr += (unsigned char) mac_ce_size;
if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) }
nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8));
} if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) {
mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); mac_pdu_ptr->R = 0;
//Copying bytes for MAC CEs to the mac pdu pointer mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT;
memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); mac_pdu_ptr++;
//incrementing the mac pdu pointer CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce;
mac_pdu_ptr += (unsigned char) mac_ce_size; csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact;
//freeing the allocated memory csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId;
free(nr_UESpec_TCI_StateInd_PDSCH); csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id;
csi_rs_im_act_deact_ce.R1 = 0;
csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent
csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id;
if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present
csi_rs_im_act_deact_ce.R2 = 0;
csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id;
mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE );
} else {
mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1;
} }
//TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size);
if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { mac_pdu_ptr += (unsigned char) mac_ce_size;
//Computing the number of octects to be allocated for Flexible array member
//of MAC CE structure
uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory
//filling the subheader
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
last_size = 2;
//Incrementing the PDU pointer
mac_pdu_ptr += last_size;
//allocating memory for CE structure
NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//initializing to zero
memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
//filling the CE Structure
nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits
nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits
nr_Aperiodic_CSI_Trigger->R = 0;
for(i = 0; i < (num_octects * 8); i++) {
if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i])
nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8));
}
mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
// Copying bytes for MAC CEs to the mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size);
//incrementing the mac pdu pointer
mac_pdu_ptr += (unsigned char) mac_ce_size;
//freeing the allocated memory
free(nr_Aperiodic_CSI_Trigger);
}
if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; mac_ce_size = sizeof ( struct TCI_S);
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT;
mac_pdu_ptr++;
((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact;
((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits
((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits
((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits
((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0;
LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id);
mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET);
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) {
mac_pdu_ptr->R = 0; csi_rs_im_act_deact_ce.TCI_STATE.R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F;
mac_pdu_ptr++; memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size);
CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce;
csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact;
csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId;
csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id;
csi_rs_im_act_deact_ce.R1 = 0;
csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent
csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id;
if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present
csi_rs_im_act_deact_ce.R2 = 0;
csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id;
mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE );
} else {
mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1;
}
memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size);
mac_pdu_ptr += (unsigned char) mac_ce_size; mac_pdu_ptr += (unsigned char) mac_ce_size;
}
if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1
mac_ce_size = sizeof ( struct TCI_S);
for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) {
csi_rs_im_act_deact_ce.TCI_STATE.R = 0;
csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F;
memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size);
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
}
} }
}
#endif
// 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs
// 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs for (i = 0; i < num_sdus; i++) {
for (i = 0; i < num_sdus; i++) { LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);
LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);
if (sdu_lengths[i] < 128) {
if (sdu_lengths[i] < 128) { ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i];
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i];
((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; last_size = 2;
last_size = 2;
} else {
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i];
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff;
last_size = 3;
}
mac_pdu_ptr += last_size;
// 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]);
dlsch_buffer_ptr += sdu_lengths[i];
mac_pdu_ptr += sdu_lengths[i];
}
// 4) Compute final offset for padding
if (post_padding > 0) {
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING;
mac_pdu_ptr++;
} else { } else {
// no MAC subPDU with padding ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i];
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f;
((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff;
last_size = 3;
} }
// compute final offset mac_pdu_ptr += last_size;
offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]);
//printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); dlsch_buffer_ptr += sdu_lengths[i];
mac_pdu_ptr += sdu_lengths[i];
return offset; }
// 4) Compute final offset for padding
if (post_padding > 0) {
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING;
mac_pdu_ptr++;
} else {
// no MAC subPDU with padding
}
// compute final offset
offset = ((unsigned char *) mac_pdu_ptr - mac_pdu);
//printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu));
return offset;
} }
/* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 884cbc7c
...@@ -76,325 +76,321 @@ ...@@ -76,325 +76,321 @@
#define NR_NB_RA_PROC_MAX 4 #define NR_NB_RA_PROC_MAX 4
typedef enum { typedef enum {
RA_IDLE = 0, RA_IDLE = 0,
Msg2 = 1, Msg2 = 1,
WAIT_Msg3 = 2, WAIT_Msg3 = 2,
Msg4 = 3, Msg4 = 3,
WAIT_Msg4_ACK = 4 WAIT_Msg4_ACK = 4
} RA_gNB_state_t; } RA_gNB_state_t;
/*! \brief gNB template for the Random access information */ /*! \brief gNB template for the Random access information */
typedef struct { typedef struct {
/// Flag to indicate this process is active /// Flag to indicate this process is active
RA_gNB_state_t state; RA_gNB_state_t state;
/// BWP id of RA process /// BWP id of RA process
int bwp_id; int bwp_id;
/// CORESET0 configured flag /// CORESET0 configured flag
int coreset0_configured; int coreset0_configured;
/// Slot where preamble was received /// Slot where preamble was received
uint8_t preamble_slot; uint8_t preamble_slot;
/// Subframe where Msg2 is to be sent /// Subframe where Msg2 is to be sent
uint8_t Msg2_slot; uint8_t Msg2_slot;
/// Frame where Msg2 is to be sent /// Frame where Msg2 is to be sent
frame_t Msg2_frame; frame_t Msg2_frame;
/// Subframe where Msg3 is to be sent /// Subframe where Msg3 is to be sent
sub_frame_t Msg3_slot; sub_frame_t Msg3_slot;
/// Frame where Msg3 is to be sent /// Frame where Msg3 is to be sent
frame_t Msg3_frame; frame_t Msg3_frame;
/// Msg3 time domain allocation index /// Msg3 time domain allocation index
uint8_t Msg3_tda_id; uint8_t Msg3_tda_id;
/// Subframe where Msg4 is to be sent /// Subframe where Msg4 is to be sent
sub_frame_t Msg4_slot; sub_frame_t Msg4_slot;
/// Frame where Msg4 is to be sent /// Frame where Msg4 is to be sent
frame_t Msg4_frame; frame_t Msg4_frame;
/// harq_pid used for Msg4 transmission /// harq_pid used for Msg4 transmission
uint8_t harq_pid; uint8_t harq_pid;
/// UE RNTI allocated during RAR /// UE RNTI allocated during RAR
rnti_t rnti; rnti_t rnti;
/// RA RNTI allocated from received PRACH /// RA RNTI allocated from received PRACH
uint16_t RA_rnti; uint16_t RA_rnti;
/// Received preamble_index /// Received preamble_index
uint8_t preamble_index; uint8_t preamble_index;
/// Received UE Contention Resolution Identifier /// Received UE Contention Resolution Identifier
uint8_t cont_res_id[6]; uint8_t cont_res_id[6];
/// Timing offset indicated by PHY /// Timing offset indicated by PHY
int16_t timing_offset; int16_t timing_offset;
/// Timeout for RRC connection /// Timeout for RRC connection
int16_t RRC_timer; int16_t RRC_timer;
/// Msg3 first RB /// Msg3 first RB
uint8_t msg3_first_rb; uint8_t msg3_first_rb;
/// Msg3 number of RB /// Msg3 number of RB
uint8_t msg3_nb_rb; uint8_t msg3_nb_rb;
/// Msg3 TPC command /// Msg3 TPC command
uint8_t msg3_TPC; uint8_t msg3_TPC;
/// Msg3 ULdelay command /// Msg3 ULdelay command
uint8_t msg3_ULdelay; uint8_t msg3_ULdelay;
/// Msg3 cqireq command /// Msg3 cqireq command
uint8_t msg3_cqireq; uint8_t msg3_cqireq;
/// Round of Msg3 HARQ /// Round of Msg3 HARQ
uint8_t msg3_round; uint8_t msg3_round;
/// Msg3 pusch pdu /// Msg3 pusch pdu
nfapi_nr_pusch_pdu_t pusch_pdu; nfapi_nr_pusch_pdu_t pusch_pdu;
/// TBS used for Msg4 /// TBS used for Msg4
int msg4_TBsize; int msg4_TBsize;
/// MCS used for Msg4 /// MCS used for Msg4
int msg4_mcs; int msg4_mcs;
/// RA search space /// RA search space
NR_SearchSpace_t *ra_ss; NR_SearchSpace_t *ra_ss;
} NR_RA_t; } NR_RA_t;
/*! \brief gNB common channels */ /*! \brief gNB common channels */
typedef struct { typedef struct {
int physCellId; int physCellId;
int p_gNB; int p_gNB;
int Ncp; int Ncp;
int nr_band; int nr_band;
lte_frame_type_t frame_type; lte_frame_type_t frame_type;
uint64_t dl_CarrierFreq; uint64_t dl_CarrierFreq;
NR_BCCH_BCH_Message_t *mib; NR_BCCH_BCH_Message_t *mib;
NR_ServingCellConfigCommon_t *ServingCellConfigCommon; NR_ServingCellConfigCommon_t *ServingCellConfigCommon;
NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; NR_ARFCN_ValueEUTRA_t ul_CarrierFreq;
long ul_Bandwidth; long ul_Bandwidth;
/// Outgoing MIB PDU for PHY /// Outgoing MIB PDU for PHY
MIB_PDU MIB_pdu; MIB_PDU MIB_pdu;
/// Outgoing BCCH pdu for PHY /// Outgoing BCCH pdu for PHY
BCCH_PDU BCCH_pdu; BCCH_PDU BCCH_pdu;
/// Outgoing BCCH DCI allocation /// Outgoing BCCH DCI allocation
uint32_t BCCH_alloc_pdu; uint32_t BCCH_alloc_pdu;
/// Outgoing CCCH pdu for PHY /// Outgoing CCCH pdu for PHY
CCCH_PDU CCCH_pdu; CCCH_PDU CCCH_pdu;
/// Outgoing PCCH DCI allocation /// Outgoing PCCH DCI allocation
uint32_t PCCH_alloc_pdu; uint32_t PCCH_alloc_pdu;
/// Outgoing PCCH pdu for PHY /// Outgoing PCCH pdu for PHY
PCCH_PDU PCCH_pdu; PCCH_PDU PCCH_pdu;
/// Outgoing RAR pdu for PHY /// Outgoing RAR pdu for PHY
RAR_PDU RAR_pdu; RAR_PDU RAR_pdu;
/// Template for RA computations /// Template for RA computations
NR_RA_t ra[NR_NB_RA_PROC_MAX]; NR_RA_t ra[NR_NB_RA_PROC_MAX];
/// VRB map for common channels /// VRB map for common channels
uint8_t vrb_map[100]; uint8_t vrb_map[100];
/// VRB map for common channels and retransmissions by PHICH /// VRB map for common channels and retransmissions by PHICH
uint8_t vrb_map_UL[100]; uint8_t vrb_map_UL[100];
/// number of subframe allocation pattern available for MBSFN sync area /// number of subframe allocation pattern available for MBSFN sync area
uint8_t num_sf_allocation_pattern; uint8_t num_sf_allocation_pattern;
} NR_COMMON_channels_t; } NR_COMMON_channels_t;
#ifdef GES_SUPPORT
// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
typedef struct sp_zp_csirs { typedef struct sp_zp_csirs {
bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled
bool act_deact; //Activation/Deactivation indication bool act_deact; //Activation/Deactivation indication
uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies
uint8_t bwpid; //Downlink BWP id uint8_t bwpid; //Downlink BWP id
uint8_t rsc_id; //SP ZP CSI-RS resource set uint8_t rsc_id; //SP ZP CSI-RS resource set
} sp_zp_csirs_t; } sp_zp_csirs_t;
//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
#define MAX_CSI_RESOURCE_SET 64 #define MAX_CSI_RESOURCE_SET 64
typedef struct csi_rs_im { typedef struct csi_rs_im {
bool is_scheduled; bool is_scheduled;
bool act_deact; bool act_deact;
uint8_t serv_cellid; uint8_t serv_cellid;
uint8_t bwp_id; uint8_t bwp_id;
bool im; bool im;
uint8_t csi_im_rsc_id; uint8_t csi_im_rsc_id;
uint8_t nzp_csi_rsc_id; uint8_t nzp_csi_rsc_id;
uint8_t nb_tci_resource_set_id; uint8_t nb_tci_resource_set_id;
uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ];
} csi_rs_im_t; } csi_rs_im_t;
typedef struct pdcchStateInd { typedef struct pdcchStateInd {
bool is_scheduled; bool is_scheduled;
uint8_t servingCellId; uint8_t servingCellId;
uint8_t coresetId; uint8_t coresetId;
uint8_t tciStateId; uint8_t tciStateId;
} pdcchStateInd_t; } pdcchStateInd_t;
typedef struct SPCSIReportingpucch { typedef struct SPCSIReportingpucch {
bool is_scheduled; bool is_scheduled;
uint8_t servingCellId; uint8_t servingCellId;
uint8_t bwpId; uint8_t bwpId;
bool s0tos3_actDeact[4]; bool s0tos3_actDeact[4];
} SPCSIReportingpucch_t; } SPCSIReportingpucch_t;
#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 #define MAX_APERIODIC_TRIGGER_STATES 128 //38.331
typedef struct aperiodicCSI_triggerStateSelection { typedef struct aperiodicCSI_triggerStateSelection {
bool is_scheduled; bool is_scheduled;
uint8_t servingCellId; uint8_t servingCellId;
uint8_t bwpId; uint8_t bwpId;
uint8_t highestTriggerStateSelected; uint8_t highestTriggerStateSelected;
bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES];
} aperiodicCSI_triggerStateSelection_t; } aperiodicCSI_triggerStateSelection_t;
#define MAX_TCI_STATES 128 //38.331 #define MAX_TCI_STATES 128 //38.331
typedef struct pdschTciStatesActDeact { typedef struct pdschTciStatesActDeact {
bool is_scheduled; bool is_scheduled;
uint8_t servingCellId; uint8_t servingCellId;
uint8_t bwpId; uint8_t bwpId;
uint8_t highestTciStateActivated; uint8_t highestTciStateActivated;
bool tciStateActDeact[MAX_TCI_STATES]; bool tciStateActDeact[MAX_TCI_STATES];
} pdschTciStatesActDeact_t; } pdschTciStatesActDeact_t;
typedef struct UE_info { typedef struct UE_info {
sp_zp_csirs_t sp_zp_csi_rs; sp_zp_csirs_t sp_zp_csi_rs;
csi_rs_im_t csi_im; csi_rs_im_t csi_im;
pdcchStateInd_t pdcch_state_ind; pdcchStateInd_t pdcch_state_ind;
SPCSIReportingpucch_t SP_CSI_reporting_pucch; SPCSIReportingpucch_t SP_CSI_reporting_pucch;
aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger;
pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact;
} NR_UE_mac_ce_ctrl_t; } NR_UE_mac_ce_ctrl_t;
#endif
/*! \brief scheduling control information set through an API (not used)*/ /*! \brief scheduling control information set through an API (not used)*/
typedef struct { typedef struct {
int dummy; int dummy;
#ifdef GES_SUPPORT NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
#endif
} NR_UE_sched_ctrl_t; } NR_UE_sched_ctrl_t;
/*! \brief UE list used by gNB to order UEs/CC for scheduling*/ /*! \brief UE list used by gNB to order UEs/CC for scheduling*/
typedef struct { typedef struct {
DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB];
/// scheduling control info /// scheduling control info
UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB];
int next[MAX_MOBILES_PER_GNB]; int next[MAX_MOBILES_PER_GNB];
int head; int head;
int next_ul[MAX_MOBILES_PER_GNB]; int next_ul[MAX_MOBILES_PER_GNB];
int head_ul; int head_ul;
int avail; int avail;
int num_UEs; int num_UEs;
boolean_t active[MAX_MOBILES_PER_GNB]; boolean_t active[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
} NR_UE_list_t; } NR_UE_list_t;
/*! \brief top level eNB MAC structure */ /*! \brief top level eNB MAC structure */
typedef struct gNB_MAC_INST_s { typedef struct gNB_MAC_INST_s {
/// Ethernet parameters for northbound midhaul interface /// Ethernet parameters for northbound midhaul interface
eth_params_t eth_params_n; eth_params_t eth_params_n;
/// Ethernet parameters for fronthaul interface /// Ethernet parameters for fronthaul interface
eth_params_t eth_params_s; eth_params_t eth_params_s;
/// Module /// Module
module_id_t Mod_id; module_id_t Mod_id;
/// frame counter /// frame counter
frame_t frame; frame_t frame;
/// slot counter /// slot counter
int slot; int slot;
/// timing advance group /// timing advance group
NR_TAG_t *tag; NR_TAG_t *tag;
/// Pointer to IF module instance for PHY /// Pointer to IF module instance for PHY
NR_IF_Module_t *if_inst; NR_IF_Module_t *if_inst;
/// TA command /// TA command
int ta_command; int ta_command;
/// MAC CE flag indicating TA length /// MAC CE flag indicating TA length
int ta_len; int ta_len;
/// Common cell resources /// Common cell resources
NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; NR_COMMON_channels_t common_channels[NFAPI_CC_MAX];
/// current PDU index (BCH,DLSCH) /// current PDU index (BCH,DLSCH)
uint16_t pdu_index[NFAPI_CC_MAX]; uint16_t pdu_index[NFAPI_CC_MAX];
/// NFAPI Config Request Structure /// NFAPI Config Request Structure
nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX];
/// NFAPI DL Config Request Structure /// NFAPI DL Config Request Structure
nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX];
/// NFAPI UL TTI Request Structure (this is from the new SCF specs) /// NFAPI UL TTI Request Structure (this is from the new SCF specs)
nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX];
/// NFAPI HI/DCI0 Config Request Structure /// NFAPI HI/DCI0 Config Request Structure
nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX];
/// NFAPI DL PDU structure /// NFAPI DL PDU structure
nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX];
NR_UE_list_t UE_list; NR_UE_list_t UE_list;
/// UL handle /// UL handle
uint32_t ul_handle; uint32_t ul_handle;
// MAC function execution peformance profiler // MAC function execution peformance profiler
/// processing time of eNB scheduler /// processing time of eNB scheduler
time_stats_t eNB_scheduler; time_stats_t eNB_scheduler;
/// processing time of eNB scheduler for SI /// processing time of eNB scheduler for SI
time_stats_t schedule_si; time_stats_t schedule_si;
/// processing time of eNB scheduler for Random access /// processing time of eNB scheduler for Random access
time_stats_t schedule_ra; time_stats_t schedule_ra;
/// processing time of eNB ULSCH scheduler /// processing time of eNB ULSCH scheduler
time_stats_t schedule_ulsch; time_stats_t schedule_ulsch;
/// processing time of eNB DCI generation /// processing time of eNB DCI generation
time_stats_t fill_DLSCH_dci; time_stats_t fill_DLSCH_dci;
/// processing time of eNB MAC preprocessor /// processing time of eNB MAC preprocessor
time_stats_t schedule_dlsch_preprocessor; time_stats_t schedule_dlsch_preprocessor;
/// processing time of eNB DLSCH scheduler /// processing time of eNB DLSCH scheduler
time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
/// processing time of eNB MCH scheduler /// processing time of eNB MCH scheduler
time_stats_t schedule_mch; time_stats_t schedule_mch;
/// processing time of eNB ULSCH reception /// processing time of eNB ULSCH reception
time_stats_t rx_ulsch_sdu; // include rlc_data_ind time_stats_t rx_ulsch_sdu; // include rlc_data_ind
/// processing time of eNB PCH scheduler /// processing time of eNB PCH scheduler
time_stats_t schedule_pch; time_stats_t schedule_pch;
/// CCE lists /// CCE lists
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
} gNB_MAC_INST; } gNB_MAC_INST;
typedef struct { typedef struct {
uint8_t format_indicator; //1 bit uint8_t format_indicator; //1 bit
uint16_t frequency_domain_assignment; //up to 16 bits uint16_t frequency_domain_assignment; //up to 16 bits
uint8_t time_domain_assignment; // 4 bits uint8_t time_domain_assignment; // 4 bits
uint8_t frequency_hopping_flag; //1 bit uint8_t frequency_hopping_flag; //1 bit
uint8_t ra_preamble_index; //6 bits uint8_t ra_preamble_index; //6 bits
uint8_t ss_pbch_index; //6 bits uint8_t ss_pbch_index; //6 bits
uint8_t prach_mask_index; //4 bits uint8_t prach_mask_index; //4 bits
uint8_t vrb_to_prb_mapping; //0 or 1 bit uint8_t vrb_to_prb_mapping; //0 or 1 bit
uint8_t mcs; //5 bits uint8_t mcs; //5 bits
uint8_t ndi; //1 bit uint8_t ndi; //1 bit
uint8_t rv; //2 bits uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits uint8_t harq_pid; //4 bits
uint8_t dai; //0, 2 or 4 bits uint8_t dai; //0, 2 or 4 bits
uint8_t dai1; //1 or 2 bits uint8_t dai1; //1 or 2 bits
uint8_t dai2; //0 or 2 bits uint8_t dai2; //0 or 2 bits
uint8_t tpc; //2 bits uint8_t tpc; //2 bits
uint8_t pucch_resource_indicator; //3 bits uint8_t pucch_resource_indicator; //3 bits
uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
uint8_t short_messages_indicator; //2 bits uint8_t short_messages_indicator; //2 bits
uint8_t short_messages; //8 bits uint8_t short_messages; //8 bits
uint8_t tb_scaling; //2 bits uint8_t tb_scaling; //2 bits
uint8_t carrier_indicator; //0 or 3 bits uint8_t carrier_indicator; //0 or 3 bits
uint8_t bwp_indicator; //0, 1 or 2 bits uint8_t bwp_indicator; //0, 1 or 2 bits
uint8_t prb_bundling_size_indicator; //0 or 1 bits uint8_t prb_bundling_size_indicator; //0 or 1 bits
uint8_t rate_matching_indicator; //0, 1 or 2 bits uint8_t rate_matching_indicator; //0, 1 or 2 bits
uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits
uint8_t transmission_configuration_indication; //0 or 3 bits uint8_t transmission_configuration_indication; //0 or 3 bits
uint8_t srs_request; //2 bits uint8_t srs_request; //2 bits
uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
uint8_t dmrs_sequence_initialization; //0 or 1 bit uint8_t dmrs_sequence_initialization; //0 or 1 bit
uint8_t srs_resource_indicator; uint8_t srs_resource_indicator;
uint8_t precoding_information; uint8_t precoding_information;
uint8_t csi_request; uint8_t csi_request;
uint8_t ptrs_dmrs_association; uint8_t ptrs_dmrs_association;
uint8_t beta_offset_indicator; //0 or 2 bits uint8_t beta_offset_indicator; //0 or 2 bits
uint8_t slot_format_indicator_count; uint8_t slot_format_indicator_count;
uint8_t *slot_format_indicators; uint8_t *slot_format_indicators;
uint8_t pre_emption_indication_count; uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit uint16_t *pre_emption_indications; //14 bit
uint8_t block_number_count; uint8_t block_number_count;
uint8_t *block_numbers; uint8_t *block_numbers;
uint8_t ul_sul_indicator; //0 or 1 bit uint8_t ul_sul_indicator; //0 or 1 bit
uint8_t antenna_ports; uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding; uint16_t padding;
} dci_pdu_rel15_t; } dci_pdu_rel15_t;
......
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