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Commit 986b5fb2 authored by cig's avatar cig
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Integrated nfapi_nr_dl_dci_pdu_t in DL DCI

parent ffa5911d
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nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
View file @ 986b5fb2
...@@ -622,22 +622,35 @@ typedef struct { ...@@ -622,22 +622,35 @@ typedef struct {
//table 3-37 //table 3-37
#define DCI_PAYLOAD_BTYE_LEN 12 //? TS38.212 sec 7.3.1 #define DCI_PAYLOAD_BYTE_LEN 8 // 12 ? TS38.212 sec 7.3.1
#define MAX_DCI_CORESET 8
typedef struct typedef struct {
{ // The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
uint16_t rnti;// uint16_t RNTI[MAX_DCI_CORESET];
uint16_t scrambling_id;// // For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured,
uint16_t scrambling_rnti;/* */ // otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
uint8_t cce_index;// uint16_t ScramblingId[MAX_DCI_CORESET];
uint8_t aggregation_level;// // For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI.
nfapi_nr_tx_precoding_and_beamforming_t* precoding_and_beamforming_list; // Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
//tx power info uint16_t ScramblingRNTI[MAX_DCI_CORESET];
uint8_t beta_pdcch_1_0;/*PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of // CCE start Index used to send the DCI Value: 0->135
SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */ uint8_t CceIndex[MAX_DCI_CORESET];
uint8_t power_control_offset_ss;//PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB // Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
uint16_t payload_size_bits;//The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0-> DCI_PAYLOAD_BTYE_LEN*8 uint8_t AggregationLevel[MAX_DCI_CORESET];
uint8_t payload[DCI_PAYLOAD_BTYE_LEN];//DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB // Precoding and Beamforming structure See Table 3-43
nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
// PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI.
// This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1]
// Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
// PDCCH power value used for all other PDCCH Formats.
// This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
// The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8
uint16_t PayloadSizeBits[MAX_DCI_CORESET];
// DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_dci_pdu_t; } nfapi_nr_dl_dci_pdu_t;
...@@ -652,9 +665,6 @@ typedef struct { ...@@ -652,9 +665,6 @@ typedef struct {
uint16_t *beamIdx[275]; uint16_t *beamIdx[275];
} nr_beamforming_t; } nr_beamforming_t;
#define MAX_DCI_CORESET 8
#define DCI_PAYLOAD_BYTE_LEN 8
typedef struct { typedef struct {
///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275
uint16_t BWPSize; uint16_t BWPSize;
...@@ -684,26 +694,8 @@ typedef struct { ...@@ -684,26 +694,8 @@ typedef struct {
uint8_t precoderGranularity; uint8_t precoderGranularity;
///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot
uint16_t numDlDci; uint16_t numDlDci;
///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. ///DL DCI PDU
uint16_t RNTI[MAX_DCI_CORESET]; nfapi_nr_dl_dci_pdu_t dci_pdu;
///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
uint16_t ScramblingId[MAX_DCI_CORESET];
///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
uint16_t ScramblingRNTI[MAX_DCI_CORESET];
///CCE start Index used to send the DCI Value: 0->135
uint8_t CceIndex[MAX_DCI_CORESET];
///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
uint8_t AggregationLevel[MAX_DCI_CORESET];
///Precoding and Beamforming structure See Table 3-43
nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8
uint16_t PayloadSizeBits[MAX_DCI_CORESET];
///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_tti_pdcch_pdu_rel15_t; } nfapi_nr_dl_tti_pdcch_pdu_rel15_t;
typedef struct { typedef struct {
......
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @ 986b5fb2
...@@ -206,8 +206,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, ...@@ -206,8 +206,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED, AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED,
"Interleaved CCE REG MAPPING not supported\n"); "Interleaved CCE REG MAPPING not supported\n");
uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)? uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
(n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) (n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType); LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
...@@ -228,18 +228,18 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, ...@@ -228,18 +228,18 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
/// DCI payload processing /// DCI payload processing
// CRC attachment + Scrambling + Channel coding + Rate matching // CRC attachment + Scrambling + Channel coding + Rate matching
uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d]; uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d];
uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d]; uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d];
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE,
pdcch_pdu_rel15->PayloadSizeBits[d], pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],
pdcch_pdu_rel15->AggregationLevel[d], pdcch_pdu_rel15->dci_pdu.AggregationLevel[d],
0,NULL); 0,NULL);
polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr); polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], encoder_output, n_RNTI,1,currentPtr);
#ifdef DEBUG_CHANNEL_CODING #ifdef DEBUG_CHANNEL_CODING
printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]); printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]);
printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]); ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1]);
printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
for (int i=0; i<encoded_length>>5; i++) for (int i=0; i<encoded_length>>5; i++)
...@@ -272,7 +272,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, ...@@ -272,7 +272,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
cset_start_sc -= frame_parms.ofdm_symbol_size; cset_start_sc -= frame_parms.ofdm_symbol_size;
/*Reorder REG list for a freq first mapping*/ /*Reorder REG list for a freq first mapping*/
uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE; uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE;
/*Mapping the encoded DCI along with the DMRS */ /*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) { for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
......
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
View file @ 986b5fb2
...@@ -140,7 +140,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { ...@@ -140,7 +140,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) {
int C; int C;
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) { for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
int L = pdcch_pdu_rel15->AggregationLevel[d]; int L = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d];
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
...@@ -151,10 +151,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { ...@@ -151,10 +151,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) {
C = N_reg/(bsize*R); C = N_reg/(bsize*R);
} }
LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->CceIndex[d]); LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu.CceIndex[d]);
for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) { for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
cce = &gNB->cce_list[d][cce_idx]; cce = &gNB->cce_list[d][cce_idx];
cce->cce_idx = pdcch_pdu_rel15->CceIndex[d] + cce_idx; cce->cce_idx = pdcch_pdu_rel15->dci_pdu.CceIndex[d] + cce_idx;
LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); LOG_D(PHY, "cce_idx %d\n", cce->cce_idx);
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
...@@ -210,12 +210,12 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, ...@@ -210,12 +210,12 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) { for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i];
int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE);
if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){
LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->RNTI[i],dlsch_id); LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id);
return; return;
} }
...@@ -228,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, ...@@ -228,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
"illegal harq_pid %d\n",harq_pid); "illegal harq_pid %d\n",harq_pid);
dlsch->harq_mask |= (1<<harq_pid); dlsch->harq_mask |= (1<<harq_pid);
dlsch->rnti = pdcch_pdu_rel15->RNTI[i]; dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i];
nr_fill_cce_list(gNB,0); nr_fill_cce_list(gNB,0);
/* /*
...@@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, ...@@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) { for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i];
// if there's no DL DCI then generate CCE list // if there's no DL DCI then generate CCE list
if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0); if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ 986b5fb2
...@@ -373,11 +373,11 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -373,11 +373,11 @@ int configure_fapi_dl_pdu(int Mod_idP,
bwp); bwp);
pdcch_pdu_rel15->numDlDci = 1; pdcch_pdu_rel15->numDlDci = 1;
pdcch_pdu_rel15->AggregationLevel[0] = 4; pdcch_pdu_rel15->dci_pdu.AggregationLevel[0] = 4;
pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; pdcch_pdu_rel15->dci_pdu.RNTI[0]=UE_list->rnti[0];
pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0]; pdcch_pdu_rel15->dci_pdu.CceIndex[0] = CCEIndex[0];
pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; pdcch_pdu_rel15->dci_pdu.beta_PDCCH_1_0[0]=0;
pdcch_pdu_rel15->powerControlOffsetSS[0]=1; pdcch_pdu_rel15->dci_pdu.powerControlOffsetSS[0]=1;
int dci_formats[2]; int dci_formats[2];
int rnti_types[2]; int rnti_types[2];
...@@ -385,12 +385,12 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -385,12 +385,12 @@ int configure_fapi_dl_pdu(int Mod_idP,
dci_formats[0] = NR_DL_DCI_FORMAT_1_0; dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
rnti_types[0] = NR_RNTI_C; rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
pdcch_pdu_rel15->RNTI[0], pdcch_pdu_rel15->dci_pdu.RNTI[0],
rnti_types[0], rnti_types[0],
dci_formats[0], dci_formats[0],
(unsigned long long)pdcch_pdu_rel15->FreqDomainResource, (unsigned long long)pdcch_pdu_rel15->FreqDomainResource,
...@@ -433,7 +433,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr ...@@ -433,7 +433,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
dci_pdu_rel15->tpc = 2; dci_pdu_rel15->tpc = 2;
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment, dci_pdu_rel15->frequency_domain_assignment,
dci_pdu_rel15->time_domain_assignment, dci_pdu_rel15->time_domain_assignment,
dci_pdu_rel15->frequency_hopping_flag, dci_pdu_rel15->frequency_hopping_flag,
...@@ -825,13 +825,13 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -825,13 +825,13 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); AssertFatal(CCEIndex>=0,"CCEIndex is negative \n");
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex;
LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]); LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]);
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
} }
\ No newline at end of file
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 986b5fb2
...@@ -497,7 +497,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -497,7 +497,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
for (int i=0;i<pdcch_pdu->numDlDci;i++) { for (int i=0;i<pdcch_pdu->numDlDci;i++) {
//pdcch-DMRS-ScramblingID //pdcch-DMRS-ScramblingID
AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n");
pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; pdcch_pdu->dci_pdu.ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID;
} }
/// SearchSpace /// SearchSpace
...@@ -559,10 +559,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -559,10 +559,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) { for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d];
AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; int dci_size = pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d];
/// Payload generation /// Payload generation
switch(dci_formats[d]) { switch(dci_formats[d]) {
...@@ -1365,19 +1365,21 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ ...@@ -1365,19 +1365,21 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
} }
*/ */
/* TBR fix this /*
boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_flag, int slot, int aggregation, int rnti){ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_id, int format_flag, int slot, int aggregation, int rnti){
nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_idP]->DL_req[CC_idP].dl_config_request_body; gNB_MAC_INST *mac = RC.nrmac[module_idP];
nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_id].dl_config_request_body;
nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_idP][slot].hi_dci0_request_body; nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_id][slot].hi_dci0_request_body;
nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi]; nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi];
int ret; int ret;
boolean_t res = FALSE; boolean_t res = FALSE;
if (format_flag != 2) { // DL DCI if (format_flag != 2) { // DL DCI
if (DL_req->number_pdu == MAX_NUM_DL_PDU) { if (dl_req->number_pdu == MAX_NUM_DL_PDU) {
LOG_W(MAC, LOG_W(MAC,
"Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n",
slot, rnti); slot, rnti);
...@@ -1387,7 +1389,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl ...@@ -1387,7 +1389,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation;
DL_req->number_pdu++; dl_req->number_pdu++;
LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n", LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n",
slot, format_flag, rnti, aggregation, slot, format_flag, rnti, aggregation,
...@@ -1396,11 +1398,11 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl ...@@ -1396,11 +1398,11 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl
aggregation_level, aggregation_level,
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type); dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type);
// ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR
if (ret == -1) res = TRUE; if (ret == -1) res = TRUE;
DL_req->number_pdu--; dl_req->number_pdu--;
} }
} else { // ue-specific UL DCI } else { // ue-specific UL DCI
if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) { if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) {
...@@ -1411,7 +1413,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl ...@@ -1411,7 +1413,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti;
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation;
HI_DCI0_req->number_of_dci++; HI_DCI0_req->number_of_dci++;
// ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR
if (ret == -1) res = TRUE; if (ret == -1) res = TRUE;
HI_DCI0_req->number_of_dci--; HI_DCI0_req->number_of_dci--;
} }
......
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