Commit b3cae4e6 authored by Robert Schmidt's avatar Robert Schmidt

Remove support for ORAN FHI bronze release

parent 384b06cb
......@@ -496,27 +496,14 @@ target_link_libraries(shlib_loader PRIVATE CONFIG_LIB)
# ORAN 5G library
######################################################################
add_boolean_option(ORAN_BRONZE OFF "Build support for Bronze version of ORAN FHI" OFF)
if (ORAN_BRONZE)
set(ORAN_FHLIB_5G_SOURCE
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/sample-app-bronze.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/common_bronze.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/config_bronze.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oran_isolate.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oaioran.c
)
else()
set(ORAN_FHLIB_5G_SOURCE
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/sample-app-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/app_io_fh_xran-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/common-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/config-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oran_isolate.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oaioran.c
)
endif()
add_library(oran_fhlib_5g MODULE ${ORAN_FHLIB_5G_SOURCE})
add_library(oran_fhlib_5g MODULE
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/sample-app-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/app_io_fh_xran-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/common-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/config-E.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oran_isolate.c
${OPENAIR_DIR}/radio/ETHERNET/oran/5g/oaioran.c
)
target_include_directories(oran_fhlib_5g PRIVATE ${XRAN_DIR})
target_include_directories(oran_fhlib_5g PRIVATE ${DPDK_DIR})
......@@ -524,11 +511,7 @@ target_include_directories(oran_fhlib_5g PRIVATE ${INTEL_LIB})
target_include_directories(oran_fhlib_5g PRIVATE ${XRAN_COMMON_DIR})
target_include_directories(oran_fhlib_5g PRIVATE ${XRAN_LIB_API_DIR})
if (ORAN_BRONZE)
set_target_properties(oran_fhlib_5g PROPERTIES COMPILE_FLAGS "-DORAN_BRONZE -fvisibility=hidden -march=native -I$ENV{RTE_SDK}/$ENV{RTE_TARGET}/include")
else()
set_target_properties(oran_fhlib_5g PROPERTIES COMPILE_FLAGS "-fvisibility=hidden -march=native -I$ENV{RTE_SDK}/$ENV{RTE_TARGET}/include")
endif()
#SET(DPDK_LIBS "-Wl,-rpath,$ENV{RTE_SDK}/$ENV{RTE_TARGET}/lib -Wl,--whole-archive -L$ENV{RTE_SDK}/$ENV{RTE_TARGET}/lib -ldpdk -Wl,--no-whole-archive")
execute_process(
......
......@@ -58,7 +58,6 @@ Tested libxran releases:
| Vendor |
|---------------------------------|
| oran_release_bronze_v1.1 |
| oran_e_maintenance_release_v1.0 |
## 1.1 Configure your server
......@@ -330,7 +329,6 @@ git checkout fhidriver_E_rk
git checkout develop
# We have different versions of patches per O-RAN releases
ls cmake_targets/tools/oran_fhi_integration_patches/
E bronze
```
## 2.1 Build ORAN Fronthaul Interface Library
......@@ -342,26 +340,6 @@ git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git ~/phy
cd ~/phy
```
### 2.1.1. Using the Bronze Release
```bash
git checkout oran_release_bronze_v1.1
```
Apply patches (available in `oai_folder/cmake_targets/tools/oran_fhi_integration_patches/bronze`)
```bash
cp ~/openairinterface5g/cmake_targets/tools/oran_fhi_integration_patches/bronze/oran-fhi-*.patch .
git apply oran-fhi-1-compile-libxran-using-gcc-and-disable-avx512.patch
git apply oran-fhi-2-return-correct-slot_id.patch
git apply oran-fhi-3-disable-pkt-validate-at-process_mbuf.patch
git apply oran-fhi-4-process_all_rx_ring.patch
git apply oran-fhi-5-remove-not-used-dependencies.patch
```
### 2.1.2. Using the E Release
```bash
git checkout oran_e_maintenance_release_v1.0
```
......
This diff is collapsed.
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
#ifndef _XRAN_APP_COMMON_H_
#define _XRAN_APP_COMMON_H_
#include <stdio.h>
#include <unistd.h>
#include "xran_fh_o_du.h"
#include "xran_pkt_up.h"
#include <rte_common.h>
#include <rte_mbuf.h>
#define VERSIONX "oran_bronze_release_v1.1"
#define APP_O_DU 0
#define APP_O_RU 1
enum app_state
{
APP_RUNNING,
APP_STOPPED
};
enum nRChBwOptions
{
PHY_BW_5_0_MHZ = 5, PHY_BW_10_0_MHZ = 10, PHY_BW_15_0_MHZ = 15, PHY_BW_20_0_MHZ = 20, PHY_BW_25_0_MHZ = 25,
PHY_BW_30_0_MHZ = 30, PHY_BW_40_0_MHZ = 40, PHY_BW_50_0_MHZ = 50, PHY_BW_60_0_MHZ = 60, PHY_BW_70_0_MHZ = 70,
PHY_BW_80_0_MHZ = 80, PHY_BW_90_0_MHZ = 90, PHY_BW_100_0_MHZ = 100, PHY_BW_200_0_MHZ = 200, PHY_BW_400_0_MHZ = 400
};
#define N_SC_PER_PRB 12
#define N_SYM_PER_SLOT 14
#define MAX_ANT_CARRIER_SUPPORTED (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR)
#define MAX_ANT_CARRIER_SUPPORTED_CAT_B (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR)
#define SUBFRAME_DURATION_US 1000
//#define SLOTNUM_PER_SUBFRAME 8
#define SUBFRAMES_PER_SYSTEMFRAME 10
#define IQ_PLAYBACK_BUFFER_BYTES (XRAN_NUM_OF_SLOT_IN_TDD_LOOP*N_SYM_PER_SLOT*XRAN_MAX_PRBS*N_SC_PER_PRB*4L)
/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 839 samples for long sequence or 144*14 (max) for short sequence. The payload length is 3356 octets.*/
#define PRACH_PLAYBACK_BUFFER_BYTES (144*14*4L)
#ifdef _DEBUG
#define iAssert(p) if(!(p)){fprintf(stderr,\
"Assertion failed: %s, file %s, line %d, val %d\n",\
#p, __FILE__, __LINE__, p);exit(-1);}
#else /* _DEBUG */
#define iAssert(p)
#endif /* _DEBUG */
extern int iq_playback_buffer_size_dl;
extern int iq_playback_buffer_size_ul;
extern int iq_bfw_buffer_size_dl;
extern int iq_bfw_buffer_size_ul;
extern int iq_srs_buffer_size_ul;
extern uint8_t numCCPorts;
/* Number of antennas supported by front-end */
extern uint8_t num_eAxc;
/* Number of antennas supported by front-end */
extern int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
extern int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
extern int16_t *p_tx_srs_play_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
extern int32_t tx_srs_play_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
extern int32_t tx_srs_play_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
/* Number of antennas supported by front-end */
extern int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
extern int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
extern int16_t *p_srs_log_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
extern int32_t srs_log_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
extern int32_t srs_log_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
extern int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
extern int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
extern int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-RU) */
extern int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-RU) */
extern int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
extern int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
void sys_save_buf_to_file_txt(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
uint32_t app_xran_get_scs(uint8_t nMu);
uint16_t app_xran_get_num_rbs(uint8_t ranTech, uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA);
uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq);
int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType,
uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig);
uint32_t app_xran_get_tti_interval(uint8_t nMu);
#endif /*_XRAN_APP_COMMON_H_*/
This diff is collapsed.
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
/**
* @brief
* @file
* @ingroup
* @author Intel Corporation
**/
#ifndef _SAMPLEAPP__CONFIG_H_
#define _SAMPLEAPP__CONFIG_H_
#include <stdint.h>
#include <rte_ether.h>
#include "xran_fh_o_du.h"
/** Run time configuration of application */
typedef struct _RuntimeConfig
{
uint8_t appMode; /**< Application mode: lls-CU or RU */
uint8_t xranTech; /**< Radio Access Technology (NR or LTE) */
uint8_t xranCat; /**< xran mode: NR Categoty A, NR Category B, LTE Cat A, LTE Cat B */
uint8_t numCC; /**< Number of CC per ports supported by RU */
uint8_t numAxc; /**< Number of Antenna Carriers per CC */
uint8_t numUlAxc; /**< Number of Antenna Carriers per CC for UL (Cat B) */
uint32_t antElmTRx; /**< Number of antenna elements for TX and RX */
uint32_t muMimoUEs; /**< Number of UEs (with 1 RX ant)/beams */
uint32_t DlLayersPerUe; /**< Number of DL layer per UE */
uint32_t UlLayersPerUe; /**< Number of UL layer per UE */
uint32_t ttiPeriod; /**< TTI period */
uint32_t testVect; /**< Test Signal to send */
struct rte_ether_addr o_du_addr[XRAN_VF_MAX]; /**< O-DU Ethernet Mac Address */
struct rte_ether_addr o_ru_addr[XRAN_VF_MAX]; /**< O-RU Ethernet Mac Address */
struct rte_ether_addr tmp_addr; /**< Temp Ethernet Mac Address */
uint32_t instance_id; /**< Instance ID of application */
uint32_t io_core; /**< Core used for IO */
uint64_t io_worker; /**< Mask for worker cores */
int32_t io_sleep; /**< enable sleep on PMD cores */
uint32_t system_core; /* house keeping core */
int iova_mode; /**< DPDK IOVA Mode */
uint32_t mtu; /**< maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) */
int numSlots; /**< number of slots in IQ vector */
char ant_file[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file to use for test vector */
char prach_file[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file to use for test vector */
char dl_bfw_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file with beamforming weights for DL streams */
char ul_bfw_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file with beamforming weights for UL streams */
char ul_srs_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR][512]; /**< file with SRS content for UL antenna elements */
/* prach config */
uint8_t enablePrach; /**< enable PRACH */
uint8_t prachOffset; /**< Sets the PRACH position in frequency / subcarrier position, n_PRBoffset^RA and is expressed as a physical resource block number.
Set by SIB2, prach-FreqOffset in E-UTRA. */
uint8_t prachConfigIndex;/**< TS36.211 - Table 5.7.1-2 : PRACH Configuration Index */
int32_t prachFreqOffset;
uint8_t iqswap; /**< do swap of IQ before send to ETH */
uint8_t nebyteorderswap; /**< do swap of byte order from host byte order to network byte order. ETH */
uint8_t compression; /**< enable use case with compression */
uint8_t CompHdrType; /**< dynamic or static compression header */
uint8_t iqWidth; /**< width of I and Q samples in bits */
uint16_t totalBfWeights; /**< The total number of beamforming weights on RU */
uint8_t enableSrs; /**< enable SRS (valid for Cat B only) */
uint16_t srsSymMask; /**< SRS symbol mask [014] within S/U slot [0-13] def is 13 */
uint16_t maxFrameId; /**< max value of frame id */
uint16_t Tadv_cp_dl;
uint16_t T2a_min_cp_dl;
uint16_t T2a_max_cp_dl;
uint16_t T2a_min_cp_ul;
uint16_t T2a_max_cp_ul;
uint16_t T2a_min_up;
uint16_t T2a_max_up;
uint16_t Ta3_min;
uint16_t Ta3_max;
uint16_t T1a_min_cp_dl;
uint16_t T1a_max_cp_dl;
uint16_t T1a_min_cp_ul;
uint16_t T1a_max_cp_ul;
uint16_t T1a_min_up;
uint16_t T1a_max_up;
uint16_t Ta4_min;
uint16_t Ta4_max;
uint8_t enableCP; /**< enable C-plane */
uint16_t cp_vlan_tag; /**< C-plane vlan tag */
uint16_t up_vlan_tag; /**< U-plane vlan tag */
int32_t debugStop;
int32_t debugStopCount;
int32_t bbdevMode;
int32_t DynamicSectionEna;
int32_t GPS_Alpha;
int32_t GPS_Beta;
uint8_t mu_number; /**< Mu numner as per 3GPP */
uint32_t nDLAbsFrePointA; /**< Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 */
uint32_t nULAbsFrePointA; /**< Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 */
uint32_t nDLBandwidth; /**< Carrier bandwidth for in MHz. Value: 5->400 */
uint32_t nULBandwidth; /**< Carrier bandwidth for in MHz. Value: 5->400 */
uint32_t nDLFftSize; /**< DL FFT size */
uint32_t nULFftSize; /**< UL FFT size */
uint8_t nFrameDuplexType;
uint8_t nTddPeriod;
struct xran_slot_config sSlotConfig[XRAN_MAX_TDD_PERIODICITY];
struct xran_prb_map PrbMapDl;
struct xran_prb_map PrbMapUl;
int32_t DU_Port_ID_bitwidth;
int32_t BandSector_ID_bitwidth;
int32_t CC_ID_bitwidth;
int32_t RU_Port_ID_bitwidth;
} RuntimeConfig;
/**
* Parse application configuration file.
*
* @param filename The name of the configuration file to be parsed.
* @param config The configuration structure to be filled with parsed data. */
int parseConfigFile(char *filename, RuntimeConfig *config);
#endif /* _SAMPLEAPP__CONFIG_H_ */
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
/**
* @brief
* @file
* @ingroup
* @author Intel Corporation
**/
#ifndef _SAMPLEAPP__DEBUG_H_
#define _SAMPLEAPP__DEBUG_H_
#include <stdio.h>
#include "config.h"
#define MAX_FILE_NAME_LEN (512)
#define MAX_PATH_NAME_LEN (1024)
#ifdef _DEBUG
#define log_dbg(fmt, ...) \
fprintf(stderr, \
"DEBUG: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
#else
#define log_dbg(fmt, ...)
#endif
#if defined(_DEBUG) || defined(_VERBOSE)
#define log_wrn(fmt, ...) \
fprintf( \
stderr, \
"WARNING: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
#else
#define log_dbg(fmt, ...)
#define log_wrn(fmt, ...)
#endif
#define log_err(fmt, ...) \
fprintf(stderr, \
"ERROR: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
inline void ShowData(void* ptr, unsigned int size)
{
uint8_t *d = (uint8_t *)ptr;
unsigned int i;
for(i = 0; i < size; i++)
{
if ( !(i & 0xf) )
printf("\n");
printf("%02x ", d[i]);
}
printf("\n");
}
#endif /* _SAMPLEAPP__DEBUG_H_ */
......@@ -55,14 +55,8 @@ volatile uint32_t rx_cb_slot = 0;
#define GetFrameNum(tti,SFNatSecStart,numSubFramePerSystemFrame, numSlotPerSubFrame) ((((uint32_t)tti / ((uint32_t)numSubFramePerSystemFrame * (uint32_t)numSlotPerSubFrame)) + SFNatSecStart) & 0x3FF)
#define GetSlotNum(tti, numSlotPerSfn) ((uint32_t)tti % ((uint32_t)numSlotPerSfn))
#ifdef ORAN_BRONZE
extern struct xran_fh_config xranConf;
extern void * xranHandle;
int xran_is_prach_slot(uint32_t subframe_id, uint32_t slot_id);
#else
#include "app_io_fh_xran.h"
int xran_is_prach_slot(uint8_t PortId, uint32_t subframe_id, uint32_t slot_id);
#endif
#include "common/utils/LOG/log.h"
#ifndef USE_POLLING
......@@ -82,11 +76,7 @@ void oai_xran_fh_rx_callback(void *pCallbackTag, xran_status_t status){
static int32_t last_slot=-1;
static int32_t last_frame=-1;
tti = xran_get_slot_idx(
#ifndef ORAN_BRONZE
0,
#endif
&frame,&subframe,&slot,&second);
tti = xran_get_slot_idx(0, &frame, &subframe, &slot, &second);
rx_sym = callback_tag->symbol;
if (rx_sym == 7) {
......@@ -161,12 +151,8 @@ int read_prach_data(ru_info_t *ru, int frame, int slot)
/* calculate tti and subframe_id from frame, slot num */
int tti = 20 * (frame) + (slot);
uint32_t subframe = XranGetSubFrameNum(tti, 2, 10);
uint32_t is_prach_slot = xran_is_prach_slot(
#ifndef ORAN_BRONZE
0,
#endif
subframe, (slot % 2));
int sym_idx = 0;
uint32_t is_prach_slot = xran_is_prach_slot(0, subframe, (slot % 2));
int sym_idx = 0;
struct xran_device_ctx *xran_ctx = xran_dev_get_ctx();
struct xran_prach_cp_config *pPrachCPConfig = &(xran_ctx->PrachCPConfig);
......@@ -277,17 +263,10 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
read_prach_data(ru, *frame, *slot);
struct xran_device_ctx *xran_ctx = xran_dev_get_ctx();
#ifdef ORAN_BRONZE
int num_eaxc = xranConf.neAxc;
int num_eaxc_ul = xranConf.neAxcUl;
int nPRBs = xranConf.nULRBs;
int fftsize = 1<<xranConf.ru_conf.fftSize;
#else
int num_eaxc = app_io_xran_fh_config[0].neAxc;
int num_eaxc_ul = app_io_xran_fh_config[0].neAxcUl;
int nPRBs = app_io_xran_fh_config[0].nULRBs;
int fftsize = 1<<app_io_xran_fh_config[0].ru_conf.fftSize;
#endif
uint32_t xran_max_antenna_nr = RTE_MAX(num_eaxc, num_eaxc_ul);
int slot_offset_rxdata = 3&(*slot);
......@@ -334,11 +313,7 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
p_prbMapElm->nRBSize*N_SC_PER_PRB);
pos_len = (p_prbMapElm->nRBSize*N_SC_PER_PRB) - neg_len;
#ifdef ORAN_BRONZE
p_sec_desc = p_prbMapElm->p_sec_desc[sym_id];
#else
p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0];
#endif
if(pRbMap->nPrbElm==1 && idxElm==0){
src = pData;
}
......@@ -418,11 +393,7 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
}//sym_ind
}//ant_ind
}//vv_inf
#ifdef ORAN_BRONZE
if ((*frame&0x7f)==0 && *slot == 0 && xran_get_common_counters(xranHandle, &x_counters[0]) == XRAN_STATUS_SUCCESS)
#else
if ((*frame&0x7f)==0 && *slot == 0 && xran_get_common_counters(app_io_xran_handle, &x_counters[0]) == XRAN_STATUS_SUCCESS)
#endif
{
for (int o_xu_id = 0; o_xu_id < 1 /*p_usecaseConfiguration->oXuNum*/; o_xu_id++) {
LOG_I(NR_PHY,"[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld][Total Msgs_Rcvd %ld]\n",
......@@ -457,17 +428,10 @@ int xran_fh_tx_send_slot(ru_info_t *ru, int frame, int slot, uint64_t timestamp)
struct xran_device_ctx *xran_ctx = xran_dev_get_ctx();
#ifdef ORAN_BRONZE
int num_eaxc = xranConf.neAxc;
int num_eaxc_ul = xranConf.neAxcUl;
int nPRBs = xranConf.nDLRBs;
int fftsize = 1<<xranConf.ru_conf.fftSize;
#else
int num_eaxc = app_io_xran_fh_config[0].neAxc;
int num_eaxc_ul = app_io_xran_fh_config[0].neAxcUl;
int nPRBs = app_io_xran_fh_config[0].nDLRBs;
int fftsize = 1<<app_io_xran_fh_config[0].ru_conf.fftSize;
#endif
uint32_t xran_max_antenna_nr = RTE_MAX(num_eaxc, num_eaxc_ul);
/*
for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
......@@ -503,12 +467,8 @@ int xran_fh_tx_send_slot(ru_info_t *ru, int frame, int slot, uint64_t timestamp)
struct xran_section_desc *p_sec_desc = NULL;
p_prbMapElm = &pRbMap->prbMap[idxElm];
p_sec_desc =
#ifdef ORAN_BRONZE
p_prbMapElm->p_sec_desc[sym_id];
#else
//assumes one fragment per symbol
p_prbMapElm->p_sec_desc[sym_id][0];
#endif
dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
......
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