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lizhongxiao
OpenXG-RAN
Commits
d3f90a90
Commit
d3f90a90
authored
Apr 07, 2022
by
francescomani
Browse files
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Plain Diff
removing calculate_preferred_ul_tda
parent
276b2d5e
Changes
8
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8 changed files
with
45 additions
and
172 deletions
+45
-172
openair2/LAYER2/NR_MAC_gNB/config.c
openair2/LAYER2/NR_MAC_gNB/config.c
+1
-11
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+1
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2
-3
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+14
-127
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+1
-1
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+0
-4
openair2/RRC/NR/nr_rrc_config.c
openair2/RRC/NR/nr_rrc_config.c
+25
-23
No files found.
openair2/LAYER2/NR_MAC_gNB/config.c
View file @
d3f90a90
...
...
@@ -592,19 +592,9 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if
(
CellGroup
)
{
const
NR_ServingCellConfig_t
*
servingCellConfig
=
NULL
;
if
(
CellGroup
->
spCellConfig
&&
CellGroup
->
spCellConfig
->
spCellConfigDedicated
)
{
if
(
CellGroup
->
spCellConfig
&&
CellGroup
->
spCellConfig
->
spCellConfigDedicated
)
servingCellConfig
=
CellGroup
->
spCellConfig
->
spCellConfigDedicated
;
const
struct
NR_UplinkConfig__uplinkBWP_ToAddModList
*
ubwpList
=
servingCellConfig
->
uplinkConfig
->
uplinkBWP_ToAddModList
;
if
(
ubwpList
)
{
AssertFatal
(
ubwpList
->
list
.
count
>
0
,
"uplinkBWP_ToAddModList no BWPs!
\n
"
);
for
(
int
i
=
0
;
i
<
ubwpList
->
list
.
count
;
++
i
)
{
const
NR_BWP_Uplink_t
*
ubwp
=
ubwpList
->
list
.
array
[
i
];
calculate_preferred_ul_tda
(
Mod_idP
,
ubwp
);
}
}
}
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
Mod_idP
]
->
UE_info
;
if
(
add_ue
==
1
&&
get_softmodem_params
()
->
phy_test
)
{
const
int
UE_id
=
add_new_nr_ue
(
Mod_idP
,
rnti
,
CellGroup
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
d3f90a90
...
...
@@ -60,8 +60,7 @@ const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int
scc
->
tdd_UL_DL_ConfigurationCommon
?
&
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
:
NULL
;
if
(
tdd
)
{
int
nr_mix_slots
=
tdd
->
nrofDownlinkSymbols
!=
0
;
// there are dl symbols in mixed slot
if
(
nr_mix_slots
!=
0
)
{
// if there is a mixed slot
if
(
tdd
->
nrofDownlinkSymbols
>
1
)
{
// if there is a mixed slot where we can transmit DL
int
nr_slots_period
=
n
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofDownlinkSlots
)
return
1
;
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
d3f90a90
...
...
@@ -436,7 +436,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
RC
.
nrmac
[
module_id
]
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
1
;
const
int
tda
=
s
et_ul_tda
(
nr_mac
,
scc
,
slot
)
;
if
(
tda
<
0
)
return
false
;
const
struct
NR_PUSCH_TimeDomainResourceAllocationList
*
tdaList
=
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
d3f90a90
...
...
@@ -2917,14 +2917,13 @@ void nr_mac_update_timers(module_id_t module_id,
cg
->
spCellConfig
->
spCellConfigDedicated
&&
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
?
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
initialUplinkBWP
:
NULL
;
int
**
preferred_ul_tda
=
RC
.
nrmac
[
module_id
]
->
preferred_ul_tda
;
NR_pusch_semi_static_t
*
ups
=
&
sched_ctrl
->
pusch_semi_static
;
int
dci_format
=
get_dci_format
(
sched_ctrl
);
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
ubwp
||
ubwpd
)
?
1
:
2
;
const
uint8_t
nrOfLayers
=
1
;
const
int
utda
=
ubwp
&&
preferred_ul_tda
[
ubwp
->
bwp_Id
][
slot
]
>=
0
?
preferred_ul_tda
[
ubwp
->
bwp_Id
][
slot
]
:
(
ups
->
time_domain_allocation
>=
0
?
ups
->
time_domain_allocation
:
0
);
const
int
utda
=
set_ul_tda
(
RC
.
nrmac
[
module_id
],
scc
,
slot
);
nr_set_pusch_semi_static
(
sib1
,
scc
,
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
d3f90a90
...
...
@@ -46,138 +46,25 @@ int get_dci_format(NR_UE_sched_ctrl_t *sched_ctrl) {
return
(
dci_format
);
}
void
calculate_preferred_ul_tda
(
module_id_t
module_id
,
const
NR_BWP_Uplink_t
*
ubwp
)
{
gNB_MAC_INST
*
nrmac
=
RC
.
nrmac
[
module_id
];
const
int
bwp_id
=
ubwp
->
bwp_Id
;
if
(
nrmac
->
preferred_ul_tda
[
bwp_id
])
return
;
const
int
set_ul_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
)
{
/* there is a mixed slot only when in TDD */
NR_ServingCellConfigCommon_t
*
scc
=
nrmac
->
common_channels
->
ServingCellConfigCommon
;
frame_type_t
frame_type
=
nrmac
->
common_channels
->
frame_type
;
const
int
n
=
nr_slots_per_frame
[
*
scc
->
ssbSubcarrierSpacing
];
const
NR_TDD_UL_DL_Pattern_t
*
tdd
=
scc
->
tdd_UL_DL_ConfigurationCommon
?
&
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
:
NULL
;
NR_ServingCellConfigCommonSIB_t
*
scc_sib1
=
nrmac
->
common_channels
[
0
].
sib1
?
RC
.
nrmac
[
module_id
]
->
common_channels
[
0
].
sib1
->
message
.
choice
.
c1
->
choice
.
systemInformationBlockType1
->
servingCellConfigCommon
:
NULL
;
AssertFatal
(
scc
!=
NULL
||
scc_sib1
!=
NULL
,
"We need one serving cell config common
\n
"
);
const
int
mu
=
scc
?
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
subcarrierSpacing
:
scc_sib1
->
uplinkConfigCommon
->
initialUplinkBWP
.
genericParameters
.
subcarrierSpacing
;
NR_TDD_UL_DL_Pattern_t
*
tdd
=
NULL
;
if
(
scc
&&
scc
->
tdd_UL_DL_ConfigurationCommon
)
{
tdd
=
&
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
;
}
else
if
(
scc_sib1
&&
scc_sib1
->
tdd_UL_DL_ConfigurationCommon
)
{
tdd
=
&
scc_sib1
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
;
}
/* Uplink symbols are at the end of the slot */
int
symb_ulMixed
=
0
;
int
nr_mix_slots
=
0
;
int
nr_slots_period
=
n
;
if
(
tdd
)
{
symb_ulMixed
=
((
1
<<
tdd
->
nrofUplinkSymbols
)
-
1
)
<<
(
14
-
tdd
->
nrofUplinkSymbols
);
nr_mix_slots
=
tdd
->
nrofDownlinkSymbols
!=
0
||
tdd
->
nrofUplinkSymbols
!=
0
;
nr_slots_period
/=
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
if
(
tdd
->
nrofUplinkSymbols
>
1
)
{
// if there is uplink symbols in mixed slot
int
nr_slots_period
=
n
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofUplinkSlots
)
return
1
;
}
}
else
// if TDD configuration is not present and the band is not FDD, it means it is a dynamic TDD configuration
AssertFatal
(
nrmac
->
common_channels
->
frame_type
==
FDD
,
"Dynamic TDD not handled yet
\n
"
);
const
struct
NR_PUCCH_Config__resourceToAddModList
*
resList
=
ubwp
->
bwp_Dedicated
->
pucch_Config
->
choice
.
setup
->
resourceToAddModList
;
// for the moment, just block any symbol that might hold a PUCCH, regardless
// of the RB. This is a big simplification, as most RBs will NOT have a PUCCH
// in the respective symbols, but it simplifies scheduling
uint16_t
symb_pucch
=
0
;
for
(
int
i
=
0
;
i
<
resList
->
list
.
count
;
++
i
)
{
const
NR_PUCCH_Resource_t
*
resource
=
resList
->
list
.
array
[
i
];
int
nrofSymbols
=
0
;
int
startingSymbolIndex
=
0
;
switch
(
resource
->
format
.
present
)
{
case
NR_PUCCH_Resource__format_PR_format0
:
nrofSymbols
=
resource
->
format
.
choice
.
format0
->
nrofSymbols
;
startingSymbolIndex
=
resource
->
format
.
choice
.
format0
->
startingSymbolIndex
;
break
;
case
NR_PUCCH_Resource__format_PR_format1
:
nrofSymbols
=
resource
->
format
.
choice
.
format1
->
nrofSymbols
;
startingSymbolIndex
=
resource
->
format
.
choice
.
format1
->
startingSymbolIndex
;
break
;
case
NR_PUCCH_Resource__format_PR_format2
:
nrofSymbols
=
resource
->
format
.
choice
.
format2
->
nrofSymbols
;
startingSymbolIndex
=
resource
->
format
.
choice
.
format2
->
startingSymbolIndex
;
break
;
case
NR_PUCCH_Resource__format_PR_format3
:
nrofSymbols
=
resource
->
format
.
choice
.
format3
->
nrofSymbols
;
startingSymbolIndex
=
resource
->
format
.
choice
.
format3
->
startingSymbolIndex
;
break
;
case
NR_PUCCH_Resource__format_PR_format4
:
nrofSymbols
=
resource
->
format
.
choice
.
format4
->
nrofSymbols
;
startingSymbolIndex
=
resource
->
format
.
choice
.
format4
->
startingSymbolIndex
;
break
;
default:
AssertFatal
(
0
,
"found NR_PUCCH format index %d
\n
"
,
resource
->
format
.
present
);
break
;
}
symb_pucch
|=
((
1
<<
nrofSymbols
)
-
1
)
<<
startingSymbolIndex
;
}
/* check that TDA index 1 fits into UL slot and does not overlap with PUCCH */
const
struct
NR_PUSCH_TimeDomainResourceAllocationList
*
tdaList
=
ubwp
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
;
const
NR_PUSCH_TimeDomainResourceAllocation_t
*
tdaP_UL
=
tdaList
->
list
.
array
[
0
];
const
int
k2
=
get_K2
(
scc
,
scc_sib1
,
(
NR_BWP_Uplink_t
*
)
ubwp
,
0
,
mu
);
int
start
,
len
;
SLIV2SL
(
tdaP_UL
->
startSymbolAndLength
,
&
start
,
&
len
);
const
uint16_t
symb_tda
=
((
1
<<
len
)
-
1
)
<<
start
;
// check whether PUCCH and TDA overlap: then, we cannot use it. Note that
// here we assume that the PUCCH is scheduled in every slot, and on all RBs
// (which is mostly not true, this is a simplification)
AssertFatal
((
symb_pucch
&
symb_tda
)
==
0
,
"TDA index 0 for UL overlaps with PUCCH
\n
"
);
// get largest time domain allocation (TDA) for UL slot and UL in mixed slot
int
tdaMi
=
-
1
;
if
(
nr_mix_slots
>
0
)
{
const
NR_PUSCH_TimeDomainResourceAllocation_t
*
tdaP_Mi
=
tdaList
->
list
.
array
[
1
];
AssertFatal
(
k2
==
get_K2
(
scc
,
scc_sib1
,
(
NR_BWP_Uplink_t
*
)
ubwp
,
1
,
mu
),
"scheduler cannot handle different k2 for UL slot (%d) and UL Mixed slot (%ld)
\n
"
,
k2
,
get_K2
(
scc
,
scc_sib1
,
(
NR_BWP_Uplink_t
*
)
ubwp
,
1
,
mu
));
SLIV2SL
(
tdaP_Mi
->
startSymbolAndLength
,
&
start
,
&
len
);
const
uint16_t
symb_tda_mi
=
((
1
<<
len
)
-
1
)
<<
start
;
// check whether PUCCH and TDA overlap: then, we cannot use it. Also, check
// whether TDA is entirely within mixed slot, UL. Note that here we assume
// that the PUCCH is scheduled in every slot, and on all RBs (which is
// mostly not true, this is a simplification)
if
((
symb_pucch
&
symb_tda_mi
)
==
0
&&
(
symb_ulMixed
&
symb_tda_mi
)
==
symb_tda_mi
)
{
tdaMi
=
1
;
}
else
{
LOG_E
(
NR_MAC
,
"TDA index 1 UL overlaps with PUCCH or is not entirely in mixed slot (symb_pucch %x symb_ulMixed %x symb_tda_mi %x), won't schedule UL mixed slot
\n
"
,
symb_pucch
,
symb_ulMixed
,
symb_tda_mi
);
}
}
nrmac
->
preferred_ul_tda
[
bwp_id
]
=
malloc
(
n
*
sizeof
(
*
nrmac
->
preferred_ul_tda
[
bwp_id
]));
for
(
int
slot
=
0
;
slot
<
n
;
++
slot
)
{
const
int
sched_slot
=
(
slot
+
k2
)
%
n
;
nrmac
->
preferred_ul_tda
[
bwp_id
][
slot
]
=
-
1
;
if
(
frame_type
==
FDD
||
sched_slot
%
nr_slots_period
>=
tdd
->
nrofDownlinkSlots
+
nr_mix_slots
)
nrmac
->
preferred_ul_tda
[
bwp_id
][
slot
]
=
0
;
else
if
(
nr_mix_slots
&&
sched_slot
%
nr_slots_period
==
tdd
->
nrofDownlinkSlots
)
nrmac
->
preferred_ul_tda
[
bwp_id
][
slot
]
=
tdaMi
;
LOG_D
(
MAC
,
"DL slot %d UL slot %d preferred_ul_tda %d
\n
"
,
slot
,
sched_slot
,
nrmac
->
preferred_ul_tda
[
bwp_id
][
slot
]);
}
if
(
tdd
&&
k2
<
tdd
->
nrofUplinkSlots
)
{
LOG_W
(
NR_MAC
,
"k2 %d < tdd->nrofUplinkSlots %ld: not all UL slots can be scheduled
\n
"
,
k2
,
tdd
->
nrofUplinkSlots
);
}
return
0
;
// if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
}
// For both UL-SCH except:
...
...
@@ -961,7 +848,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
{
const
int
CC_id
=
0
;
gNB_MAC_INST
*
nr_mac
=
RC
.
nrmac
[
module_id
];
const
NR_ServingCellConfigCommon_t
*
scc
=
nr_mac
->
common_channels
[
CC_id
].
ServingCellConfigCommon
;
NR_ServingCellConfigCommon_t
*
scc
=
nr_mac
->
common_channels
[
CC_id
].
ServingCellConfigCommon
;
NR_UE_info_t
*
UE_info
=
&
nr_mac
->
UE_info
;
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
NR_sched_pusch_t
*
retInfo
=
&
sched_ctrl
->
ul_harq_processes
[
harq_pid
].
sched_pusch
;
...
...
@@ -980,7 +867,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
const
uint16_t
bwpSize
=
NRRIV2BW
(
genericParameters
->
locationAndBandwidth
,
MAX_BWP_SIZE
);
const
uint8_t
nrOfLayers
=
1
;
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
sched_ctrl
->
active_bwp
||
ubwpd
)
?
1
:
2
;
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
RC
.
nrmac
[
module_id
]
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
0
;
const
int
tda
=
s
et_ul_tda
(
nr_mac
,
scc
,
slot
)
;
LOG_D
(
NR_MAC
,
"retInfo->time_domain_allocation = %d, tda = %d
\n
"
,
retInfo
->
time_domain_allocation
,
tda
);
LOG_D
(
NR_MAC
,
"num_dmrs_cdm_grps_no_data %d, tbs %d
\n
"
,
num_dmrs_cdm_grps_no_data
,
retInfo
->
tb_size
);
if
(
tda
==
retInfo
->
time_domain_allocation
)
{
...
...
@@ -1249,7 +1136,7 @@ void pf_ul(module_id_t module_id,
const
uint8_t
nrOfLayers
=
1
;
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
sched_ctrl
->
active_ubwp
||
ubwpd
)
?
1
:
2
;
int
dci_format
=
get_dci_format
(
sched_ctrl
);
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
nrmac
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
0
;
const
int
tda
=
s
et_ul_tda
(
nrmac
,
scc
,
slot
)
;
if
(
ps
->
time_domain_allocation
!=
tda
||
ps
->
dci_format
!=
dci_format
||
ps
->
nrOfLayers
!=
nrOfLayers
...
...
@@ -1389,7 +1276,7 @@ void pf_ul(module_id_t module_id,
const
uint8_t
nrOfLayers
=
1
;
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
sched_ctrl
->
active_ubwp
||
ubwpd
)
?
1
:
2
;
int
dci_format
=
get_dci_format
(
sched_ctrl
);
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
nrmac
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
0
;
const
int
tda
=
s
et_ul_tda
(
nrmac
,
scc
,
slot
)
;
if
(
ps
->
time_domain_allocation
!=
tda
||
ps
->
dci_format
!=
dci_format
||
ps
->
nrOfLayers
!=
nrOfLayers
...
...
@@ -1482,7 +1369,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
* schedule now (slot + k2 is not UL slot) */
int
UE_id
=
UE_info
->
list
.
head
;
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
nr_mac
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
0
;
const
int
tda
=
s
et_ul_tda
(
nr_mac
,
scc
,
slot
)
;
if
(
tda
<
0
)
return
false
;
int
K2
=
get_K2
(
scc
,
scc_sib1
,
sched_ctrl
->
active_ubwp
,
tda
,
mu
);
...
...
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
d3f90a90
...
...
@@ -523,7 +523,7 @@ uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
int
get_dci_format
(
NR_UE_sched_ctrl_t
*
sched_ctrl
);
const
int
set_dl_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
);
void
calculate_preferred_ul_tda
(
module_id_t
module_id
,
const
NR_BWP_Uplink_t
*
ubwp
);
const
int
set_ul_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
);
bool
find_free_CCE
(
module_id_t
module_id
,
sub_frame_t
slot
,
int
UE_id
);
...
...
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @
d3f90a90
...
...
@@ -809,10 +809,6 @@ typedef struct gNB_MAC_INST_s {
uint64_t
dlsch_slot_bitmap
[
3
];
/// bitmap of ULSCH slots, can hold up to 160 slots
uint64_t
ulsch_slot_bitmap
[
3
];
/// Lookup for preferred time domain allocation for UL BWP, dynamically
/// allocated. The index refers to the DL slot, and the indicated TDA's k2
/// points to the right UL slot
int
*
preferred_ul_tda
[
MAX_NUM_BWP
];
/// maximum number of slots before a UE will be scheduled ULSCH automatically
uint32_t
ulsch_max_frame_inactivity
;
...
...
openair2/RRC/NR/nr_rrc_config.c
View file @
d3f90a90
...
...
@@ -372,18 +372,19 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
uint8_t
DELTA
[
4
]
=
{
2
,
3
,
4
,
6
};
// Delta parameter for Msg3
int
mu
=
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
subcarrierSpacing
;
// UL TDA index 0 is basic slot configuration starting in symbol 0 til the last but one symbol
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
pusch_timedomainresourceallocation
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
0
,
13
);
// basic slot configuration starting in symbol 0 til the last but one symbol
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
0
,
13
);
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
if
(
frame_type
==
TDD
)
{
// TDD
if
(
scc
->
tdd_UL_DL_ConfigurationCommon
)
{
int
ul_symb
=
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
nrofUplinkSymbols
;
if
(
ul_symb
>
1
)
{
// UL TDA index 1 for mixed slot (TDD)
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
...
...
@@ -391,7 +392,7 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
14
-
ul_symb
,
ul_symb
-
1
);
// starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
// for msg3 in the mixed slot
// UL TDA index 2 for msg3 in the mixed slot (TDD)
int
nb_periods_per_frame
=
get_nb_periods_per_frame
(
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
dl_UL_TransmissionPeriodicity
);
int
nb_slots_per_period
=
((
1
<<
mu
)
*
10
)
/
nb_periods_per_frame
;
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation_msg3
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
...
...
@@ -406,6 +407,7 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation_msg3
);
}
}
}
}
...
...
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