MAC procedures to handle DLSCH allocation type 0

nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h

@@ -337,7 +337,7 @@ typedef struct
   uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
   //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
   uint8_t  resource_alloc;
-  uint8_t  rb_bitmap[36];//
+  uint8_t  rb_bitmap[36];
   uint16_t rb_start;
   uint16_t rb_size;
   uint8_t  vrb_to_prb_mapping;
@@ -438,6 +438,8 @@ typedef struct {
   uint16_t BWPSize;
   uint16_t BWPStart;
   uint8_t SubcarrierSpacing;
+  uint8_t resource_alloc;
+  uint8_t rb_bitmap[36];
   uint16_t number_rbs;
   uint16_t start_rb;
   uint16_t number_symbols;

openair1/SCHED_NR_UE/phy_procedures_nr_ue.c

@@ -513,6 +513,9 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
     uint16_t s0             = dlsch0->dlsch_config.start_symbol;
     uint16_t s1             = dlsch0->dlsch_config.number_symbols;
 
+    AssertFatal(dlsch0->dlsch_config.resource_alloc == 1,
+                "DLSCH resource allocation type0 not supported at PHY\n");
+
     LOG_D(PHY,"[UE %d] nr_slot_rx %d, harq_pid %d (%d), BWP start %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x, Nl %d\n",
           ue->Mod_id,nr_slot_rx,harq_pid,dlsch0_harq->status,BWPStart,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->dlsch_config.dlDmrsSymbPos, dlsch0->Nl);
 

openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c

@@ -2594,20 +2594,23 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
 }
 
 // Table 5.1.2.2.1-1 38.214
-uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
-  
-  AssertFatal(bwp_size < 276,"Invalid BWP Size > 275\n");
-  
-  if (bwp_size < 37)  return (rbg_size_config ? 4 : 2);
-  if (bwp_size < 73)  return (rbg_size_config ? 8 : 4);
-  if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
-  else return 16;
+uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config)
+{
+  AssertFatal(bwp_size < 276, "Invalid BWP Size %d\n", bwp_size);
+  if (bwp_size < 37)
+    return (rbg_size_config ? 4 : 2);
+  if (bwp_size < 73)
+    return (rbg_size_config ? 8 : 4);
+  if (bwp_size < 145)
+    return (rbg_size_config ? 16 : 8);
+  else
+    return 16;
 }
 
-uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
-
-  uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
-  return (uint8_t)ceil((float)(bwp_size+(bwp_start % rbg_size))/(float)rbg_size);
+uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config)
+{
+  uint8_t rbg_size = getRBGSize(bwp_size, rbg_size_config);
+  return (uint8_t)ceil((float)(bwp_size + (bwp_start % rbg_size)) / (float)rbg_size);
 }
 
 uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {

openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h

@@ -93,6 +93,8 @@ NR_tda_info_t get_ul_tda_info(const NR_UE_UL_BWP_t *ul_bwp, int controlResourceS
 NR_tda_info_t get_dl_tda_info(const NR_UE_DL_BWP_t *dl_BWP, int ss_type, int tda_index, int dmrs_typeA_pos,
                               int mux_pattern, nr_rnti_type_t rnti_type, int coresetid, bool sib1);
 
+uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config);
+
 uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
                      const NR_UE_UL_BWP_t *UL_BWP,
                      const NR_CrossCarrierSchedulingConfig_t *crossCarrierSchedulingConfig,

openair2/LAYER2/NR_MAC_UE/mac_proto.h

@@ -391,9 +391,11 @@ void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach
 
 int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu,
                                                       fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
+                                                      NR_PDSCH_Config_t *pdsch_Config,
                                                       uint16_t n_RB_ULBWP,
                                                       uint16_t n_RB_DLBWP,
-                                                      uint16_t riv);
+                                                      int start_DLBWP,
+                                                      dci_field_t frequency_domain_assignment);
 
 void build_ssb_to_ro_map(NR_UE_MAC_INST_t *mac);
 

openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c

@@ -316,38 +316,63 @@ int8_t nr_ue_decode_BCCH_DL_SCH(module_id_t module_id,
  */
 int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu,
                                                       fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
+                                                      NR_PDSCH_Config_t *pdsch_Config,
                                                       uint16_t n_RB_ULBWP,
                                                       uint16_t n_RB_DLBWP,
-                                                      uint16_t riv)
+                                                      int start_DLBWP,
+                                                      dci_field_t frequency_domain_assignment)
 {
 
   /*
    * TS 38.214 subclause 5.1.2.2 Resource allocation in frequency domain (downlink)
    * when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used
    */
-  if(dlsch_config_pdu != NULL){
-
-    /*
-     * TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
-     */
-    /*
-     * TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1
-     */
+  if(dlsch_config_pdu != NULL) {
+    if (pdsch_Config &&
+        pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType0) {
+      // TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
+      dlsch_config_pdu->resource_alloc = 0;
+      int P = getRBGSize(n_RB_DLBWP, pdsch_Config->rbg_Size);
+      int n_RBG = frequency_domain_assignment.nbits;
+      int index = 0;
+      for (int i = 0; i < n_RBG; i++) {
+        // The order of RBG bitmap is such that RBG 0 to RBG n_RBG − 1 are mapped from MSB to LSB
+        int bit_rbg = (frequency_domain_assignment.val >> (n_RBG - 1 - i)) & 0x01;
+        int size_RBG;
+        if (i == n_RBG - 1)
+          size_RBG = (start_DLBWP + n_RB_DLBWP) % P > 0 ?
+                     (start_DLBWP + n_RB_DLBWP) % P :
+                     P;
+        else if (i == 0)
+          size_RBG = P - (start_DLBWP % P);
+        else
+          size_RBG = P;
+        for (int j = index; j < size_RBG; j++)
+          dlsch_config_pdu->rb_bitmap[j / 8] |= bit_rbg << (j % 8);
+        index += size_RBG;
+      }
+    }
+    else if (pdsch_Config &&
+             pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_dynamicSwitch)
+      AssertFatal(false, "DLSCH dynamic switch allocation not yet supported\n");
+    else {
+      // TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1
+      dlsch_config_pdu->resource_alloc = 1;
+      int riv = frequency_domain_assignment.val;
       dlsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_DLBWP);
       dlsch_config_pdu->start_rb   = NRRIV2PRBOFFSET(riv,n_RB_DLBWP);
 
       // Sanity check in case a false or erroneous DCI is received
-    if ((dlsch_config_pdu->number_rbs < 1 ) || (dlsch_config_pdu->number_rbs > n_RB_DLBWP - dlsch_config_pdu->start_rb)) {
+      if ((dlsch_config_pdu->number_rbs < 1) || (dlsch_config_pdu->number_rbs > n_RB_DLBWP - dlsch_config_pdu->start_rb)) {
         // DCI is invalid!
         LOG_W(MAC, "Frequency domain assignment values are invalid! #RBs: %d, Start RB: %d, n_RB_DLBWP: %d \n", dlsch_config_pdu->number_rbs, dlsch_config_pdu->start_rb, n_RB_DLBWP);
         return -1;
       }
-
       LOG_D(MAC,"DLSCH riv = %i\n", riv);
       LOG_D(MAC,"DLSCH n_RB_DLBWP = %i\n", n_RB_DLBWP);
       LOG_D(MAC,"DLSCH number_rbs = %i\n", dlsch_config_pdu->number_rbs);
       LOG_D(MAC,"DLSCH start_rb = %i\n", dlsch_config_pdu->start_rb);
-
+    }
   }
   if(pusch_config_pdu != NULL){
     /*
@@ -359,7 +384,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
     /*
      * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1
      */
-
+    int riv = frequency_domain_assignment.val;
     pusch_config_pdu->rb_size  = NRRIV2BW(riv,n_RB_ULBWP);
     pusch_config_pdu->rb_start = NRRIV2PRBOFFSET(riv,n_RB_ULBWP);
 
@@ -643,7 +668,13 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
 
   /* IDENTIFIER_DCI_FORMATS */
   /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
-  if (nr_ue_process_dci_freq_dom_resource_assignment(NULL, dlsch_pdu, 0, dlsch_pdu->BWPSize, dci->frequency_domain_assignment.val)
+  if (nr_ue_process_dci_freq_dom_resource_assignment(NULL,
+                                                     dlsch_pdu,
+                                                     NULL,
+                                                     0,
+                                                     dlsch_pdu->BWPSize,
+                                                     0,
+                                                     dci->frequency_domain_assignment)
       < 0) {
     LOG_W(MAC, "[%d.%d] Invalid frequency_domain_assignment. Possibly due to false DCI. Ignoring DCI!\n", frame, slot);
     return -1;
@@ -912,9 +943,11 @@ static int nr_ue_process_dci_dl_11(module_id_t module_id,
   /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
   if (nr_ue_process_dci_freq_dom_resource_assignment(NULL,
                                                      dlsch_pdu,
+                                                     pdsch_Config,
                                                      0,
                                                      current_DL_BWP->BWPSize,
-                                                     dci->frequency_domain_assignment.val)
+                                                     current_DL_BWP->BWPStart,
+                                                     dci->frequency_domain_assignment)
       < 0) {
     LOG_W(MAC, "[%d.%d] Invalid frequency_domain_assignment. Possibly due to false DCI. Ignoring DCI!\n", frame, slot);
     return -1;

openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c

@@ -467,8 +467,15 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
     else
       mask = (1 << (28 - (int)(ceil(log2((ibwp_size*(ibwp_size+1))>>1))))) - 1;
 
-    int f_alloc = rar_grant->Msg3_f_alloc & mask;
-    if (nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu, NULL, ibwp_size, 0, f_alloc) < 0)
+    dci_field_t f_alloc;
+    f_alloc.val = rar_grant->Msg3_f_alloc & mask;
+    if (nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu,
+                                                       NULL,
+                                                       NULL,
+                                                       ibwp_size,
+                                                       0,
+                                                       0,
+                                                       f_alloc) < 0)
       return -1;
 
     // virtual resource block to physical resource mapping for Msg3 PUSCH (6.3.1.7 in 38.211)
@@ -598,7 +605,13 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
 
     /* IDENTIFIER_DCI_FORMATS */
     /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
-    if (nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu, NULL, current_UL_BWP->BWPSize, 0, dci->frequency_domain_assignment.val) < 0){
+    if (nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu,
+                                                       NULL,
+                                                       NULL,
+                                                       current_UL_BWP->BWPSize,
+                                                       0,
+                                                       0,
+                                                       dci->frequency_domain_assignment) < 0) {
       return -1;
     }