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lizhongxiao
OpenXG-RAN
Commits
d964cf60
Commit
d964cf60
authored
Apr 01, 2021
by
rmagueta
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Fix for RA when Msg3 fails
parent
4a807dd0
Changes
3
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3 changed files
with
13 additions
and
4 deletions
+13
-4
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+2
-0
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+4
-4
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+7
-0
No files found.
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @
d964cf60
...
@@ -84,6 +84,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
...
@@ -84,6 +84,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
}
}
else
if
(
dl_config
->
dl_config_list
[
i
].
pdu_type
==
FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH
){
else
if
(
dl_config
->
dl_config_list
[
i
].
pdu_type
==
FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH
){
dlsch0
=
PHY_vars_UE_g
[
module_id
][
cc_id
]
->
dlsch_ra
[
0
];
dlsch0
=
PHY_vars_UE_g
[
module_id
][
cc_id
]
->
dlsch_ra
[
0
];
dlsch0
->
rnti_type
=
_RA_RNTI_
;
dlsch0
->
harq_processes
[
dlsch0
->
current_harq_pid
]
->
status
=
ACTIVE
;
}
}
else
if
(
dl_config
->
dl_config_list
[
i
].
pdu_type
==
FAPI_NR_DL_CONFIG_TYPE_SI_DLSCH
){
else
if
(
dl_config
->
dl_config_list
[
i
].
pdu_type
==
FAPI_NR_DL_CONFIG_TYPE_SI_DLSCH
){
dlsch0
=
PHY_vars_UE_g
[
module_id
][
cc_id
]
->
dlsch_SI
[
0
];
dlsch0
=
PHY_vars_UE_g
[
module_id
][
cc_id
]
->
dlsch_SI
[
0
];
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
d964cf60
...
@@ -444,19 +444,19 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
...
@@ -444,19 +444,19 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
uint8_t
start_next_period
=
(
rach_slot
-
(
rach_slot
%
tdd_period_slot
)
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
uint8_t
start_next_period
=
(
rach_slot
-
(
rach_slot
%
tdd_period_slot
)
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_slot
=
start_next_period
+
last_dl_slot_period
;
// initializing scheduling of slot to next mixed (or last dl) slot
*
msg2_slot
=
start_next_period
+
last_dl_slot_period
;
// initializing scheduling of slot to next mixed (or last dl) slot
*
msg2_frame
=
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
)
;
*
msg2_frame
=
(
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
))
%
1024
;
// we can't schedule msg2 before sl_ahead since prach
// we can't schedule msg2 before sl_ahead since prach
int
eff_slot
=
*
msg2_slot
+
(
*
msg2_frame
-
rach_frame
)
*
nr_slots_per_frame
[
mu
];
int
eff_slot
=
*
msg2_slot
+
(
*
msg2_frame
-
rach_frame
)
*
nr_slots_per_frame
[
mu
];
if
((
eff_slot
-
rach_slot
)
<=
sl_ahead
)
{
if
((
eff_slot
-
rach_slot
)
<=
sl_ahead
)
{
*
msg2_slot
=
(
*
msg2_slot
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_slot
=
(
*
msg2_slot
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_frame
=
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
)
;
*
msg2_frame
=
(
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
))
%
1024
;
}
}
if
(
FR
==
nr_FR2
)
{
if
(
FR
==
nr_FR2
)
{
int
num_tdd_period
=
*
msg2_slot
/
tdd_period_slot
;
int
num_tdd_period
=
*
msg2_slot
/
tdd_period_slot
;
while
((
tdd_beam_association
[
num_tdd_period
]
!=-
1
)
&&
(
tdd_beam_association
[
num_tdd_period
]
!=
beam_index
))
{
while
((
tdd_beam_association
[
num_tdd_period
]
!=-
1
)
&&
(
tdd_beam_association
[
num_tdd_period
]
!=
beam_index
))
{
*
msg2_slot
=
(
*
msg2_slot
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_slot
=
(
*
msg2_slot
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_frame
=
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
)
;
*
msg2_frame
=
(
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
))
%
1024
;
num_tdd_period
=
*
msg2_slot
/
tdd_period_slot
;
num_tdd_period
=
*
msg2_slot
/
tdd_period_slot
;
}
}
if
(
tdd_beam_association
[
num_tdd_period
]
==
-
1
)
if
(
tdd_beam_association
[
num_tdd_period
]
==
-
1
)
...
@@ -692,7 +692,7 @@ void nr_get_Msg3alloc(module_id_t module_id,
...
@@ -692,7 +692,7 @@ void nr_get_Msg3alloc(module_id_t module_id,
if
(
nr_slots_per_frame
[
mu
]
>
temp_slot
)
if
(
nr_slots_per_frame
[
mu
]
>
temp_slot
)
ra
->
Msg3_frame
=
current_frame
;
ra
->
Msg3_frame
=
current_frame
;
else
else
ra
->
Msg3_frame
=
current_frame
+
(
temp_slot
/
nr_slots_per_frame
[
mu
])
;
ra
->
Msg3_frame
=
(
current_frame
+
(
temp_slot
/
nr_slots_per_frame
[
mu
]))
%
1024
;
// beam association for FR2
// beam association for FR2
if
(
*
scc
->
downlinkConfigCommon
->
frequencyInfoDL
->
frequencyBandList
.
list
.
array
[
0
]
>=
257
)
{
if
(
*
scc
->
downlinkConfigCommon
->
frequencyInfoDL
->
frequencyBandList
.
list
.
array
[
0
]
>=
257
)
{
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
d964cf60
...
@@ -520,6 +520,13 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
...
@@ -520,6 +520,13 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
"expected TC_RNTI %04x to match current RNTI %04x
\n
"
,
"expected TC_RNTI %04x to match current RNTI %04x
\n
"
,
ra
->
rnti
,
ra
->
rnti
,
current_rnti
);
current_rnti
);
if
(
(
frameP
==
ra
->
Msg3_frame
)
&&
(
slotP
==
ra
->
Msg3_slot
)
)
{
LOG_W
(
NR_MAC
,
"Random Access %i failed at state %i
\n
"
,
i
,
ra
->
state
);
nr_mac_remove_ra_rnti
(
gnb_mod_idP
,
ra
->
rnti
);
nr_clear_ra_proc
(
gnb_mod_idP
,
CC_idP
,
frameP
,
ra
);
}
continue
;
continue
;
}
}
...
...
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