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Commit 21e5a616 authored by Niccolò Iardella's avatar Niccolò Iardella
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Split accounting and positioning in pre_processor

parent 8acf8456
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Showing with 292 additions and 247 deletions
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
View file @ 21e5a616
...@@ -708,7 +708,6 @@ schedule_ue_spec(module_id_t module_idP,slice_id_t slice_idP, ...@@ -708,7 +708,6 @@ schedule_ue_spec(module_id_t module_idP,slice_id_t slice_idP,
slice_idP, slice_idP,
frameP, frameP,
subframeP, subframeP,
N_RBG,
mbsfn_flag); mbsfn_flag);
stop_meas(&eNB->schedule_dlsch_preprocessor); stop_meas(&eNB->schedule_dlsch_preprocessor);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
......
openair2/LAYER2/MAC/pre_processor.c
View file @ 21e5a616
...@@ -187,12 +187,11 @@ store_dlsch_buffer(module_id_t Mod_id, slice_id_t slice_id, frame_t frameP, ...@@ -187,12 +187,11 @@ store_dlsch_buffer(module_id_t Mod_id, slice_id_t slice_id, frame_t frameP,
// This function returns the estimated number of RBs required by each UE for downlink scheduling // This function returns the estimated number of RBs required by each UE for downlink scheduling
void void
assign_rbs_required(module_id_t Mod_id, assign_rbs_required(module_id_t Mod_id,
slice_id_t slice_id, slice_id_t slice_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframe, sub_frame_t subframe,
uint16_t int min_rb_unit[MAX_NUM_CCs],
nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX])
int min_rb_unit[MAX_NUM_CCs])
{ {
uint16_t TBS = 0; uint16_t TBS = 0;
...@@ -620,37 +619,31 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -620,37 +619,31 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
slice_id_t slice_id, slice_id_t slice_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs], int min_rb_unit[MAX_NUM_CCs],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX], uint8_t total_ue_count[MAX_NUM_CCs],
uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX], uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX])
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX]) { {
int UE_id, CC_id; int UE_id, CC_id;
int ii, r1; int i;
rnti_t rnti; rnti_t rnti;
uint8_t harq_pid, round, transmission_mode; uint8_t harq_pid, round;
uint8_t total_rbs_used[MAX_NUM_CCs]; uint8_t total_rbs_used[MAX_NUM_CCs];
uint8_t total_ue_count[MAX_NUM_CCs];
uint16_t average_rbs_per_user[MAX_NUM_CCs]; uint16_t average_rbs_per_user[MAX_NUM_CCs];
uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
int N_RB_DL; int N_RB_DL;
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
UE_sched_ctrl *ue_sched_ctl; UE_sched_ctrl *ue_sched_ctl;
COMMON_channels_t *cc; COMMON_channels_t *cc;
// Reset
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
total_ue_count[CC_id] = 0; total_ue_count[CC_id] = 0;
total_rbs_used[CC_id] = 0; total_rbs_used[CC_id] = 0;
average_rbs_per_user[CC_id] = 0; average_rbs_per_user[CC_id] = 0;
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; ++UE_id) {
nb_rbs_required_remaining[CC_id][UE_id] = 0;
}
} }
// loop over all active UEs // loop over all active UEs
...@@ -664,8 +657,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -664,8 +657,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
if (!ue_slice_membership(UE_id, slice_id)) if (!ue_slice_membership(UE_id, slice_id))
continue; continue;
for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[ii][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
cc = &RC.mac[Mod_id]->common_channels[CC_id]; cc = &RC.mac[Mod_id]->common_channels[CC_id];
// TODO Can we use subframe2harqpid() here? // TODO Can we use subframe2harqpid() here?
...@@ -700,8 +693,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -700,8 +693,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
if (!ue_slice_membership(UE_id, slice_id)) if (!ue_slice_membership(UE_id, slice_id))
continue; continue;
for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[ii][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
// hypothetical assignment // hypothetical assignment
/* /*
...@@ -745,8 +738,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -745,8 +738,8 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
if (!ue_slice_membership(UE_id, slice_id)) if (!ue_slice_membership(UE_id, slice_id))
continue; continue;
for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[ii][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
cc = &RC.mac[Mod_id]->common_channels[CC_id]; cc = &RC.mac[Mod_id]->common_channels[CC_id];
// TODO Can we use subframe2harqpid() here? // TODO Can we use subframe2harqpid() here?
...@@ -765,15 +758,38 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -765,15 +758,38 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
} }
} }
} }
}
void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id,
slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]) {
int UE_id, CC_id;
int i;
uint8_t transmission_mode;
uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX];
uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
rnti_t rnti;
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
decode_slice_positioning(Mod_id, slice_id, slice_allocation_mask);
//Allocation to UEs is done in 2 rounds, //Allocation to UEs is done in 2 rounds,
// 1st stage: average number of RBs allocated to each UE // 1st stage: average number of RBs allocated to each UE
// 2nd stage: remaining RBs are allocated to high priority UEs // 2nd stage: remaining RBs are allocated to high priority UEs
for (r1 = 0; r1 < 2; r1++) { for (int r1 = 0; r1 < 2; r1++) {
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[ii][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
if (r1 == 0) { if (r1 == 0) {
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] =
...@@ -803,9 +819,9 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -803,9 +819,9 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[ii][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
// if there are UEs with traffic // if there are UEs with traffic
if (total_ue_count[CC_id] > 0) { if (total_ue_count[CC_id] > 0) {
// ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; // ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
...@@ -862,10 +878,10 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -862,10 +878,10 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
&& (nb_rbs_required_remaining[CC_id][UE_id] && (nb_rbs_required_remaining[CC_id][UE_id]
> 0)) { > 0)) {
for (ii = UE_list->next[UE_id + 1]; ii >= 0; for (i = UE_list->next[UE_id + 1]; i >= 0;
ii = UE_list->next[ii]) { i = UE_list->next[i]) {
UE_id2 = ii; UE_id2 = i;
rnti2 = UE_RNTI(Mod_id, UE_id2); rnti2 = UE_RNTI(Mod_id, UE_id2);
ue_sched_ctl2 = ue_sched_ctl2 =
&UE_list->UE_sched_ctrl[UE_id2]; &UE_list->UE_sched_ctrl[UE_id2];
...@@ -1016,19 +1032,19 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1016,19 +1032,19 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
slice_id_t slice_id, slice_id_t slice_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int N_RBG[MAX_NUM_CCs],
int *mbsfn_flag) { int *mbsfn_flag) {
int UE_id; int UE_id;
uint8_t CC_id; uint8_t CC_id;
uint16_t i, j; uint16_t i, j;
int N_RBG[MAX_NUM_CCs];
int min_rb_unit[MAX_NUM_CCs];
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX]; uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX];
uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX]; uint8_t total_ue_count[MAX_NUM_CCs];
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; // If TM5 is revisited, we can move this inside accounting uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; // If TM5 is revisited, we can move this inside accounting
int min_rb_unit[MAX_NUM_CCs];
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
UE_sched_ctrl *ue_sched_ctl; UE_sched_ctrl *ue_sched_ctl;
...@@ -1045,59 +1061,43 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1045,59 +1061,43 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
UE_sched_ctrl *ue_sched_ctl1, *ue_sched_ctl2; UE_sched_ctrl *ue_sched_ctl1, *ue_sched_ctl2;
#endif #endif
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { // Initialize scheduling information for all active UEs
dlsch_scheduler_pre_processor_reset(Mod_id, slice_id, frameP, subframeP,
if (mbsfn_flag[CC_id] > 0) // If this CC is allocated for MBSFN skip it here N_RBG,
continue; min_rb_unit,
nb_rbs_required,
min_rb_unit[CC_id] = get_min_rb_unit(Mod_id, CC_id); rballoc_sub,
MIMO_mode_indicator,
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; ++UE_id) { mbsfn_flag); // TODO Not sure if useful
if (UE_list->active[UE_id] != TRUE)
continue;
if (!ue_slice_membership(UE_id, slice_id))
continue;
// Initialize scheduling information for all active UEs
dlsch_scheduler_pre_processor_reset(Mod_id,
UE_id,
CC_id,
frameP,
subframeP,
N_RBG[CC_id],
nb_rbs_required,
rballoc_sub,
MIMO_mode_indicator);
}
}
// Store the DLSCH buffer for each logical channel // Store the DLSCH buffer for each logical channel
store_dlsch_buffer(Mod_id, slice_id, frameP, subframeP); store_dlsch_buffer(Mod_id, slice_id, frameP, subframeP);
// Calculate the number of RBs required by each UE on the basis of logical channel's buffer // Calculate the number of RBs required by each UE on the basis of logical channel's buffer
assign_rbs_required(Mod_id, slice_id, frameP, subframeP, nb_rbs_required, min_rb_unit); assign_rbs_required(Mod_id, slice_id, frameP, subframeP,
min_rb_unit,
nb_rbs_required);
// Sorts the user on the basis of dlsch logical channel buffer and CQI // Sorts the user on the basis of dlsch logical channel buffer and CQI
sort_UEs(Mod_id, slice_id, frameP, subframeP); sort_UEs(Mod_id, slice_id, frameP, subframeP);
// TODO: When accounting() is revised, this will be moved inside positioning()
decode_slice_positioning(Mod_id, slice_id, slice_allocation_mask);
// ACCOUNTING // ACCOUNTING
// This function does the main allocation of the *number* of RBs // This procedure decides the number of RBs to allocate
dlsch_scheduler_pre_processor_accounting(Mod_id, dlsch_scheduler_pre_processor_accounting(Mod_id, slice_id, frameP, subframeP,
slice_id,
frameP,
subframeP,
N_RBG,
min_rb_unit, min_rb_unit,
rballoc_sub, total_ue_count,
slice_allocation_mask, nb_rbs_required,
MIMO_mode_indicator, nb_rbs_accounted);
nb_rbs_required); // POSITIONING
// This procedure does the main allocation of the RBs
dlsch_scheduler_pre_processor_positioning(Mod_id, slice_id,
N_RBG,
min_rb_unit,
total_ue_count,
nb_rbs_required,
nb_rbs_accounted,
rballoc_sub,
MIMO_mode_indicator);
#ifdef TM5 #ifdef TM5
// This has to be revisited!!!! // This has to be revisited!!!!
...@@ -1169,188 +1169,220 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1169,188 +1169,220 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
#define SF0_LIMIT 1 #define SF0_LIMIT 1
void void
dlsch_scheduler_pre_processor_reset(int module_idP, dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
int UE_id, slice_id_t slice_id,
uint8_t CC_id, frame_t frameP,
int frameP, sub_frame_t subframeP,
int subframeP, int N_RBG[MAX_NUM_CCs],
int N_RBG, int min_rb_unit[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs] uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
[NUMBER_OF_UE_MAX], unsigned char rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
unsigned char unsigned char MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX],
rballoc_sub[MAX_NUM_CCs] int *mbsfn_flag)
[N_RBG_MAX],
unsigned char
MIMO_mode_indicator[MAX_NUM_CCs]
[N_RBG_MAX])
{ {
int UE_id;
uint8_t CC_id;
int i, j; int i, j;
UE_list_t *UE_list = &RC.mac[module_idP]->UE_list; int N_RB_DL, RBGsize, RBGsize_last;
UE_sched_ctrl *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
rnti_t rnti = UE_RNTI(module_idP, UE_id);
uint8_t *vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map;
int N_RB_DL =
to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth);
int RBGsize = N_RB_DL / N_RBG, RBGsize_last;
#ifdef SF0_LIMIT #ifdef SF0_LIMIT
int sf0_upper = -1, sf0_lower = -1; int sf0_lower, sf0_upper;
#endif #endif
rnti_t rnti;
UE_list_t *UE_list;
UE_sched_ctrl *ue_sched_ctl;
uint8_t *vrb_map;
COMMON_channels_t *cc;
//
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
cc = &RC.mac[module_idP]->common_channels[CC_id];
N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth);
min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id);
if (mbsfn_flag[CC_id] > 0) // If this CC is allocated for MBSFN skip it here
continue;
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; ++UE_id) {
UE_list = &RC.mac[module_idP]->UE_list;
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
rnti = UE_RNTI(module_idP, UE_id);
LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti);
// initialize harq_pid and round
if (ue_sched_ctl->ta_timer) if (rnti == NOT_A_RNTI)
ue_sched_ctl->ta_timer--; continue;
/* if (UE_list->active[UE_id] != TRUE)
eNB_UE_stats *eNB_UE_stats; continue;
if (eNB_UE_stats == NULL) if (!ue_slice_membership(UE_id, slice_id))
return; continue;
vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map;
N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth);
mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti, #ifdef SF0_LIMIT
frameP,subframeP, sf0_lower = -1;
&ue_sched_ctl->harq_pid[CC_id], sf0_upper = -1;
&ue_sched_ctl->round[CC_id], #endif
openair_harq_DL);
LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti);
// initialize harq_pid and round
if (ue_sched_ctl->ta_timer)
ue_sched_ctl->ta_timer--;
/*
eNB_UE_stats *eNB_UE_stats;
if (ue_sched_ctl->ta_timer == 0) { if (eNB_UE_stats == NULL)
return;
// WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,
switch (N_RB_DL) { frameP,subframeP,
case 6: &ue_sched_ctl->harq_pid[CC_id],
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update; &ue_sched_ctl->round[CC_id],
break; openair_harq_DL);
case 15:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2;
break;
case 25: if (ue_sched_ctl->ta_timer == 0) {
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4;
break;
case 50: // WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8;
break;
case 75: ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12; switch (N_RB_DL) {
break; case 6:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update;
break;
case 100: case 15:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16; ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2;
break; break;
}
// clear the update in case PHY does not have a new measurement after timer expiry
eNB_UE_stats->timing_advance_update = 0;
}
else {
ue_sched_ctl->ta_timer--;
ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
}
case 25:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4;
break;
if (UE_id==0) { case 50:
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update); ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8;
} break;
*/
nb_rbs_required[CC_id][UE_id] = 0; case 75:
ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0; ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12;
ue_sched_ctl->dl_pow_off[CC_id] = 2; break;
switch (N_RB_DL) { case 100:
case 6: ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16;
RBGsize = 1; break;
RBGsize_last = 1; }
break; // clear the update in case PHY does not have a new measurement after timer expiry
case 15: eNB_UE_stats->timing_advance_update = 0;
RBGsize = 2; }
RBGsize_last = 1; else {
break; ue_sched_ctl->ta_timer--;
case 25: ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
RBGsize = 2; }
RBGsize_last = 1;
break;
case 50: if (UE_id==0) {
RBGsize = 3; VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update);
RBGsize_last = 2; }
break; */
case 75:
RBGsize = 4; nb_rbs_required[CC_id][UE_id] = 0;
RBGsize_last = 3; ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
break; ue_sched_ctl->dl_pow_off[CC_id] = 2;
case 100:
RBGsize = 4; switch (N_RB_DL) {
RBGsize_last = 4; case 6:
break; RBGsize = 1;
default: RBGsize_last = 1;
AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); break;
} case 15:
RBGsize = 2;
RBGsize_last = 1;
break;
case 25:
RBGsize = 2;
RBGsize_last = 1;
break;
case 50:
RBGsize = 3;
RBGsize_last = 2;
break;
case 75:
RBGsize = 4;
RBGsize_last = 3;
break;
case 100:
RBGsize = 4;
RBGsize_last = 4;
break;
default:
AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL);
}
#ifdef SF0_LIMIT #ifdef SF0_LIMIT
switch (N_RBG) { switch (N_RBG[CC_id]) {
case 6: case 6:
sf0_lower = 0; sf0_lower = 0;
sf0_upper = 5; sf0_upper = 5;
break; break;
case 8: case 8:
sf0_lower = 2; sf0_lower = 2;
sf0_upper = 5; sf0_upper = 5;
break; break;
case 13: case 13:
sf0_lower = 4; sf0_lower = 4;
sf0_upper = 7; sf0_upper = 7;
break; break;
case 17: case 17:
sf0_lower = 7; sf0_lower = 7;
sf0_upper = 9; sf0_upper = 9;
break; break;
case 25: case 25:
sf0_lower = 11; sf0_lower = 11;
sf0_upper = 13; sf0_upper = 13;
break; break;
default: default:
AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL);
} }
#endif #endif
// Initialize Subbands according to VRB map // Initialize Subbands according to VRB map
for (i = 0; i < N_RBG; i++) { for (i = 0; i < N_RBG[CC_id]; i++) {
int rb_size = i == N_RBG - 1 ? RBGsize_last : RBGsize; int rb_size = i == N_RBG[CC_id] - 1 ? RBGsize_last : RBGsize;
ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0; ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
rballoc_sub[CC_id][i] = 0; rballoc_sub[CC_id][i] = 0;
#ifdef SF0_LIMIT #ifdef SF0_LIMIT
// for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors) // for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors)
/* TODO: make it proper - allocate those RBs, do not "protect" them, but /* TODO: make it proper - allocate those RBs, do not "protect" them, but
* compute number of available REs and limit MCS according to the * compute number of available REs and limit MCS according to the
* TBS table 36.213 7.1.7.2.1-1 (can be done after pre-processor) * TBS table 36.213 7.1.7.2.1-1 (can be done after pre-processor)
*/ */
if (subframeP == 0 && i >= sf0_lower && i <= sf0_upper) if (subframeP == 0 && i >= sf0_lower && i <= sf0_upper)
rballoc_sub[CC_id][i] = 1; rballoc_sub[CC_id][i] = 1;
#endif #endif
// for SI-RNTI,RA-RNTI and P-RNTI allocations // for SI-RNTI,RA-RNTI and P-RNTI allocations
for (j = 0; j < rb_size; j++) { for (j = 0; j < rb_size; j++) {
if (vrb_map[j + (i * RBGsize)] != 0) { if (vrb_map[j + (i*RBGsize)] != 0) {
rballoc_sub[CC_id][i] = 1; rballoc_sub[CC_id][i] = 1;
LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", frameP, subframeP, j + (i*RBGsize));
frameP, subframeP, j + (i * RBGsize)); break;
break; }
}
LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n",
frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]);
MIMO_mode_indicator[CC_id][i] = 2;
} }
} }
LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n",
frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]);
MIMO_mode_indicator[CC_id][i] = 2;
} }
} }
......
openair2/LAYER2/MAC/proto.h
View file @ 21e5a616
...@@ -201,20 +201,6 @@ void mac_UE_out_of_sync_ind(module_id_t module_idP, frame_t frameP, ...@@ -201,20 +201,6 @@ void mac_UE_out_of_sync_ind(module_id_t module_idP, frame_t frameP,
void clear_nfapi_information(eNB_MAC_INST * eNB, int CC_idP, void clear_nfapi_information(eNB_MAC_INST * eNB, int CC_idP,
frame_t frameP, sub_frame_t subframeP); frame_t frameP, sub_frame_t subframeP);
void dlsch_scheduler_pre_processor_reset(int module_idP, int UE_id,
uint8_t CC_id,
int frameP,
int subframeP,
int N_RBG,
uint16_t
nb_rbs_required[MAX_NUM_CCs]
[NUMBER_OF_UE_MAX],
unsigned char
rballoc_sub[MAX_NUM_CCs]
[N_RBG_MAX],
unsigned char
MIMO_mode_indicator[MAX_NUM_CCs]
[N_RBG_MAX]);
// eNB functions // eNB functions
/* \brief This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done /* \brief This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
...@@ -226,12 +212,40 @@ void dlsch_scheduler_pre_processor_reset(int module_idP, int UE_id, ...@@ -226,12 +212,40 @@ void dlsch_scheduler_pre_processor_reset(int module_idP, int UE_id,
void dlsch_scheduler_pre_processor(module_id_t module_idP, void dlsch_scheduler_pre_processor(module_id_t module_idP,
slice_id_t slice_idP, slice_id_t slice_idP,
frame_t frameP, frame_t frameP,
sub_frame_t subframe, sub_frame_t subframe,
int N_RBG[MAX_NUM_CCs], int *mbsfn_flag);
int *mbsfn_flag);
void dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
slice_id_t slice_id,
frame_t frameP,
sub_frame_t subframeP,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
unsigned char rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
unsigned char MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX],
int *mbsfn_flag);
void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
slice_id_t slice_id,
frame_t frameP,
sub_frame_t subframeP,
int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX]);
void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id,
slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]);
void dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id, void dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id,
int UE_id, int UE_id,
......
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