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Commit ff984699 authored by francescomani's avatar francescomani
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Merge remote-tracking branch 'origin/develop' into NR_FR2_initsync_fixes

parents 31aade20 d953b253
x2_handle_sctp_shutdown 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA NRUE_usedlschparallel NR_2port_CSIRS NR_CSIRS_tomerge NR_FR2_initsync_fixes NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS RFquality Test_SA_5GREC add-ru-docker-image avxllr benetel_dpdk20 bugfix-nr-t-reordering bugfix_gnb_rt_stats_html ci-fix-module-ul-iperf ci_benetel_longrun_limits ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_testinfra_as_code debug-UL-5GRECORDS debug_UL_signal develop develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-aw2sori develop-wf-du dongzhanyi-zte-develop1 episys-merge fedora-gen-kernel-fix fix-check fix-compile fix-physim-deploy fix-retransmission-rbg fix_nr_ulsim flexran-rtc-repo-is-public hack-bch-no-sched-sf-0 integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 ldpc_offload_t1 migrate-vm-pipeline-to-bionic nfapi_nr_arch_mod nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-small-bugfixes nr_improve_chanest oairu phy-asan-fixes physim-deploy-handle-error-cases prb_based_dl_channel_estimation rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_rfsim_sa scs_60_iisc test-5GREC test-nsa-benetel wf_testc 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a
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Showing with 33 additions and 17 deletions
ci-scripts/conf_files/benetel-5g.conf
View file @ ff984699
......@@ -66,7 +66,17 @@ gNBs =
initialDLBWPk0_1 = 0; #for mixed slot
initialDLBWPmappingType_1 = 0;
initialDLBWPstartSymbolAndLength_1 = 57; #this is SS=1,L=5
initialDLBWPstartSymbolAndLength_1 = 53; #this is SS=1,L=5
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
#uplinkConfigCommon
#frequencyInfoUL
......@@ -92,9 +102,7 @@ gNBs =
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 74;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -118;
#preambleReceivedTargetPower = -104;
#preambleReceivedTargetPower = -108;
preambleReceivedTargetPower = -108;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
......@@ -124,13 +132,13 @@ gNBs =
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
# pusch-ConfigCommon (up to 16 elements)
initialULBWPk2_0 = 6; # used for UL slot
initialULBWPk2_0 = 2; # used for UL slot
initialULBWPmappingType_0 = 1
initialULBWPstartSymbolAndLength_0 = 55; # this is SS=0 L=12
initialULBWPk2_1 = 6; # used for mixed slot
initialULBWPk2_1 = 2; # used for mixed slot
initialULBWPmappingType_1 = 1;
initialULBWPstartSymbolAndLength_1 = 24; # this is SS=10 L=2
initialULBWPstartSymbolAndLength_1 = 69; # this is SS=10 L=2
initialULBWPk2_2 = 7; # used for Msg.3 during RA
initialULBWPmappingType_2 = 1;
......
targets/PROJECTS/GENERIC-LTE-EPC/CONF/benetel-5g.conf
View file @ ff984699
......@@ -15,7 +15,8 @@ gNBs =
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;});
#plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;});
plmn_list = ({mcc = 208; mnc = 99; mnc_length = 2;});
tr_s_preference = "local_mac"
......@@ -66,7 +67,17 @@ gNBs =
initialDLBWPk0_1 = 0; #for mixed slot
initialDLBWPmappingType_1 = 0;
initialDLBWPstartSymbolAndLength_1 = 57; #this is SS=1,L=5
initialDLBWPstartSymbolAndLength_1 = 53; #this is SS=1,L=5
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
#uplinkConfigCommon
#frequencyInfoUL
......@@ -92,9 +103,7 @@ gNBs =
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 74;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -118;
#preambleReceivedTargetPower = -104;
#preambleReceivedTargetPower = -108;
preambleReceivedTargetPower = -108;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
......@@ -124,13 +133,13 @@ gNBs =
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
# pusch-ConfigCommon (up to 16 elements)
initialULBWPk2_0 = 6; # used for UL slot
initialULBWPk2_0 = 2; # used for UL slot
initialULBWPmappingType_0 = 1
initialULBWPstartSymbolAndLength_0 = 55; # this is SS=0 L=12
initialULBWPk2_1 = 6; # used for mixed slot
initialULBWPk2_1 = 2; # used for mixed slot
initialULBWPmappingType_1 = 1;
initialULBWPstartSymbolAndLength_1 = 24; # this is SS=10 L=2
initialULBWPstartSymbolAndLength_1 = 69; # this is SS=10 L=2
initialULBWPk2_2 = 7; # used for Msg.3 during RA
initialULBWPmappingType_2 = 1;
......@@ -196,7 +205,7 @@ gNBs =
////////// MME parameters:
mme_ip_address = ( { ipv4 = "192.168.18.99";
mme_ip_address = ( { ipv4 = "192.168.18.150"; #"192.168.18.99";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
......@@ -276,7 +285,6 @@ RUs = (
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
//parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_DISABLE";
......
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