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Commit 16e15b33 authored by Robert Schmidt's avatar Robert Schmidt
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Merge remote-tracking branch 'origin/develop-UL-RI' into integration_2023_w40

parents 08fca7eb e5804c48
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_srs.c
View file @ 16e15b33
...@@ -32,6 +32,10 @@ ...@@ -32,6 +32,10 @@
#include "common/ran_context.h" #include "common/ran_context.h"
#include "nfapi/oai_integration/vendor_ext.h" #include "nfapi/oai_integration/vendor_ext.h"
#include "common/utils/nr/nr_common.h" #include "common/utils/nr/nr_common.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <immintrin.h>
//#define SRS_DEBUG //#define SRS_DEBUG
...@@ -42,12 +46,112 @@ const uint16_t m_SRS[64] = { 4, 8, 12, 16, 16, 20, 24, 24, 28, 32, 36, 40, 48, 4 ...@@ -42,12 +46,112 @@ const uint16_t m_SRS[64] = { 4, 8, 12, 16, 16, 20, 24, 24, 28, 32, 36, 40, 48, 4
160, 160, 168, 176, 184, 192, 192, 192, 192, 208, 216, 224, 240, 240, 240, 240, 256, 256, 160, 160, 168, 176, 184, 192, 192, 192, 192, 208, 216, 224, 240, 240, 240, 240, 256, 256,
256, 264, 272, 272, 272 }; 256, 264, 272, 272, 272 };
static uint32_t max4(uint32_t a, uint32_t b, uint32_t c, uint32_t d) #ifdef SRS_DEBUG
static void print128_number(const simde__m128i var)
{
int32_t *var16 = (int32_t *)&var;
for (int i = 0; i < 4; i++) {
printf("%5d ", var16[i]);
}
printf("\n");
}
#endif
int most_frequent_ri(const int *arr, int n)
{ {
int x = max(a, b); int maxcount = 0;
x = max(x, c); int element_having_max_freq = -1;
x = max(x, d); for (int i = 0; i < n; i++) {
return x; int count = 0;
for (int j = 0; j < n; j++) {
if (arr[i] == arr[j])
count++;
}
if (count > maxcount) {
maxcount = count;
element_having_max_freq = arr[i];
}
}
return element_having_max_freq;
}
void matrix_rank_128bits(int row, int col, simde__m128i mat[4])
{
if ((row == 2 && col == 2) || (row == 4 && col == 2)) {
int32_t *mat_k = (int32_t *)&mat[0];
int32_t *mat_i = (int32_t *)&mat[1];
simde__m128 mult_128 = simde_mm_setr_ps((float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[2] / (float)mat_k[2],
(float)mat_i[2] / (float)mat_k[2]);
simde__m128i mat_kj_128 = simde_mm_setr_epi32(mat_k[0], mat_k[1], mat_k[2], mat_k[3]);
simde__m128 multiplication = simde_mm_mul_ps(mult_128, simde_mm_cvtepi32_ps(mat_kj_128));
mat[1] = simde_mm_sub_epi32(mat[1], simde_mm_cvtps_epi32(multiplication));
mat_k = (int32_t *)&mat[2];
mat_i = (int32_t *)&mat[3];
mult_128 = simde_mm_setr_ps((float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[2] / (float)mat_k[2],
(float)mat_i[2] / (float)mat_k[2]);
mat_kj_128 = simde_mm_setr_epi32(mat_k[0], mat_k[1], mat_k[2], mat_k[3]);
multiplication = simde_mm_mul_ps(mult_128, simde_mm_cvtepi32_ps(mat_kj_128));
mat[3] = simde_mm_sub_epi32(mat[3], simde_mm_cvtps_epi32(multiplication));
} else if (row == 2 && col == 4) {
int32_t *mat_k = (int32_t *)&mat[0];
int32_t *mat_i = (int32_t *)&mat[1];
simde__m128 mult_128 = simde_mm_setr_ps((float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0]);
simde__m128i mat_kj_128 = simde_mm_setr_epi32(mat_k[0], mat_k[1], mat_k[2], mat_k[3]);
simde__m128 multiplication = simde_mm_mul_ps(mult_128, simde_mm_cvtepi32_ps(mat_kj_128));
mat[1] = simde_mm_sub_epi32(mat[1], simde_mm_cvtps_epi32(multiplication));
mat_k = (int32_t *)&mat[2];
mat_i = (int32_t *)&mat[3];
mult_128 = simde_mm_setr_ps((float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0],
(float)mat_i[0] / (float)mat_k[0]);
mat_kj_128 = simde_mm_setr_epi32(mat_k[0], mat_k[1], mat_k[2], mat_k[3]);
multiplication = simde_mm_mul_ps(mult_128, simde_mm_cvtepi32_ps(mat_kj_128));
mat[3] = simde_mm_sub_epi32(mat[3], simde_mm_cvtps_epi32(multiplication));
} else if (row == 4 && col == 4) {
for (int k = 0; k < col; k++) {
int32_t *mat_k = (int32_t *)&mat[k];
for (int i = k + 1; i < row; i++) {
int32_t *mat_i = (int32_t *)&mat[i];
float mult = (float)mat_i[k] / (float)mat_k[k];
if (isnan(mult))
mult = 0;
if (isinf(mult))
mult = 0;
simde__m128 mult_128 = simde_mm_set1_ps(mult);
simde__m128i mat_kj_128 = simde_mm_setr_epi32(mat_k[0], mat_k[1], mat_k[2], mat_k[3]);
simde__m128 multiplication = simde_mm_mul_ps(mult_128, simde_mm_cvtepi32_ps(mat_kj_128));
mat[i] = simde_mm_sub_epi32(mat[i], simde_mm_cvtps_epi32(multiplication));
}
}
} else {
AssertFatal(1 == 0, "matrix_rank_128bits() function is not implemented for row = %i and col = %i\n", row, col);
}
} }
void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr_srs_normalized_channel_iq_matrix, void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr_srs_normalized_channel_iq_matrix,
...@@ -57,12 +161,15 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr ...@@ -57,12 +161,15 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr
/* already mutex protected: held in handle_nr_srs_measurements() */ /* already mutex protected: held in handle_nr_srs_measurements() */
NR_SCHED_ENSURE_LOCKED(&RC.nrmac[0]->sched_lock); NR_SCHED_ENSURE_LOCKED(&RC.nrmac[0]->sched_lock);
// If the gNB or UE has 1 antenna, the rank is always 1, i.e., *ul_ri = 0. #ifdef SRS_DEBUG
// For 2x2 scenario, we compute the rank of channel. LOG_I(NR_MAC, "num_gnb_antenna_elements = %i\n", nr_srs_normalized_channel_iq_matrix->num_gnb_antenna_elements);
// The computation for 2x4, 4x2, 4x4, ... scenarios are not implemented yet. In these cases, the function sets *ul_ri = 0, which is always a valid value. LOG_I(NR_MAC, "num_ue_srs_ports = %i\n", nr_srs_normalized_channel_iq_matrix->num_ue_srs_ports);
if (!(nr_srs_normalized_channel_iq_matrix->num_gnb_antenna_elements == 2 && #endif
nr_srs_normalized_channel_iq_matrix->num_ue_srs_ports == 2 &&
current_BWP->pusch_Config && *current_BWP->pusch_Config->maxRank == 2)) { if (nr_srs_normalized_channel_iq_matrix->num_gnb_antenna_elements == 1 ||
nr_srs_normalized_channel_iq_matrix->num_ue_srs_ports == 1 ||
current_BWP->pusch_Config == NULL ||
(current_BWP->pusch_Config && *current_BWP->pusch_Config->maxRank == 1)) {
*ul_ri = 0; *ul_ri = 0;
return; return;
} }
...@@ -70,75 +177,236 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr ...@@ -70,75 +177,236 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr
const c16_t *ch = (c16_t *)nr_srs_normalized_channel_iq_matrix->channel_matrix; const c16_t *ch = (c16_t *)nr_srs_normalized_channel_iq_matrix->channel_matrix;
const uint16_t num_gnb_antenna_elements = nr_srs_normalized_channel_iq_matrix->num_gnb_antenna_elements; const uint16_t num_gnb_antenna_elements = nr_srs_normalized_channel_iq_matrix->num_gnb_antenna_elements;
const uint16_t num_prgs = nr_srs_normalized_channel_iq_matrix->num_prgs; const uint16_t num_prgs = nr_srs_normalized_channel_iq_matrix->num_prgs;
const uint16_t base00_idx = 0 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 0
const uint16_t base01_idx = 1 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 1
const uint16_t base10_idx = 0 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 0
const uint16_t base11_idx = 1 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 1
const uint8_t bshift = 2;
const int16_t cond_dB_threshold = 5;
int count = 0;
for(int pI = 0; pI < num_prgs; pI++) { int row = num_gnb_antenna_elements;
int col = nr_srs_normalized_channel_iq_matrix->num_ue_srs_ports;
simde__m128i mat_real128[4];
simde__m128i mat_imag128[4];
simde__m128i sum_matrix[4];
if ((row == 2 && col == 2) || (row == 4 && col == 2)) {
int array_lim = num_prgs >> 2;
int antenna_rank[array_lim];
int count = 0;
const uint16_t base00_idx = 0 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 0
const uint16_t base01_idx = 1 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 1
const uint16_t base10_idx = 0 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 0
const uint16_t base11_idx = 1 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 1
for (int pI = 0; pI < num_prgs; pI += 4) {
uint16_t pI00 = pI + base00_idx;
uint16_t pI10 = pI + base10_idx;
uint16_t pI01 = pI + base01_idx;
uint16_t pI11 = pI + base11_idx;
mat_real128[0] = simde_mm_setr_epi32(ch[pI00].r, ch[pI10].r, ch[pI00 + 1].r, ch[pI10 + 1].r);
mat_real128[1] = simde_mm_setr_epi32(ch[pI01].r, ch[pI11].r, ch[pI01 + 1].r, ch[pI11 + 1].r);
mat_real128[2] = simde_mm_setr_epi32(ch[pI00 + 2].r, ch[pI10 + 2].r, ch[pI00 + 3].r, ch[pI10 + 3].r);
mat_real128[3] = simde_mm_setr_epi32(ch[pI01 + 2].r, ch[pI11 + 2].r, ch[pI01 + 3].r, ch[pI11 + 3].r);
mat_imag128[0] = simde_mm_setr_epi32(ch[pI00].i, ch[pI10].i, ch[pI00 + 1].i, ch[pI10 + 1].i);
mat_imag128[1] = simde_mm_setr_epi32(ch[pI01].i, ch[pI11].i, ch[pI01 + 1].i, ch[pI11 + 1].i);
mat_imag128[2] = simde_mm_setr_epi32(ch[pI00 + 2].i, ch[pI10 + 2].i, ch[pI00 + 3].i, ch[pI10 + 3].i);
mat_imag128[3] = simde_mm_setr_epi32(ch[pI01 + 2].i, ch[pI11 + 2].i, ch[pI01 + 3].i, ch[pI11 + 3].i);
matrix_rank_128bits(row, col, mat_real128);
matrix_rank_128bits(row, col, mat_imag128);
sum_matrix[0] = simde_mm_add_epi32(mat_real128[0], mat_imag128[0]);
sum_matrix[1] = simde_mm_add_epi32(mat_real128[1], mat_imag128[1]);
sum_matrix[2] = simde_mm_add_epi32(mat_real128[2], mat_imag128[2]);
sum_matrix[3] = simde_mm_add_epi32(mat_real128[3], mat_imag128[3]);
/* Hh x H = #ifdef SRS_DEBUG
* | conjch00 conjch10 | x | ch00 ch01 | = | conjch00*ch00+conjch10*ch10 conjch00*ch01+conjch10*ch11 | LOG_I(NR_MAC, "\nSum matrix\n");
* | conjch01 conjch11 | | ch10 ch11 | | conjch01*ch00+conjch11*ch10 conjch01*ch01+conjch11*ch11 | print128_number(sum_matrix[0]);
*/ print128_number(sum_matrix[1]);
print128_number(sum_matrix[2]);
print128_number(sum_matrix[3]);
#endif
const c32_t ch00 = {ch[base00_idx + pI].r, ch[base00_idx + pI].i}; int count_pivots = 0;
const c32_t ch01 = {ch[base01_idx + pI].r, ch[base01_idx + pI].i};
const c32_t ch10 = {ch[base10_idx + pI].r, ch[base10_idx + pI].i};
const c32_t ch11 = {ch[base11_idx + pI].r, ch[base11_idx + pI].i};
c16_t HhxH00 = {(int16_t)((ch00.r * ch00.r + ch00.i * ch00.i + ch10.r * ch10.r + ch10.i * ch10.i) >> bshift), int32_t *sum_matrix_i = (int32_t *)&sum_matrix[1];
(int16_t)((ch00.r * ch00.i - ch00.i * ch00.r + ch10.r * ch10.i - ch10.i * ch10.r) >> bshift)}; if (sum_matrix_i[1] != 0)
count_pivots++;
if (sum_matrix_i[3] != 0)
count_pivots++;
c16_t HhxH01 = {(int16_t)((ch00.r * ch01.r + ch00.i * ch01.i + ch10.r * ch11.r + ch10.i * ch11.i) >> bshift), sum_matrix_i = (int32_t *)&sum_matrix[3];
(int16_t)((ch00.r * ch01.i - ch00.i * ch01.r + ch10.r * ch11.i - ch10.i * ch11.r) >> bshift)}; if (sum_matrix_i[1] != 0)
count_pivots++;
if (sum_matrix_i[3] != 0)
count_pivots++;
c16_t HhxH10 = {(int16_t)((ch01.r * ch00.r + ch01.i * ch00.i + ch11.r * ch10.r + ch11.i * ch10.i) >> bshift), antenna_rank[count] = count_pivots / 4;
(int16_t)((ch01.r * ch00.i - ch01.i * ch00.r + ch11.r * ch10.i - ch11.i * ch10.r) >> bshift)}; count++;
}
*ul_ri = most_frequent_ri(antenna_rank, array_lim);
} else if (row == 2 && col == 4) {
int array_lim = num_prgs >> 1;
int antenna_rank[array_lim];
int count = 0;
const uint16_t base00_idx = 0 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 0
const uint16_t base10_idx = 1 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 1, Tx port 0
const uint16_t base20_idx = 2 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 2, Tx port 0
const uint16_t base30_idx = 3 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 3, Tx port 0
const uint16_t base01_idx = 0 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 0, Tx port 1
const uint16_t base11_idx = 1 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 1
const uint16_t base21_idx = 2 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 2, Tx port 1
const uint16_t base31_idx = 3 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 3, Tx port 1
for (int pI = 0; pI < num_prgs; pI += 2) {
mat_real128[0] = simde_mm_setr_epi32(ch[base00_idx + pI].r,
ch[base10_idx + pI].r,
ch[base20_idx + pI].r,
ch[base30_idx + pI].r);
mat_real128[1] = simde_mm_setr_epi32(ch[base01_idx + pI].r,
ch[base11_idx + pI].r,
ch[base21_idx + pI].r,
ch[base31_idx + pI].r);
mat_real128[2] = simde_mm_setr_epi32(ch[base00_idx + (pI + 1)].r,
ch[base10_idx + (pI + 1)].r,
ch[base20_idx + (pI + 1)].r,
ch[base30_idx + (pI + 1)].r);
mat_real128[3] = simde_mm_setr_epi32(ch[base01_idx + (pI + 1)].r,
ch[base11_idx + (pI + 1)].r,
ch[base21_idx + (pI + 1)].r,
ch[base31_idx + (pI + 1)].r);
mat_imag128[0] = simde_mm_setr_epi32(ch[base00_idx + pI].i,
ch[base10_idx + pI].i,
ch[base20_idx + pI].i,
ch[base30_idx + pI].i);
mat_imag128[1] = simde_mm_setr_epi32(ch[base01_idx + pI].i,
ch[base11_idx + pI].i,
ch[base21_idx + pI].i,
ch[base31_idx + pI].i);
mat_imag128[2] = simde_mm_setr_epi32(ch[base00_idx + (pI + 1)].i,
ch[base10_idx + (pI + 1)].i,
ch[base20_idx + (pI + 1)].i,
ch[base30_idx + (pI + 1)].i);
mat_imag128[3] = simde_mm_setr_epi32(ch[base01_idx + (pI + 1)].i,
ch[base11_idx + (pI + 1)].i,
ch[base21_idx + (pI + 1)].i,
ch[base31_idx + (pI + 1)].i);
matrix_rank_128bits(row, col, mat_real128);
matrix_rank_128bits(row, col, mat_imag128);
sum_matrix[0] = simde_mm_add_epi32(mat_real128[0], mat_imag128[0]);
sum_matrix[1] = simde_mm_add_epi32(mat_real128[1], mat_imag128[1]);
sum_matrix[2] = simde_mm_add_epi32(mat_real128[2], mat_imag128[2]);
sum_matrix[3] = simde_mm_add_epi32(mat_real128[3], mat_imag128[3]);
c16_t HhxH11 = {(int16_t)((ch01.r * ch01.r + ch01.i * ch01.i + ch11.r * ch11.r + ch11.i * ch11.i) >> bshift), #ifdef SRS_DEBUG
(int16_t)((ch01.r * ch01.i - ch01.i * ch01.r + ch11.r * ch11.i - ch11.i * ch11.r) >> bshift)}; LOG_I(NR_MAC, "\nSum matrix\n");
print128_number(sum_matrix[0]);
print128_number(sum_matrix[1]);
print128_number(sum_matrix[2]);
print128_number(sum_matrix[3]);
#endif
int8_t det_HhxH_dB = dB_fixed(HhxH00.r * HhxH11.r - HhxH00.i * HhxH11.i - HhxH01.r * HhxH10.r + HhxH01.i * HhxH10.i); int count_pivots = 0;
int8_t norm_HhxH_2_dB = dB_fixed(max4(HhxH00.r*HhxH00.r + HhxH00.i*HhxH00.i, int32_t *sum_matrix_i = (int32_t *)&sum_matrix[1];
HhxH01.r*HhxH01.r + HhxH01.i*HhxH01.i, if (sum_matrix_i[1] != 0)
HhxH10.r*HhxH10.r + HhxH10.i*HhxH10.i, count_pivots++;
HhxH11.r*HhxH11.r + HhxH11.i*HhxH11.i)); if (sum_matrix_i[3] != 0)
count_pivots++;
int8_t cond_db = norm_HhxH_2_dB - det_HhxH_dB; sum_matrix_i = (int32_t *)&sum_matrix[3];
if (sum_matrix_i[1] != 0)
count_pivots++;
if (sum_matrix_i[3] != 0)
count_pivots++;
if (cond_db < cond_dB_threshold) { antenna_rank[count] = count_pivots / 2;
count++; count++;
} else {
count--;
} }
#ifdef SRS_DEBUG int rr = most_frequent_ri(antenna_rank, array_lim);
LOG_I(NR_MAC, "H00[%i] = %i + j(%i)\n", pI, ch[base00_idx+pI].r, ch[base00_idx+pI].i); if (rr == 0 || rr == 1)
LOG_I(NR_MAC, "H01[%i] = %i + j(%i)\n", pI, ch[base01_idx+pI].r, ch[base01_idx+pI].i); *ul_ri = 0;
LOG_I(NR_MAC, "H10[%i] = %i + j(%i)\n", pI, ch[base10_idx+pI].r, ch[base10_idx+pI].i); if (rr > 1)
LOG_I(NR_MAC, "H11[%i] = %i + j(%i)\n", pI, ch[base11_idx+pI].r, ch[base11_idx+pI].i); *ul_ri = 1;
LOG_I(NR_MAC, "HhxH00[%i] = %i + j(%i)\n", pI, HhxH00.r, HhxH00.i);
LOG_I(NR_MAC, "HhxH01[%i] = %i + j(%i)\n", pI, HhxH01.r, HhxH01.i);
LOG_I(NR_MAC, "HhxH10[%i] = %i + j(%i)\n", pI, HhxH10.r, HhxH10.i);
LOG_I(NR_MAC, "HhxH11[%i] = %i + j(%i)\n", pI, HhxH11.r, HhxH11.i);
LOG_I(NR_MAC, "det_HhxH[%i] = %i\n", pI, det_HhxH_dB);
LOG_I(NR_MAC, "norm_HhxH_2_dB[%i] = %i\n", pI, norm_HhxH_2_dB);
#endif
}
if (count > 0) { } else if (row == 4 && col == 4) {
*ul_ri = 1;
} int antenna_rank[num_prgs];
int count = 0;
const uint16_t base00_idx = 0 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 0, Tx port 0
const uint16_t base10_idx = 1 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 1, Tx port 0
const uint16_t base20_idx = 2 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 2, Tx port 0
const uint16_t base30_idx = 3 * num_gnb_antenna_elements * num_prgs + 0 * num_prgs; // Rx antenna 3, Tx port 0
const uint16_t base01_idx = 0 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 0, Tx port 1
const uint16_t base11_idx = 1 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 1, Tx port 1
const uint16_t base21_idx = 2 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 2, Tx port 1
const uint16_t base31_idx = 3 * num_gnb_antenna_elements * num_prgs + 1 * num_prgs; // Rx antenna 3, Tx port 1
const uint16_t base02_idx = 0 * num_gnb_antenna_elements * num_prgs + 2 * num_prgs; // Rx antenna 0, Tx port 2
const uint16_t base12_idx = 1 * num_gnb_antenna_elements * num_prgs + 2 * num_prgs; // Rx antenna 1, Tx port 2
const uint16_t base22_idx = 2 * num_gnb_antenna_elements * num_prgs + 2 * num_prgs; // Rx antenna 2, Tx port 2
const uint16_t base32_idx = 3 * num_gnb_antenna_elements * num_prgs + 2 * num_prgs; // Rx antenna 3, Tx port 2
const uint16_t base03_idx = 0 * num_gnb_antenna_elements * num_prgs + 3 * num_prgs; // Rx antenna 0, Tx port 3
const uint16_t base13_idx = 1 * num_gnb_antenna_elements * num_prgs + 3 * num_prgs; // Rx antenna 1, Tx port 3
const uint16_t base23_idx = 2 * num_gnb_antenna_elements * num_prgs + 3 * num_prgs; // Rx antenna 2, Tx port 3
const uint16_t base33_idx = 3 * num_gnb_antenna_elements * num_prgs + 3 * num_prgs; // Rx antenna 3, Tx port 3
for (int pI = 0; pI < num_prgs; pI++) {
mat_real128[0] = simde_mm_setr_epi32(ch[base00_idx + pI].r, ch[base10_idx + pI].r, ch[base20_idx + pI].r, ch[base30_idx + pI].r);
mat_real128[1] = simde_mm_setr_epi32(ch[base01_idx + pI].r, ch[base11_idx + pI].r, ch[base21_idx + pI].r, ch[base31_idx + pI].r);
mat_real128[2] = simde_mm_setr_epi32(ch[base02_idx + pI].r, ch[base12_idx + pI].r, ch[base22_idx + pI].r, ch[base32_idx + pI].r);
mat_real128[3] = simde_mm_setr_epi32(ch[base03_idx + pI].r, ch[base13_idx + pI].r, ch[base23_idx + pI].r, ch[base33_idx + pI].r);
mat_imag128[0] = simde_mm_setr_epi32(ch[base00_idx + pI].i, ch[base10_idx + pI].i, ch[base20_idx + pI].i, ch[base30_idx + pI].i);
mat_imag128[1] = simde_mm_setr_epi32(ch[base01_idx + pI].i, ch[base11_idx + pI].i, ch[base21_idx + pI].i, ch[base31_idx + pI].i);
mat_imag128[2] = simde_mm_setr_epi32(ch[base02_idx + pI].i, ch[base12_idx + pI].i, ch[base22_idx + pI].i, ch[base32_idx + pI].i);
mat_imag128[3] = simde_mm_setr_epi32(ch[base03_idx + pI].i, ch[base13_idx + pI].i, ch[base23_idx + pI].i, ch[base33_idx + pI].i);
matrix_rank_128bits(row, col, mat_real128);
matrix_rank_128bits(row, col, mat_imag128);
sum_matrix[0] = simde_mm_add_epi32(mat_real128[0], mat_imag128[0]);
sum_matrix[1] = simde_mm_add_epi32(mat_real128[1], mat_imag128[1]);
sum_matrix[2] = simde_mm_add_epi32(mat_real128[2], mat_imag128[2]);
sum_matrix[3] = simde_mm_add_epi32(mat_real128[3], mat_imag128[3]);
#ifdef SRS_DEBUG #ifdef SRS_DEBUG
LOG_I(NR_MAC, "ul_ri = %i (count = %i)\n", (*ul_ri)+1, count); LOG_I(NR_MAC, "\nSum matrix\n");
print128_number(sum_matrix[0]);
print128_number(sum_matrix[1]);
print128_number(sum_matrix[2]);
print128_number(sum_matrix[3]);
#endif #endif
int count_pivots = 0;
for (int i = 0; i < row; i++) {
int32_t *sum_matrix_i = (int32_t *)&sum_matrix[i];
int found_piv = 0;
for (int j = 0; j < col; j++) {
if (sum_matrix_i[j] != 0 && found_piv == 0) {
count_pivots++;
found_piv = 1;
}
}
}
antenna_rank[count] = count_pivots;
count++;
}
*ul_ri = most_frequent_ri(antenna_rank, num_prgs) - 1;
} else {
AssertFatal(1 == 0, "nr_srs_ri_computation() function is not implemented for row = %i and col = %i\n", row, col);
}
} }
static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu,
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ 16e15b33
...@@ -1319,8 +1319,11 @@ void handle_nr_srs_measurements(const module_id_t module_id, ...@@ -1319,8 +1319,11 @@ void handle_nr_srs_measurements(const module_id_t module_id,
NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP; NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
sched_ctrl->srs_feedback.sri = NR_SRS_SRI_0; sched_ctrl->srs_feedback.sri = NR_SRS_SRI_0;
start_meas(&nr_mac->nr_srs_ri_computation_timer);
nr_srs_ri_computation(&nr_srs_channel_iq_matrix, current_BWP, &sched_ctrl->srs_feedback.ul_ri); nr_srs_ri_computation(&nr_srs_channel_iq_matrix, current_BWP, &sched_ctrl->srs_feedback.ul_ri);
stop_meas(&nr_mac->nr_srs_ri_computation_timer);
start_meas(&nr_mac->nr_srs_tpmi_computation_timer);
sched_ctrl->srs_feedback.tpmi = nr_srs_tpmi_estimation(current_BWP->pusch_Config, sched_ctrl->srs_feedback.tpmi = nr_srs_tpmi_estimation(current_BWP->pusch_Config,
current_BWP->transform_precoding, current_BWP->transform_precoding,
nr_srs_channel_iq_matrix.channel_matrix, nr_srs_channel_iq_matrix.channel_matrix,
...@@ -1330,6 +1333,7 @@ void handle_nr_srs_measurements(const module_id_t module_id, ...@@ -1330,6 +1333,7 @@ void handle_nr_srs_measurements(const module_id_t module_id,
nr_srs_channel_iq_matrix.prg_size, nr_srs_channel_iq_matrix.prg_size,
nr_srs_channel_iq_matrix.num_prgs, nr_srs_channel_iq_matrix.num_prgs,
sched_ctrl->srs_feedback.ul_ri); sched_ctrl->srs_feedback.ul_ri);
stop_meas(&nr_mac->nr_srs_tpmi_computation_timer);
sprintf(stats->srs_stats, "UL-RI %d, TPMI %d", sched_ctrl->srs_feedback.ul_ri + 1, sched_ctrl->srs_feedback.tpmi); sprintf(stats->srs_stats, "UL-RI %d, TPMI %d", sched_ctrl->srs_feedback.ul_ri + 1, sched_ctrl->srs_feedback.tpmi);
......
openair2/LAYER2/NR_MAC_gNB/main.c
View file @ 16e15b33
...@@ -69,6 +69,8 @@ void *nrmac_stats_thread(void *arg) { ...@@ -69,6 +69,8 @@ void *nrmac_stats_thread(void *arg) {
p += print_meas_log(&gNB->schedule_dlsch, "dlsch scheduler", NULL, NULL, p, end - p); p += print_meas_log(&gNB->schedule_dlsch, "dlsch scheduler", NULL, NULL, p, end - p);
p += print_meas_log(&gNB->rlc_data_req, "rlc_data_req", NULL, NULL, p, end - p); p += print_meas_log(&gNB->rlc_data_req, "rlc_data_req", NULL, NULL, p, end - p);
p += print_meas_log(&gNB->rlc_status_ind, "rlc_status_ind", NULL, NULL, p, end - p); p += print_meas_log(&gNB->rlc_status_ind, "rlc_status_ind", NULL, NULL, p, end - p);
p += print_meas_log(&gNB->nr_srs_ri_computation_timer, "UL-RI computation time", NULL, NULL, p, end - p);
p += print_meas_log(&gNB->nr_srs_tpmi_computation_timer, "UL-TPMI computation time", NULL, NULL, p, end - p);
fwrite(output, p - output, 1, file); fwrite(output, p - output, 1, file);
fflush(file); fflush(file);
sleep(1); sleep(1);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 16e15b33
...@@ -806,6 +806,10 @@ typedef struct gNB_MAC_INST_s { ...@@ -806,6 +806,10 @@ typedef struct gNB_MAC_INST_s {
time_stats_t rlc_data_req; time_stats_t rlc_data_req;
/// processing time of rlc_status_ind /// processing time of rlc_status_ind
time_stats_t rlc_status_ind; time_stats_t rlc_status_ind;
/// processing time of nr_srs_ri_computation
time_stats_t nr_srs_ri_computation_timer;
/// processing time of nr_srs_tpmi_estimation
time_stats_t nr_srs_tpmi_computation_timer;
/// processing time of eNB MCH scheduler /// processing time of eNB MCH scheduler
time_stats_t schedule_mch; time_stats_t schedule_mch;
/// processing time of eNB ULSCH reception /// processing time of eNB ULSCH reception
......
targets/PROJECTS/GENERIC-NR-5GC/CONF/uecap_ports4.xml 0 → 100644
View file @ 16e15b33
<UE-NR-Capability>
<accessStratumRelease><rel15/></accessStratumRelease>
<pdcp-Parameters>
<supportedROHC-Profiles>
<profile0x0000><false/></profile0x0000>
<profile0x0001><false/></profile0x0001>
<profile0x0002><false/></profile0x0002>
<profile0x0003><false/></profile0x0003>
<profile0x0004><false/></profile0x0004>
<profile0x0006><false/></profile0x0006>
<profile0x0101><false/></profile0x0101>
<profile0x0102><false/></profile0x0102>
<profile0x0103><false/></profile0x0103>
<profile0x0104><false/></profile0x0104>
</supportedROHC-Profiles>
<maxNumberROHC-ContextSessions><cs2/></maxNumberROHC-ContextSessions>
<shortSN><supported/></shortSN>
</pdcp-Parameters>
<rlc-Parameters>
<am-WithShortSN><supported/></am-WithShortSN>
<um-WithShortSN><supported/></um-WithShortSN>
<um-WithLongSN><supported/></um-WithLongSN>
</rlc-Parameters>
<mac-Parameters>
<mac-ParametersXDD-Diff>
<logicalChannelSR-DelayTimer><supported/></logicalChannelSR-DelayTimer>
<longDRX-Cycle><supported/></longDRX-Cycle>
<shortDRX-Cycle><supported/></shortDRX-Cycle>
<multipleSR-Configurations><supported/></multipleSR-Configurations>
</mac-ParametersXDD-Diff>
</mac-Parameters>
<phy-Parameters>
<phy-ParametersCommon>
<nzp-CSI-RS-IntefMgmt><supported/></nzp-CSI-RS-IntefMgmt>
<dynamicHARQ-ACK-Codebook><supported/></dynamicHARQ-ACK-Codebook>
<semiStaticHARQ-ACK-Codebook><supported/></semiStaticHARQ-ACK-Codebook>
<pdsch-MappingTypeA><supported/></pdsch-MappingTypeA>
<rateMatchingResrcSetSemi-Static><supported/></rateMatchingResrcSetSemi-Static>
<ext2>
<maxLayersMIMO-Indication><supported/></maxLayersMIMO-Indication>
</ext2>
</phy-ParametersCommon>
<phy-ParametersFRX-Diff>
<twoFL-DMRS>
11
</twoFL-DMRS>
<supportedDMRS-TypeDL><type1/></supportedDMRS-TypeDL>
<supportedDMRS-TypeUL><type1And2/></supportedDMRS-TypeUL>
<onePortsPTRS>
01
</onePortsPTRS>
<pucch-F2-WithFH><supported/></pucch-F2-WithFH>
<pucch-F3-WithFH><supported/></pucch-F3-WithFH>
<absoluteTPC-Command><supported/></absoluteTPC-Command>
<pusch-HalfPi-BPSK><supported/></pusch-HalfPi-BPSK>
<pucch-F3-4-HalfPi-BPSK><supported/></pucch-F3-4-HalfPi-BPSK>
<ext1>
<csi-RS-IM-ReceptionForFeedback>
<maxConfigNumberNZP-CSI-RS-PerCC>8</maxConfigNumberNZP-CSI-RS-PerCC>
<maxConfigNumberPortsAcrossNZP-CSI-RS-PerCC>64</maxConfigNumberPortsAcrossNZP-CSI-RS-PerCC>
<maxConfigNumberCSI-IM-PerCC><n8/></maxConfigNumberCSI-IM-PerCC>
<maxNumberSimultaneousNZP-CSI-RS-PerCC>4</maxNumberSimultaneousNZP-CSI-RS-PerCC>
<totalNumberPortsSimultaneousNZP-CSI-RS-PerCC>32</totalNumberPortsSimultaneousNZP-CSI-RS-PerCC>
</csi-RS-IM-ReceptionForFeedback>
<csi-ReportFramework>
<maxNumberPeriodicCSI-PerBWP-ForCSI-Report>2</maxNumberPeriodicCSI-PerBWP-ForCSI-Report>
<maxNumberAperiodicCSI-PerBWP-ForCSI-Report>2</maxNumberAperiodicCSI-PerBWP-ForCSI-Report>
<maxNumberSemiPersistentCSI-PerBWP-ForCSI-Report>0</maxNumberSemiPersistentCSI-PerBWP-ForCSI-Report>
<maxNumberPeriodicCSI-PerBWP-ForBeamReport>2</maxNumberPeriodicCSI-PerBWP-ForBeamReport>
<maxNumberAperiodicCSI-PerBWP-ForBeamReport>2</maxNumberAperiodicCSI-PerBWP-ForBeamReport>
<maxNumberAperiodicCSI-triggeringStatePerCC><n63/></maxNumberAperiodicCSI-triggeringStatePerCC>
<maxNumberSemiPersistentCSI-PerBWP-ForBeamReport>0</maxNumberSemiPersistentCSI-PerBWP-ForBeamReport>
<simultaneousCSI-ReportsPerCC>4</simultaneousCSI-ReportsPerCC>
</csi-ReportFramework>
<mux-SR-HARQ-ACK-CSI-PUCCH-OncePerSlot>
<sameSymbol><supported/></sameSymbol>
</mux-SR-HARQ-ACK-CSI-PUCCH-OncePerSlot>
<oneFL-DMRS-TwoAdditionalDMRS-UL><supported/></oneFL-DMRS-TwoAdditionalDMRS-UL>
<twoFL-DMRS-TwoAdditionalDMRS-UL><supported/></twoFL-DMRS-TwoAdditionalDMRS-UL>
</ext1>
</phy-ParametersFRX-Diff>
<phy-ParametersFR1>
<pdsch-256QAM-FR1><supported/></pdsch-256QAM-FR1>
<pdsch-RE-MappingFR1-PerSymbol><n10/></pdsch-RE-MappingFR1-PerSymbol>
<ext1>
<pdsch-RE-MappingFR1-PerSlot><n32/></pdsch-RE-MappingFR1-PerSlot>
</ext1>
</phy-ParametersFR1>
</phy-Parameters>
<rf-Parameters>
<supportedBandListNR>
<BandNR>
<bandNR>78</bandNR>
<mimo-ParametersPerBand>
<tci-StatePDSCH>
<maxNumberConfiguredTCI-StatesPerCC><n16/></maxNumberConfiguredTCI-StatesPerCC>
<maxNumberActiveTCI-PerBWP><n1/></maxNumberActiveTCI-PerBWP>
</tci-StatePDSCH>
<pusch-TransCoherence><nonCoherent/></pusch-TransCoherence>
<periodicBeamReport><supported/></periodicBeamReport>
<aperiodicBeamReport><supported/></aperiodicBeamReport>
<maxNumberNonGroupBeamReporting><n4/></maxNumberNonGroupBeamReporting>
<maxNumberSSB-BFD>2</maxNumberSSB-BFD>
<maxNumberCSI-RS-SSB-CBD>8</maxNumberCSI-RS-SSB-CBD>
<beamReportTiming>
<scs-15kHz><sym8/></scs-15kHz>
<scs-30kHz><sym14/></scs-30kHz>
</beamReportTiming>
<ext1>
<beamManagementSSB-CSI-RS>
<maxNumberSSB-CSI-RS-ResourceOneTx><n8/></maxNumberSSB-CSI-RS-ResourceOneTx>
<maxNumberCSI-RS-Resource><n32/></maxNumberCSI-RS-Resource>
<maxNumberCSI-RS-ResourceTwoTx><n8/></maxNumberCSI-RS-ResourceTwoTx>
<supportedCSI-RS-Density><oneAndThree/></supportedCSI-RS-Density>
<maxNumberAperiodicCSI-RS-Resource><n32/></maxNumberAperiodicCSI-RS-Resource>
</beamManagementSSB-CSI-RS>
<codebookParameters>
<type1>
<singlePanel>
<supportedCSI-RS-ResourceList>
<SupportedCSI-RS-Resource>
<maxNumberTxPortsPerResource><p8/></maxNumberTxPortsPerResource>
<maxNumberResourcesPerBand>8</maxNumberResourcesPerBand>
<totalNumberTxPortsPerBand>64</totalNumberTxPortsPerBand>
</SupportedCSI-RS-Resource>
<SupportedCSI-RS-Resource>
<maxNumberTxPortsPerResource><p4/></maxNumberTxPortsPerResource>
<maxNumberResourcesPerBand>8</maxNumberResourcesPerBand>
<totalNumberTxPortsPerBand>32</totalNumberTxPortsPerBand>
</SupportedCSI-RS-Resource>
<SupportedCSI-RS-Resource>
<maxNumberTxPortsPerResource><p16/></maxNumberTxPortsPerResource>
<maxNumberResourcesPerBand>4</maxNumberResourcesPerBand>
<totalNumberTxPortsPerBand>64</totalNumberTxPortsPerBand>
</SupportedCSI-RS-Resource>
<SupportedCSI-RS-Resource>
<maxNumberTxPortsPerResource><p32/></maxNumberTxPortsPerResource>
<maxNumberResourcesPerBand>2</maxNumberResourcesPerBand>
<totalNumberTxPortsPerBand>64</totalNumberTxPortsPerBand>
</SupportedCSI-RS-Resource>
</supportedCSI-RS-ResourceList>
<modes><mode1/></modes>
<maxNumberCSI-RS-PerResourceSet>4</maxNumberCSI-RS-PerResourceSet>
</singlePanel>
</type1>
</codebookParameters>
<csi-RS-IM-ReceptionForFeedback>
<maxConfigNumberNZP-CSI-RS-PerCC>8</maxConfigNumberNZP-CSI-RS-PerCC>
<maxConfigNumberPortsAcrossNZP-CSI-RS-PerCC>64</maxConfigNumberPortsAcrossNZP-CSI-RS-PerCC>
<maxConfigNumberCSI-IM-PerCC><n8/></maxConfigNumberCSI-IM-PerCC>
<maxNumberSimultaneousNZP-CSI-RS-PerCC>4</maxNumberSimultaneousNZP-CSI-RS-PerCC>
<totalNumberPortsSimultaneousNZP-CSI-RS-PerCC>32</totalNumberPortsSimultaneousNZP-CSI-RS-PerCC>
</csi-RS-IM-ReceptionForFeedback>
<csi-ReportFramework>
<maxNumberPeriodicCSI-PerBWP-ForCSI-Report>2</maxNumberPeriodicCSI-PerBWP-ForCSI-Report>
<maxNumberAperiodicCSI-PerBWP-ForCSI-Report>2</maxNumberAperiodicCSI-PerBWP-ForCSI-Report>
<maxNumberSemiPersistentCSI-PerBWP-ForCSI-Report>0</maxNumberSemiPersistentCSI-PerBWP-ForCSI-Report>
<maxNumberPeriodicCSI-PerBWP-ForBeamReport>2</maxNumberPeriodicCSI-PerBWP-ForBeamReport>
<maxNumberAperiodicCSI-PerBWP-ForBeamReport>2</maxNumberAperiodicCSI-PerBWP-ForBeamReport>
<maxNumberAperiodicCSI-triggeringStatePerCC><n63/></maxNumberAperiodicCSI-triggeringStatePerCC>
<maxNumberSemiPersistentCSI-PerBWP-ForBeamReport>0</maxNumberSemiPersistentCSI-PerBWP-ForBeamReport>
<simultaneousCSI-ReportsPerCC>4</simultaneousCSI-ReportsPerCC>
</csi-ReportFramework>
<csi-RS-ForTracking>
<maxBurstLength>2</maxBurstLength>
<maxSimultaneousResourceSetsPerCC>1</maxSimultaneousResourceSetsPerCC>
<maxConfiguredResourceSetsPerCC>8</maxConfiguredResourceSetsPerCC>
<maxConfiguredResourceSetsAllCC>16</maxConfiguredResourceSetsAllCC>
</csi-RS-ForTracking>
</ext1>
</mimo-ParametersPerBand>
<multipleTCI><supported/></multipleTCI>
<pusch-256QAM><supported/></pusch-256QAM>
<ue-PowerClass><pc2/></ue-PowerClass>
<channelBWs-DL>
<fr1>
<scs-15kHz>
0000000000
</scs-15kHz>
<scs-30kHz>
0001011111
</scs-30kHz>
<scs-60kHz>
0000000000
</scs-60kHz>
</fr1>
</channelBWs-DL>
<channelBWs-UL>
<fr1>
<scs-15kHz>
0000000000
</scs-15kHz>
<scs-30kHz>
0001011111
</scs-30kHz>
<scs-60kHz>
0000000000
</scs-60kHz>
</fr1>
</channelBWs-UL>
<ext1>
<maxUplinkDutyCycle-PC2-FR1><n100/></maxUplinkDutyCycle-PC2-FR1>
</ext1>
<ext4>
<channelBWs-DL-v1590>
<fr1>
<scs-30kHz>
1000000000000000
</scs-30kHz>
</fr1>
</channelBWs-DL-v1590>
<channelBWs-UL-v1590>
<fr1>
<scs-30kHz>
1000000000000000
</scs-30kHz>
</fr1>
</channelBWs-UL-v1590>
</ext4>
</BandNR>
</supportedBandListNR>
<supportedBandCombinationList>
<BandCombination>
<bandList>
<nr>
<bandNR>78</bandNR>
<ca-BandwidthClassDL-NR><a/></ca-BandwidthClassDL-NR>
<ca-BandwidthClassUL-NR><a/></ca-BandwidthClassUL-NR>
</nr>
</bandList>
<featureSetCombination>0</featureSetCombination>
<powerClass-v1530><pc2/></powerClass-v1530>
</BandCombination>
</supportedBandCombinationList>
<appliedFreqBandListFilter>
<bandInformationNR>
<bandNR>78</bandNR>
</bandInformationNR>
</appliedFreqBandListFilter>
<ext1>
<supportedBandCombinationList-v1540>
<BandCombination-v1540>
<bandList-v1540>
<BandParameters-v1540>
<srs-TxSwitch>
<supportedSRS-TxPortSwitch><t2r4/></supportedSRS-TxPortSwitch>
</srs-TxSwitch>
</BandParameters-v1540>
</bandList-v1540>
<ca-ParametersNR-v1540>
<csi-RS-IM-ReceptionForFeedbackPerBandComb>
<maxNumberSimultaneousNZP-CSI-RS-ActBWP-AllCC>8</maxNumberSimultaneousNZP-CSI-RS-ActBWP-AllCC>
<totalNumberPortsSimultaneousNZP-CSI-RS-ActBWP-AllCC>64</totalNumberPortsSimultaneousNZP-CSI-RS-ActBWP-AllCC>
</csi-RS-IM-ReceptionForFeedbackPerBandComb>
<simultaneousCSI-ReportsAllCC>8</simultaneousCSI-ReportsAllCC>
</ca-ParametersNR-v1540>
</BandCombination-v1540>
</supportedBandCombinationList-v1540>
</ext1>
</rf-Parameters>
<measAndMobParameters>
<measAndMobParametersCommon>
<ssb-RLM><supported/></ssb-RLM>
<ext1>
<eventB-MeasAndReport><supported/></eventB-MeasAndReport>
<handoverFDD-TDD><supported/></handoverFDD-TDD>
</ext1>
<ext2>
<periodicEUTRA-MeasAndReport><supported/></periodicEUTRA-MeasAndReport>
</ext2>
</measAndMobParametersCommon>
<measAndMobParametersXDD-Diff>
<intraAndInterF-MeasAndReport><supported/></intraAndInterF-MeasAndReport>
<eventA-MeasAndReport><supported/></eventA-MeasAndReport>
<ext1>
<handoverInterF><supported/></handoverInterF>
<handoverLTE-EPC><supported/></handoverLTE-EPC>
</ext1>
</measAndMobParametersXDD-Diff>
<measAndMobParametersFRX-Diff>
<ss-SINR-Meas><supported/></ss-SINR-Meas>
<ext1>
<handoverInterF><supported/></handoverInterF>
<handoverLTE-EPC><supported/></handoverLTE-EPC>
</ext1>
<ext3>
<simultaneousRxDataSSB-DiffNumerology><supported/></simultaneousRxDataSSB-DiffNumerology>
</ext3>
</measAndMobParametersFRX-Diff>
</measAndMobParameters>
<featureSets>
<featureSetsDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>1</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>2</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>3</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>4</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
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</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>5</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>6</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>7</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>8</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>9</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>10</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>11</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
<FeatureSetDownlink>
<featureSetListPerDownlinkCC>
<FeatureSetDownlinkPerCC-Id>12</FeatureSetDownlinkPerCC-Id>
</featureSetListPerDownlinkCC>
<ue-SpecificUL-DL-Assignment><supported/></ue-SpecificUL-DL-Assignment>
</FeatureSetDownlink>
</featureSetsDownlink>
<featureSetsDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz100/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz100/></fr1>
</supportedBandwidthDL>
<channelBW-90mhz><supported/></channelBW-90mhz>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz20/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><twoLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz40/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz40/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz80/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz20/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz30/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><twoLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz20/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz15/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><twoLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz15/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz30/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
<FeatureSetDownlinkPerCC>
<supportedSubcarrierSpacingDL><kHz30/></supportedSubcarrierSpacingDL>
<supportedBandwidthDL>
<fr1><mhz60/></fr1>
</supportedBandwidthDL>
<maxNumberMIMO-LayersPDSCH><fourLayers/></maxNumberMIMO-LayersPDSCH>
<supportedModulationOrderDL><qam256/></supportedModulationOrderDL>
</FeatureSetDownlinkPerCC>
</featureSetsDownlinkPerCC>
<featureSetsUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>1</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
<supportedSRS-Resources>
<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n4/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>2</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n4/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>3</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>4</FeatureSetUplinkPerCC-Id>
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<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
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<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>5</FeatureSetUplinkPerCC-Id>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>6</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>7</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>8</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
<maxNumberSemiPersistentSRS-PerBWP><n2/></maxNumberSemiPersistentSRS-PerBWP>
<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>9</FeatureSetUplinkPerCC-Id>
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<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>10</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
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<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>11</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>12</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n16/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
<FeatureSetUplink>
<featureSetListPerUplinkCC>
<FeatureSetUplinkPerCC-Id>11</FeatureSetUplinkPerCC-Id>
</featureSetListPerUplinkCC>
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<maxNumberAperiodicSRS-PerBWP><n1/></maxNumberAperiodicSRS-PerBWP>
<maxNumberAperiodicSRS-PerBWP-PerSlot>6</maxNumberAperiodicSRS-PerBWP-PerSlot>
<maxNumberPeriodicSRS-PerBWP><n16/></maxNumberPeriodicSRS-PerBWP>
<maxNumberPeriodicSRS-PerBWP-PerSlot>6</maxNumberPeriodicSRS-PerBWP-PerSlot>
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<maxNumberSemiPersistentSRS-PerBWP-PerSlot>2</maxNumberSemiPersistentSRS-PerBWP-PerSlot>
<maxNumberSRS-Ports-PerResource><n1/></maxNumberSRS-Ports-PerResource>
</supportedSRS-Resources>
</FeatureSetUplink>
</featureSetsUplink>
<featureSetsUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz100/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><fourLayers/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz100/></fr1>
</supportedBandwidthUL>
<channelBW-90mhz><supported/></channelBW-90mhz>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><fourLayers/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz15/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz20/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz15/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz40/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
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<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz40/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz80/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz20/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz15/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz30/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz15/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz15/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz100/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz100/></fr1>
</supportedBandwidthUL>
<channelBW-90mhz><supported/></channelBW-90mhz>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
<FeatureSetUplinkPerCC>
<supportedSubcarrierSpacingUL><kHz30/></supportedSubcarrierSpacingUL>
<supportedBandwidthUL>
<fr1><mhz60/></fr1>
</supportedBandwidthUL>
<mimo-CB-PUSCH>
<maxNumberMIMO-LayersCB-PUSCH><oneLayer/></maxNumberMIMO-LayersCB-PUSCH>
<maxNumberSRS-ResourcePerSet>1</maxNumberSRS-ResourcePerSet>
</mimo-CB-PUSCH>
<supportedModulationOrderUL><qam256/></supportedModulationOrderUL>
</FeatureSetUplinkPerCC>
</featureSetsUplinkPerCC>
<ext1>
<featureSetsDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
<FeatureSetDownlink-v1540>
<oneFL-DMRS-TwoAdditionalDMRS-DL><supported/></oneFL-DMRS-TwoAdditionalDMRS-DL>
<twoFL-DMRS-TwoAdditionalDMRS-DL><supported/></twoFL-DMRS-TwoAdditionalDMRS-DL>
</FeatureSetDownlink-v1540>
</featureSetsDownlink-v1540>
</ext1>
</featureSets>
<featureSetCombinations>
<FeatureSetCombination>
<FeatureSetsPerBand>
<nr>
<downlinkSetNR>2</downlinkSetNR>
<uplinkSetNR>2</uplinkSetNR>
</nr>
</FeatureSetsPerBand>
</FeatureSetCombination>
</featureSetCombinations>
<nonCriticalExtension>
<interRAT-Parameters>
<eutra>
<supportedBandListEUTRA>
<FreqBandIndicatorEUTRA>7</FreqBandIndicatorEUTRA>
<FreqBandIndicatorEUTRA>38</FreqBandIndicatorEUTRA>
</supportedBandListEUTRA>
<eutra-ParametersCommon>
<mfbi-EUTRA><supported/></mfbi-EUTRA>
</eutra-ParametersCommon>
</eutra>
</interRAT-Parameters>
<inactiveState><supported/></inactiveState>
</nonCriticalExtension>
</UE-NR-Capability>
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