Commit 331fb1ce authored by Robert Schmidt's avatar Robert Schmidt

Merge remote-tracking branch 'origin/better-dci-decoding' into integration_2024_w09

parents 64e58c1d 56c4a6ec
...@@ -497,6 +497,8 @@ int logInit (void) ...@@ -497,6 +497,8 @@ int logInit (void)
register_log_component("GNB_APP","log",GNB_APP); register_log_component("GNB_APP","log",GNB_APP);
register_log_component("NR_RRC","log",NR_RRC); register_log_component("NR_RRC","log",NR_RRC);
register_log_component("NR_MAC","log",NR_MAC); register_log_component("NR_MAC","log",NR_MAC);
register_log_component("NR_MAC_DCI", "log", NR_MAC_DCI);
register_log_component("NR_PHY_DCI", "log", NR_PHY_DCI);
register_log_component("NR_PHY","log",NR_PHY); register_log_component("NR_PHY","log",NR_PHY);
register_log_component("NGAP","",NGAP); register_log_component("NGAP","",NGAP);
register_log_component("ITTI","log",ITTI); register_log_component("ITTI","log",ITTI);
......
...@@ -215,6 +215,8 @@ typedef enum { ...@@ -215,6 +215,8 @@ typedef enum {
GNB_APP, GNB_APP,
NR_RRC, NR_RRC,
NR_MAC, NR_MAC,
NR_MAC_DCI,
NR_PHY_DCI,
NR_PHY, NR_PHY,
LOADER, LOADER,
ASN1, ASN1,
...@@ -223,8 +225,7 @@ typedef enum { ...@@ -223,8 +225,7 @@ typedef enum {
ITTI, ITTI,
UTIL, UTIL,
MAX_LOG_PREDEF_COMPONENTS, MAX_LOG_PREDEF_COMPONENTS,
} } comp_name_t;
comp_name_t;
#define MAX_LOG_DYNALLOC_COMPONENTS 20 #define MAX_LOG_DYNALLOC_COMPONENTS 20
#define MAX_LOG_COMPONENTS (MAX_LOG_PREDEF_COMPONENTS + MAX_LOG_DYNALLOC_COMPONENTS) #define MAX_LOG_COMPONENTS (MAX_LOG_PREDEF_COMPONENTS + MAX_LOG_DYNALLOC_COMPONENTS)
...@@ -247,7 +248,7 @@ typedef struct { ...@@ -247,7 +248,7 @@ typedef struct {
log_vprint_func_t vprint; log_vprint_func_t vprint;
log_print_func_t print; log_print_func_t print;
/* SR: make the log buffer component relative */ /* SR: make the log buffer component relative */
char log_buffer[MAX_LOG_TOTAL]; // char log_buffer[MAX_LOG_TOTAL];
} log_component_t; } log_component_t;
......
...@@ -361,6 +361,48 @@ ID = LEGACY_NR_MAC_TRACE ...@@ -361,6 +361,48 @@ ID = LEGACY_NR_MAC_TRACE
GROUP = ALL:LEGACY_NR_MAC:LEGACY_GROUP_TRACE:LEGACY GROUP = ALL:LEGACY_NR_MAC:LEGACY_GROUP_TRACE:LEGACY
FORMAT = string,log FORMAT = string,log
ID = LEGACY_NR_PHY_DCI_INFO
DESC = NR_PHY_DCI legacy logs - info level
GROUP = ALL:LEGACY_NR_PHY_DCI:LEGACY_GROUP_INFO:LEGACY
FORMAT = string,log
ID = LEGACY_NR_PHY_DCI_ERROR
DESC = NR_PHY_DCI legacy logs - error level
GROUP = ALL:LEGACY_NR_PHY_DCI:LEGACY_GROUP_ERROR:LEGACY
FORMAT = string,log
ID = LEGACY_NR_PHY_DCI_WARNING
DESC = NR_PHY_DCI legacy logs - warning level
GROUP = ALL:LEGACY_NR_PHY_DCI:LEGACY_GROUP_WARNING:LEGACY
FORMAT = string,log
ID = LEGACY_NR_PHY_DCI_DEBUG
DESC = NR_PHY_DCI legacy logs - debug level
GROUP = ALL:LEGACY_NR_PHY_DCI:LEGACY_GROUP_DEBUG:LEGACY
FORMAT = string,log
ID = LEGACY_NR_PHY_DCI_TRACE
DESC = NR_PHY_DCI legacy logs - trace level
GROUP = ALL:LEGACY_NR_PHY_DCI:LEGACY_GROUP_TRACE:LEGACY
FORMAT = string,log
ID = LEGACY_NR_MAC_DCI_INFO
DESC = NR_MAC_DCI legacy logs - info level
GROUP = ALL:LEGACY_NR_MAC_DCI:LEGACY_GROUP_INFO:LEGACY
FORMAT = string,log
ID = LEGACY_NR_MAC_DCI_ERROR
DESC = NR_MAC_DCI legacy logs - error level
GROUP = ALL:LEGACY_NR_MAC_DCI:LEGACY_GROUP_ERROR:LEGACY
FORMAT = string,log
ID = LEGACY_NR_MAC_DCI_WARNING
DESC = NR_MAC_DCI legacy logs - warning level
GROUP = ALL:LEGACY_NR_MAC_DCI:LEGACY_GROUP_WARNING:LEGACY
FORMAT = string,log
ID = LEGACY_NR_MAC_DCI_DEBUG
DESC = NR_MAC_DCI legacy logs - debug level
GROUP = ALL:LEGACY_NR_MAC_DCI:LEGACY_GROUP_DEBUG:LEGACY
FORMAT = string,log
ID = LEGACY_NR_MAC_DCI_TRACE
DESC = NR_MAC_DCI legacy logs - trace level
GROUP = ALL:LEGACY_NR_MAC_DCI:LEGACY_GROUP_TRACE:LEGACY
FORMAT = string,log
ID = LEGACY_PHY_INFO ID = LEGACY_PHY_INFO
DESC = PHY legacy logs - info level DESC = PHY legacy logs - info level
GROUP = ALL:LEGACY_PHY:LEGACY_GROUP_INFO:LEGACY GROUP = ALL:LEGACY_PHY:LEGACY_GROUP_INFO:LEGACY
......
...@@ -50,7 +50,7 @@ void nr_pdcch_scrambling(uint32_t *in, ...@@ -50,7 +50,7 @@ void nr_pdcch_scrambling(uint32_t *in,
uint32_t x1 = 0, x2 = 0, s = 0; uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1; reset = 1;
x2 = (scrambling_RNTI<<16) + Nid; x2 = (scrambling_RNTI<<16) + Nid;
LOG_D(PHY,"PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI); LOG_D(NR_PHY_DCI, "PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI);
for (int i=0; i<size; i++) { for (int i=0; i<size; i++) {
if ((i&0x1f)==0) { if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset); s = lte_gold_generic(&x1, &x2, reset);
...@@ -105,15 +105,28 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -105,15 +105,28 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex; cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex;
cset_nsymb = pdcch_pdu_rel15->DurationSymbols; cset_nsymb = pdcch_pdu_rel15->DurationSymbols;
dci_idx = 0; dci_idx = 0;
LOG_D(PHY, "pdcch: Coreset rb_offset %d, nb_rb %d BWP Start %d\n",rb_offset,n_rb,pdcch_pdu_rel15->BWPStart); LOG_D(NR_PHY_DCI, "pdcch: Coreset rb_offset %d, nb_rb %d BWP Start %d\n", rb_offset, n_rb, pdcch_pdu_rel15->BWPStart);
LOG_D(PHY, "pdcch: Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb); LOG_D(NR_PHY_DCI,
"pdcch: Coreset starting subcarrier %d on symbol %d (%d symbols)\n",
cset_start_sc,
cset_start_symb,
cset_nsymb);
// DMRS length is per OFDM symbol // DMRS length is per OFDM symbol
uint32_t dmrs_length = (n_rb+pdcch_pdu_rel15->BWPStart)*6; //2(QPSK)*3(per RB)*6(REG per CCE) uint32_t dmrs_length = (n_rb+pdcch_pdu_rel15->BWPStart)*6; //2(QPSK)*3(per RB)*6(REG per CCE)
uint32_t encoded_length = dci_pdu->AggregationLevel*108; //2(QPSK)*9(per RB)*6(REG per CCE) uint32_t encoded_length = dci_pdu->AggregationLevel*108; //2(QPSK)*9(per RB)*6(REG per CCE)
if (dci_pdu->RNTI != 0xFFFF) if (dci_pdu->RNTI != 0xFFFF)
LOG_D(PHY, "DL_DCI : rb_offset %d, nb_rb %d, DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d, reg_mapping %d), Scrambling_Id %d, ScramblingRNTI %x, PayloadSizeBits %d\n", LOG_D(NR_PHY_DCI,
rb_offset, n_rb,dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType, "DL_DCI : rb_offset %d, nb_rb %d, DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d, "
dci_pdu->ScramblingId,dci_pdu->ScramblingRNTI,dci_pdu->PayloadSizeBits); "reg_mapping %d), Scrambling_Id %d, ScramblingRNTI %x, PayloadSizeBits %d\n",
rb_offset,
n_rb,
dmrs_length,
encoded_length,
pdcch_pdu_rel15->precoderGranularity,
pdcch_pdu_rel15->CceRegMappingType,
dci_pdu->ScramblingId,
dci_pdu->ScramblingRNTI,
dci_pdu->PayloadSizeBits);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
/// DMRS QPSK modulation /// DMRS QPSK modulation
...@@ -182,7 +195,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -182,7 +195,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
// allocating rbs per symbol // allocating rbs per symbol
for (int reg_count = 0; reg_count < num_regs; reg_count++) { for (int reg_count = 0; reg_count < num_regs; reg_count++) {
k = cset_start_sc + reg_list[d][reg_count] * NR_NB_SC_PER_RB; k = cset_start_sc + reg_list[d][reg_count] * NR_NB_SC_PER_RB;
LOG_D(PHY, "REG %d k %d\n", reg_list[d][reg_count], k); LOG_D(NR_PHY_DCI, "REG %d k %d\n", reg_list[d][reg_count], k);
if (k >= frame_parms->ofdm_symbol_size) if (k >= frame_parms->ofdm_symbol_size)
k -= frame_parms->ofdm_symbol_size; k -= frame_parms->ofdm_symbol_size;
...@@ -202,7 +215,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -202,7 +215,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
((int16_t *)txdataF)[((l * frame_parms->ofdm_symbol_size + k) << 1) + 1] = (amp * mod_dmrs[l][(dmrs_idx << 1) + 1]) >> 15; ((int16_t *)txdataF)[((l * frame_parms->ofdm_symbol_size + k) << 1) + 1] = (amp * mod_dmrs[l][(dmrs_idx << 1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS #ifdef DEBUG_PDCCH_DMRS
LOG_I(PHY, LOG_I(NR_PHY_DCI,
"PDCCH DMRS %d: l %d position %d => (%d,%d)\n", "PDCCH DMRS %d: l %d position %d => (%d,%d)\n",
dmrs_idx, dmrs_idx,
l, l,
...@@ -218,7 +231,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -218,7 +231,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
((int16_t *)txdataF)[(l * frame_parms->ofdm_symbol_size + k) << 1] = (amp * mod_dci[dci_idx << 1]) >> 15; ((int16_t *)txdataF)[(l * frame_parms->ofdm_symbol_size + k) << 1] = (amp * mod_dci[dci_idx << 1]) >> 15;
((int16_t *)txdataF)[((l * frame_parms->ofdm_symbol_size + k) << 1) + 1] = (amp * mod_dci[(dci_idx << 1) + 1]) >> 15; ((int16_t *)txdataF)[((l * frame_parms->ofdm_symbol_size + k) << 1) + 1] = (amp * mod_dci[(dci_idx << 1) + 1]) >> 15;
#ifdef DEBUG_DCI #ifdef DEBUG_DCI
LOG_I(PHY, LOG_I(NR_PHY_DCI,
"PDCCH: l %d position %d => (%d,%d)\n", "PDCCH: l %d position %d => (%d,%d)\n",
l, l,
k, k,
...@@ -237,7 +250,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -237,7 +250,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
} // reg_count } // reg_count
} // symbol_idx } // symbol_idx
LOG_D(PHY, LOG_D(NR_PHY_DCI,
"DCI: payloadSize = %d | payload = %llx\n", "DCI: payloadSize = %d | payload = %llx\n",
dci_pdu->PayloadSizeBits, dci_pdu->PayloadSizeBits,
*(unsigned long long *)dci_pdu->Payload); *(unsigned long long *)dci_pdu->Payload);
......
...@@ -73,21 +73,30 @@ void nr_fill_reg_list(int reg_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL * NR_ ...@@ -73,21 +73,30 @@ void nr_fill_reg_list(int reg_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL * NR_
} }
if (pdcch_pdu_rel15->dci_pdu[d].RNTI != 0xFFFF) if (pdcch_pdu_rel15->dci_pdu[d].RNTI != 0xFFFF)
LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", d, bsize, R, pdcch_pdu_rel15->dci_pdu[d].CceIndex); LOG_D(NR_PHY_DCI,
"CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n",
d,
bsize,
R,
pdcch_pdu_rel15->dci_pdu[d].CceIndex);
int list_idx = 0; int list_idx = 0;
for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) { for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
int cce = pdcch_pdu_rel15->dci_pdu[d].CceIndex + cce_idx; int cce = pdcch_pdu_rel15->dci_pdu[d].CceIndex + cce_idx;
LOG_D(PHY, "cce_idx %d\n", cce); LOG_D(NR_PHY_DCI, "cce_idx %d\n", cce);
for (uint8_t bundle_idx=0; bundle_idx<NR_NB_REG_PER_CCE/bsize; bundle_idx++) { for (uint8_t bundle_idx=0; bundle_idx<NR_NB_REG_PER_CCE/bsize; bundle_idx++) {
uint8_t k = 6 * cce / bsize + bundle_idx; uint8_t k = 6 * cce / bsize + bundle_idx;
int f = cce_to_reg_interleaving(R, k, n_shift, C, bsize, N_regs); int f = cce_to_reg_interleaving(R, k, n_shift, C, bsize, N_regs);
LOG_D(PHY, "Bundle index %d: f(%d) = %d\n", bundle_idx, k, f); LOG_D(NR_PHY_DCI, "Bundle index %d: f(%d) = %d\n", bundle_idx, k, f);
// reg_list contains the regs to be allocated per symbol // reg_list contains the regs to be allocated per symbol
// the same rbs are allocated in each symbol // the same rbs are allocated in each symbol
for (uint8_t reg_idx = 0; reg_idx < bsize / dur; reg_idx++) { for (uint8_t reg_idx = 0; reg_idx < bsize / dur; reg_idx++) {
reg_list[d][list_idx] = f * bsize / dur + reg_idx; reg_list[d][list_idx] = f * bsize / dur + reg_idx;
LOG_D(PHY, "rb %d nb of symbols per rb %d start subcarrier %d\n", reg_list[d][list_idx], dur, reg_list[d][list_idx] * NR_NB_SC_PER_RB); LOG_D(NR_PHY_DCI,
"rb %d nb of symbols per rb %d start subcarrier %d\n",
reg_list[d][list_idx],
dur,
reg_list[d][list_idx] * NR_NB_SC_PER_RB);
list_idx++; list_idx++;
} }
} }
......
...@@ -1060,7 +1060,7 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -1060,7 +1060,7 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
uint16_t first_carrier_offset, uint16_t first_carrier_offset,
uint16_t BWPStart, uint16_t BWPStart,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]) c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
{ {
......
...@@ -54,7 +54,7 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -54,7 +54,7 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
uint16_t first_carrier_offset, uint16_t first_carrier_offset,
uint16_t BWPStart, uint16_t BWPStart,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]); c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]);
int nr_pbch_dmrs_correlation(PHY_VARS_NR_UE *ue, int nr_pbch_dmrs_correlation(PHY_VARS_NR_UE *ue,
......
...@@ -57,25 +57,31 @@ static const char nr_dci_format_string[8][30] = {"NR_DL_DCI_FORMAT_1_0", ...@@ -57,25 +57,31 @@ static const char nr_dci_format_string[8][30] = {"NR_DL_DCI_FORMAT_1_0",
//#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs //#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs
#ifdef NR_PDCCH_DCI_DEBUG #ifdef NR_PDCCH_DCI_DEBUG
#define LOG_DDD(a, ...) printf("<-NR_PDCCH_DCI_DEBUG (%s)-> " a, __func__, ##__VA_ARGS__ ) #define LOG_DDD(a, ...) printf("<-NR_PDCCH_DCI_DEBUG (%s)-> " a, __func__, ##__VA_ARGS__ )
#define LOG_DSYMB(b) \
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n" b, \
c_rb, \
i, \
j, \
rxF_ext[j].r, \
rxF_ext[j].i, \
i, \
rxF[i].r, \
rxF[i].i)
#else #else
#define LOG_DDD(a...) #define LOG_DDD(a...)
#define LOG_DSYMB(a...)
#endif #endif
#define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0) #define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0)
#define NR_NBR_SEARCHSPACE_ACT_BWP 10 // The number of SearSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0) #define NR_NBR_SEARCHSPACE_ACT_BWP \
10 // The number of SearSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0)
#ifdef LOG_I #ifdef LOG_I
#undef LOG_I #undef LOG_I
#define LOG_I(A,B...) printf(B) #define LOG_I(A, B...) printf(B)
#endif #endif
static void nr_pdcch_demapping_deinterleaving(c16_t *llr,
c16_t *e_rx,
//static const int16_t conjugate[8]__attribute__((aligned(32))) = {-1,1,-1,1,-1,1,-1,1};
static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
uint32_t *e_rx,
uint8_t coreset_time_dur, uint8_t coreset_time_dur,
uint8_t start_symbol, uint8_t start_symbol,
uint32_t coreset_nbr_rb, uint32_t coreset_nbr_rb,
...@@ -91,7 +97,8 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -91,7 +97,8 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
* Demapping will regroup in REG and bundles * Demapping will regroup in REG and bundles
* Deinterleaving will order the bundles * Deinterleaving will order the bundles
* *
* In the following example we can see the process. The llr contains the demodulated IQs, but they are not ordered from REG 0,1,2,.. * In the following example we can see the process. The llr contains the demodulated IQs, but they are not ordered from
REG 0,1,2,..
* In e_rx (z) we will order the REG ids and group them into bundles. * In e_rx (z) we will order the REG ids and group them into bundles.
* Then we will put the bundles in the correct order as indicated in subclause 7.3.2.2 * Then we will put the bundles in the correct order as indicated in subclause 7.3.2.2
* *
...@@ -121,16 +128,14 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -121,16 +128,14 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
| REG 0 (bundle 0) bundle 0 bundle 0 | REG 0 (bundle 0) bundle 0 bundle 0
*/ */
int c = 0, r = 0;
uint16_t f_bundle_j = 0;
uint32_t coreset_C = 0; uint32_t coreset_C = 0;
uint16_t index_z, index_llr;
int coreset_interleaved = 0; int coreset_interleaved = 0;
int N_regs = coreset_nbr_rb * coreset_time_dur; const int N_regs = coreset_nbr_rb * coreset_time_dur;
if (reg_bundle_size_L != 0) { // interleaving will be done only if reg_bundle_size_L != 0 if (reg_bundle_size_L != 0) { // interleaving will be done only if reg_bundle_size_L != 0
coreset_interleaved = 1; coreset_interleaved = 1;
coreset_C = (uint32_t) (N_regs / (coreset_interleaver_size_R * reg_bundle_size_L)); coreset_C = (uint32_t)(N_regs / (coreset_interleaver_size_R * reg_bundle_size_L));
} else { } else {
reg_bundle_size_L = 6; reg_bundle_size_L = 6;
} }
...@@ -141,6 +146,7 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -141,6 +146,7 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
int max_bundles = n_cce * num_bundles_per_cce; int max_bundles = n_cce * num_bundles_per_cce;
int f_bundle_j_list[max_bundles]; int f_bundle_j_list[max_bundles];
// for each bundle // for each bundle
int c = 0, r = 0, f_bundle_j = 0;
for (int nb = 0; nb < max_bundles; nb++) { for (int nb = 0; nb < max_bundles; nb++) {
if (coreset_interleaved == 0) if (coreset_interleaved == 0)
f_bundle_j = nb; f_bundle_j = nb;
...@@ -157,16 +163,15 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -157,16 +163,15 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
// Get cce_list indices by bundle index in ascending order // Get cce_list indices by bundle index in ascending order
int f_bundle_j_list_ord[number_of_candidates][max_bundles]; int f_bundle_j_list_ord[number_of_candidates][max_bundles];
for (int c_id = 0; c_id < number_of_candidates; c_id++ ) { for (int c_id = 0; c_id < number_of_candidates; c_id++) {
int start_bund_cand = CCE[c_id] * num_bundles_per_cce; int start_bund_cand = CCE[c_id] * num_bundles_per_cce;
int max_bund_per_cand = L[c_id] * num_bundles_per_cce; int max_bund_per_cand = L[c_id] * num_bundles_per_cce;
int f_bundle_j_list_id = 0; int f_bundle_j_list_id = 0;
for(int nb = 0; nb < max_bundles; nb++) { for (int nb = 0; nb < max_bundles; nb++) {
for(int bund_cand = start_bund_cand; bund_cand < start_bund_cand + max_bund_per_cand; bund_cand++){ for (int bund_cand = start_bund_cand; bund_cand < start_bund_cand + max_bund_per_cand; bund_cand++) {
if (f_bundle_j_list[bund_cand] == nb) { if (f_bundle_j_list[bund_cand] == nb) {
f_bundle_j_list_ord[c_id][f_bundle_j_list_id] = nb; f_bundle_j_list_ord[c_id][f_bundle_j_list_id] = nb;
f_bundle_j_list_id++; f_bundle_j_list_id++;
} }
} }
} }
...@@ -174,20 +179,30 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -174,20 +179,30 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
int rb_count = 0; int rb_count = 0;
int data_sc = 9; // 9 sub-carriers with data per PRB int data_sc = 9; // 9 sub-carriers with data per PRB
for (int c_id = 0; c_id < number_of_candidates; c_id++ ) { for (int c_id = 0; c_id < number_of_candidates; c_id++) {
for (int symbol_idx = start_symbol; symbol_idx < start_symbol+coreset_time_dur; symbol_idx++) { for (int symbol_idx = start_symbol; symbol_idx < start_symbol + coreset_time_dur; symbol_idx++) {
for (int cce_count = 0; cce_count < L[c_id]; cce_count ++) { for (int cce_count = 0; cce_count < L[c_id]; cce_count++) {
for (int k=0; k<NR_NB_REG_PER_CCE/reg_bundle_size_L; k++) { // loop over REG bundles for (int k = 0; k < NR_NB_REG_PER_CCE / reg_bundle_size_L; k++) { // loop over REG bundles
int f = f_bundle_j_list_ord[c_id][k+NR_NB_REG_PER_CCE*cce_count/reg_bundle_size_L]; int f = f_bundle_j_list_ord[c_id][k + NR_NB_REG_PER_CCE * cce_count / reg_bundle_size_L];
for(int rb=0; rb<B_rb; rb++) { // loop over the RBs of the bundle for (int rb = 0; rb < B_rb; rb++) { // loop over the RBs of the bundle
index_z = data_sc * rb_count; c16_t *out = e_rx + data_sc * rb_count;
index_llr = (uint16_t) (f*B_rb + rb + symbol_idx * coreset_nbr_rb) * data_sc; c16_t *in = llr + (uint16_t)(f * B_rb + rb + symbol_idx * coreset_nbr_rb) * data_sc;
for (int i = 0; i < data_sc; i++) { for (int i = 0; i < data_sc; i++) {
e_rx[index_z + i] = llr[index_llr + i]; out[i] = in[i];
#ifdef NR_PDCCH_DCI_DEBUG #ifdef NR_PDCCH_DCI_DEBUG
LOG_I(PHY,"[candidate=%d,symbol_idx=%d,cce=%d,REG bundle=%d,PRB=%d] z[%d]=(%d,%d) <-> \t llr[%d]=(%d,%d) \n", LOG_I(NR_PHY_DCI,
c_id,symbol_idx,cce_count,k,f*B_rb + rb,(index_z + i),*(int16_t *) &e_rx[index_z + i],*(1 + (int16_t *) &e_rx[index_z + i]), "[candidate=%d,symbol_idx=%d,cce=%d,REG bundle=%d,PRB=%d] z[%d]=(%d,%d) <-> \t llr[%d]=(%d,%d) \n",
(index_llr + i),*(int16_t *) &llr[index_llr + i], *(1 + (int16_t *) &llr[index_llr + i])); c_id,
symbol_idx,
cce_count,
k,
f * B_rb + rb,
(index_z + i),
out->r,
out->i,
index_llr + i,
in.r,
in.i);
#endif #endif
} }
rb_count++; rb_count++;
...@@ -198,92 +213,51 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -198,92 +213,51 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
} }
} }
int32_t nr_pdcch_llr(NR_DL_FRAME_PARMS *frame_parms, int32_t rx_size, int32_t rxdataF_comp[][rx_size], static void nr_pdcch_llr(NR_DL_FRAME_PARMS *frame_parms,
int16_t *pdcch_llr, uint8_t symbol,uint32_t coreset_nbr_rb) { int32_t rx_size,
int16_t *rxF = (int16_t *) &rxdataF_comp[0][(symbol * coreset_nbr_rb * 12)]; c16_t rxdataF_comp[][rx_size],
int32_t i; c16_t *pdcch_llr,
int16_t *pdcch_llrp; uint8_t symbol,
pdcch_llrp = &pdcch_llr[2 * symbol * coreset_nbr_rb * 9]; uint32_t coreset_nbr_rb)
{
c16_t *rxF = &rxdataF_comp[0][(symbol * coreset_nbr_rb * 12)];
c16_t *pdcch_llrp = &pdcch_llr[symbol * coreset_nbr_rb * 9];
if (!pdcch_llrp) { if (!pdcch_llrp) {
LOG_E(PHY,"pdcch_qpsk_llr: llr is null, symbol %d\n", symbol); LOG_E(NR_PHY_DCI, "pdcch_qpsk_llr: llr is null, symbol %d\n", symbol);
return (-1); return;
} }
LOG_DDD("llr logs: pdcch qpsk llr for symbol %d (pos %d), llr offset %ld\n",symbol,(symbol*frame_parms->N_RB_DL*12),pdcch_llrp-pdcch_llr); LOG_DDD("llr logs: pdcch qpsk llr for symbol %d (pos %d), llr offset %ld\n",symbol,(symbol*frame_parms->N_RB_DL*12),pdcch_llrp-pdcch_llr);
//for (i = 0; i < (frame_parms->N_RB_DL * ((symbol == 0) ? 16 : 24)); i++) { for (int i = 0; i < coreset_nbr_rb * 9; i++) {
for (i = 0; i < (coreset_nbr_rb * ((symbol == 0) ? 18 : 18)); i++) { // We clip the signal
if (*rxF > 31) c16_t res;
*pdcch_llrp = 31; res.r = min(rxF->r, 31);
else if (*rxF < -32) res.r = max(-32, res.r);
*pdcch_llrp = -32; res.i = min(rxF->i, 31);
else res.i = max(-32, res.i);
*pdcch_llrp = (*rxF); *pdcch_llrp = res;
LOG_DDD("llr logs: rb=%d i=%d *rxF:%d => *pdcch_llrp:%d\n",i/18,i,*rxF,*pdcch_llrp); LOG_DDD("llr logs: rb=%d i=%d *rxF:%d => *pdcch_llrp:%d\n",i/18,i,*rxF,*pdcch_llrp);
rxF++; rxF++;
pdcch_llrp++; pdcch_llrp++;
} }
return (0);
} }
#if 0
int32_t pdcch_llr(NR_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
char *pdcch_llr,
uint8_t symbol) {
int16_t *rxF= (int16_t *) &rxdataF_comp[0][(symbol*frame_parms->N_RB_DL*12)];
int32_t i;
char *pdcch_llr8;
pdcch_llr8 = &pdcch_llr[2*symbol*frame_parms->N_RB_DL*12];
if (!pdcch_llr8) {
LOG_E(PHY,"pdcch_qpsk_llr: llr is null, symbol %d\n",symbol);
return(-1);
}
// printf("pdcch qpsk llr for symbol %d (pos %d), llr offset %d\n",symbol,(symbol*frame_parms->N_RB_DL*12),pdcch_llr8-pdcch_llr);
for (i=0; i<(frame_parms->N_RB_DL*((symbol==0) ? 16 : 24)); i++) {
if (*rxF>31)
*pdcch_llr8=31;
else if (*rxF<-32)
*pdcch_llr8=-32;
else
*pdcch_llr8 = (char)(*rxF);
// printf("%d %d => %d\n",i,*rxF,*pdcch_llr8);
rxF++;
pdcch_llr8++;
}
return(0);
}
#endif
//__m128i avg128P;
//compute average channel_level on each (TX,RX) antenna pair //compute average channel_level on each (TX,RX) antenna pair
void nr_pdcch_channel_level(int32_t rx_size, void nr_pdcch_channel_level(int32_t rx_size,
int32_t dl_ch_estimates_ext[][rx_size], c16_t dl_ch_estimates_ext[][rx_size],
NR_DL_FRAME_PARMS *frame_parms, NR_DL_FRAME_PARMS *frame_parms,
int32_t *avg, int32_t *avg,
int symbol, int symbol,
uint8_t nb_rb) { int nb_rb)
int16_t rb; {
uint8_t aarx; for (int aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) {
simde__m128i *dl_ch128;
simde__m128i avg128P;
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
//clear average level //clear average level
avg128P = simde_mm_setzero_si128(); simde__m128i avg128P = simde_mm_setzero_si128();
dl_ch128=(simde__m128i *)&dl_ch_estimates_ext[aarx][symbol*nb_rb*12]; simde__m128i *dl_ch128 = (simde__m128i *)&dl_ch_estimates_ext[aarx][symbol * nb_rb * 12];
for (rb=0; rb<(nb_rb*3)>>2; rb++) { for (int rb = 0; rb < (nb_rb * 3) >> 2; rb++) {
avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[0],dl_ch128[0])); avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[0],dl_ch128[0]));
avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[1],dl_ch128[1])); avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[1],dl_ch128[1]));
avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[2],dl_ch128[2])); avg128P = simde_mm_add_epi32(avg128P,simde_mm_madd_epi16(dl_ch128[2],dl_ch128[2]));
...@@ -304,29 +278,22 @@ void nr_pdcch_channel_level(int32_t rx_size, ...@@ -304,29 +278,22 @@ void nr_pdcch_channel_level(int32_t rx_size,
avg[aarx] += ((int32_t *)&avg128P)[i] / (nb_rb * 9); avg[aarx] += ((int32_t *)&avg128P)[i] / (nb_rb * 9);
LOG_DDD("Channel level : %d\n",avg[aarx]); LOG_DDD("Channel level : %d\n",avg[aarx]);
} }
simde_mm_empty();
simde_m_empty();
} }
simde__m128i mmtmpPD0,mmtmpPD1,mmtmpPD2,mmtmpPD3;
// This function will extract the mapped DM-RS PDCCH REs as per 38.211 Section 7.4.1.3.2 (Mapping to physical resources) // This function will extract the mapped DM-RS PDCCH REs as per 38.211 Section 7.4.1.3.2 (Mapping to physical resources)
void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz, static void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz,
c16_t rxdataF[][rxdataF_sz], c16_t rxdataF[][rxdataF_sz],
int32_t est_size, int32_t est_size,
int32_t dl_ch_estimates[][est_size], c16_t dl_ch_estimates[][est_size],
int32_t rx_size, int32_t rx_size,
int32_t rxdataF_ext[][rx_size], c16_t rxdataF_ext[][rx_size],
int32_t dl_ch_estimates_ext[][rx_size], c16_t dl_ch_estimates_ext[][rx_size],
uint8_t symbol, int symbol,
NR_DL_FRAME_PARMS *frame_parms, NR_DL_FRAME_PARMS *frame_parms,
uint8_t *coreset_freq_dom, uint8_t *coreset_freq_dom,
uint32_t coreset_nbr_rb, uint32_t coreset_nbr_rb,
uint32_t n_BWP_start) { uint32_t n_BWP_start)
{
/* /*
* This function is demapping DM-RS PDCCH RE * This function is demapping DM-RS PDCCH RE
* Implementing 38.211 Section 7.4.1.3.2 Mapping to physical resources * Implementing 38.211 Section 7.4.1.3.2 Mapping to physical resources
...@@ -338,24 +305,19 @@ void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz, ...@@ -338,24 +305,19 @@ void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz,
* *
*/ */
#define NBR_RE_PER_RB_WITH_DMRS 12 #define NBR_RE_PER_RB_WITH_DMRS 12
// after removing the 3 DMRS RE, the RB contains 9 RE with PDCCH // after removing the 3 DMRS RE, the RB contains 9 RE with PDCCH
#define NBR_RE_PER_RB_WITHOUT_DMRS 9 #define NBR_RE_PER_RB_WITHOUT_DMRS 9
uint16_t c_rb; for (int aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) {
//uint8_t rb_count_bit; const c16_t *dl_ch0 = dl_ch_estimates[aarx] + frame_parms->ofdm_symbol_size * symbol;
uint8_t i, j, aarx; c16_t *rxFbase = rxdataF[aarx] + frame_parms->ofdm_symbol_size * symbol;
int32_t *dl_ch0, *dl_ch0_ext, *rxF, *rxF_ext; LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n", aarx);
for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) { const int offset = symbol * coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS;
dl_ch0 = &dl_ch_estimates[aarx][frame_parms->ofdm_symbol_size*symbol]; c16_t *dl_ch0_ext = &dl_ch_estimates_ext[aarx][offset];
LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n",aarx); LOG_DDD("dl_ch0_ext = &dl_ch_estimates_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n", aarx, offset);
c16_t *rxF_ext = &rxdataF_ext[aarx][offset];
dl_ch0_ext = &dl_ch_estimates_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)]; LOG_DDD("rxF_ext = &rxdataF_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n", aarx, offset);
LOG_DDD("dl_ch0_ext = &dl_ch_estimates_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n",
aarx,symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS));
rxF_ext = &rxdataF_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)];
LOG_DDD("rxF_ext = &rxdataF_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n",
aarx,symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS));
/* /*
* The following for loop handles treatment of PDCCH contained in table rxdataF (in frequency domain) * The following for loop handles treatment of PDCCH contained in table rxdataF (in frequency domain)
...@@ -368,157 +330,127 @@ void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz, ...@@ -368,157 +330,127 @@ void nr_pdcch_extract_rbs_single(uint32_t rxdataF_sz,
* 2. Number of RBs in the system bandwidth is odd * 2. Number of RBs in the system bandwidth is odd
* (particular case when the RB with DC as it is treated differently: it is situated in symbol borders of rxdataF) * (particular case when the RB with DC as it is treated differently: it is situated in symbol borders of rxdataF)
* 2.1 The RB is < than the N_RB_DL/2 -> IQ symbols are in the second half of the rxdataF (from first_carrier_offset) * 2.1 The RB is < than the N_RB_DL/2 -> IQ symbols are in the second half of the rxdataF (from first_carrier_offset)
* 2.2 The RB is > than the N_RB_DL/2 -> IQ symbols are in the first half of the rxdataF (from element 0 + 2nd half RB containing DC) * 2.2 The RB is > than the N_RB_DL/2 -> IQ symbols are in the first half of the rxdataF (from element 0 + 2nd half RB
* 2.3 The RB is == N_RB_DL/2 -> IQ symbols are in the upper border of the rxdataF for first 6 IQ element and the lower border of the rxdataF for the last 6 IQ elements * containing DC) 2.3 The RB is == N_RB_DL/2 -> IQ symbols are in the upper border of the rxdataF for first 6 IQ
* If the first RB containing PDCCH within the UE BWP and within the CORESET is higher than half of the system bandwidth (N_RB_DL), * element and the lower border of the rxdataF for the last 6 IQ elements If the first RB containing PDCCH within the UE BWP
* then the IQ symbol is going to be found at the position 0+c_rb-N_RB_DL/2 in rxdataF and * and within the CORESET is higher than half of the system bandwidth (N_RB_DL), then the IQ symbol is going to be found at
* we have to point the pointer at (1+c_rb-N_RB_DL/2) in rxdataF * the position 0+c_rb-N_RB_DL/2 in rxdataF and we have to point the pointer at (1+c_rb-N_RB_DL/2) in rxdataF
*/ */
int c_rb_by6; int c_rb = 0;
c_rb = 0; for (int rb = 0; rb < coreset_nbr_rb; rb++, c_rb++) {
for (int rb=0;rb<coreset_nbr_rb;rb++,c_rb++) { int c_rb_by6 = c_rb / 6;
c_rb_by6 = c_rb/6;
// skip zeros in frequency domain bitmap // skip zeros in frequency domain bitmap
while ((coreset_freq_dom[c_rb_by6>>3] & (1<<(7-(c_rb_by6&7)))) == 0) { while ((coreset_freq_dom[c_rb_by6 >> 3] & (1 << (7 - (c_rb_by6 & 7)))) == 0) {
c_rb+=6; c_rb += 6;
c_rb_by6 = c_rb/6; c_rb_by6 = c_rb / 6;
}
rxF=NULL;
// first we set initial conditions for pointer to rxdataF depending on the situation of the first RB within the CORESET (c_rb = n_BWP_start)
if (((c_rb + n_BWP_start) < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) {
//if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): even case
rxF = (int32_t *)&rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12];
LOG_DDD("in even case c_rb (%d) is lower than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
} }
if (((c_rb + n_BWP_start) >= (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // first we set initial conditions for pointer to rxdataF depending on the situation of the first RB within the CORESET
// number of RBs is even and c_rb is higher than half system bandwidth (we don't skip DC) // (c_rb = n_BWP_start)
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF if ((frame_parms->N_RB_DL & 1) == 1 && (c_rb + n_BWP_start) == (frame_parms->N_RB_DL >> 1)) {
rxF = (int32_t *)&rxdataF[aarx][12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) + symbol * frame_parms->ofdm_symbol_size]; // we point at the 1st part of the rxdataF in symbol // treatment of RB containing the DC
LOG_DDD("in even case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) + symbol * frame_parms->ofdm_symbol_size = (%d)]\n",
c_rb,aarx,(12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) + symbol * frame_parms->ofdm_symbol_size));
}
if (((c_rb + n_BWP_start) < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
//if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): odd case
rxF = (int32_t *)&rxdataF[aarx][frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size];
LOG_DDD("in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size));
}
if (((c_rb + n_BWP_start) > (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
// number of RBs is odd and c_rb is higher than half system bandwidth + 1
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF just after the first IQ symbols of the RB containing DC
rxF = (int32_t *)&rxdataF[aarx][12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) - 6 + symbol * frame_parms->ofdm_symbol_size]; // we point at the 1st part of the rxdataF in symbol
LOG_DDD("in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) - 6 + symbol * frame_parms->ofdm_symbol_size = (%d)]\n",
c_rb,aarx,(12*(c_rb + n_BWP_start - (frame_parms->N_RB_DL>>1)) - 6 + symbol * frame_parms->ofdm_symbol_size));
}
if (((c_rb + n_BWP_start) == (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // treatment of RB containing the DC
// if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC) // if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC)
// we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the end of the table) // we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the
rxF = (int32_t *)&rxdataF[aarx][frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size]; // end of the table)
LOG_DDD("in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size = (%d)]\n", c16_t *rxF = rxFbase + frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start);
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start) + symbol * frame_parms->ofdm_symbol_size));
j = 0;
for (i = 0; i < 6; i++) { //treating first part of the RB note that i=5 would correspond to DC. We treat it in NR int i = 0, j = 0;
for (; i < 6; i++) { // treating first part of the RB note that i=5 would correspond to DC. We treat it in NR
if ((i != 1) && (i != 5)) { if ((i != 1) && (i != 5)) {
dl_ch0_ext[j] = dl_ch0[i]; dl_ch0_ext[j] = dl_ch0[i];
rxF_ext[j] = rxF[i]; rxF_ext[j] = rxF[i];
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n", LOG_DSYMB("");
c_rb, i, j, *(short *) &rxF_ext[j],*(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
j++; j++;
} else { } else {
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n", LOG_DSYMB("\t\t <==> DM-RS PDCCH, this is a pilot symbol\n");
c_rb, i, j, *(short *) &rxF_ext[j], *(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
} }
} }
// then we point at the begining of the symbol part of rxdataF do process second part of RB // then we point at the begining of the symbol part of rxdataF do process second part of RB
rxF = (int32_t *)&rxdataF[aarx][symbol * frame_parms->ofdm_symbol_size]; // we point at the 1st part of the rxdataF in symbol
LOG_DDD("in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][symbol * frame_parms->ofdm_symbol_size = (%d)]\n",
c_rb,aarx,(symbol * frame_parms->ofdm_symbol_size));
for (; i < 12; i++) { for (; i < 12; i++) {
if ((i != 9)) { if ((i != 9)) {
dl_ch0_ext[j] = dl_ch0[i]; dl_ch0_ext[j] = dl_ch0[i];
rxF_ext[j] = rxF[i - 6]; rxF_ext[j] = rxFbase[i - 6];
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n", LOG_DSYMB("");
c_rb, i, j, *(short *) &rxF_ext[j],*(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i-6], *(1 + (short *) &rxF[i-6]));
j++; j++;
} else { } else {
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n", LOG_DSYMB("\t\t <==> DM-RS PDCCH, this is a pilot symbol\n");
c_rb, i, j, *(short *) &rxF_ext[j], *(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i-6], *(1 + (short *) &rxF[i-6]));
} }
} }
dl_ch0_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
rxF_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
dl_ch0 += 12;
} else { // treatment of any RB that does not contain the DC } else { // treatment of any RB that does not contain the DC
j = 0; c16_t *rxF=NULL;
if ((frame_parms->N_RB_DL & 1) == 0) {
if ((c_rb + n_BWP_start) < (frame_parms->N_RB_DL >> 1))
// if RB to be treated is lower than middle system bandwidth then rxdataF pointed
// at (offset + c_br + symbol * ofdm_symbol_size): even case
rxF = rxFbase + (frame_parms->first_carrier_offset + 12 * c_rb) + n_BWP_start * 12;
else
// number of RBs is even and c_rb is higher than half system bandwidth (we don't skip DC)
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF
// we point at the 1st part of the rxdataF in symbol
rxF = rxFbase + 12 * (c_rb + n_BWP_start - (frame_parms->N_RB_DL >> 1));
} else {
if ((c_rb + n_BWP_start) < (frame_parms->N_RB_DL >> 1))
// if RB to be treated is lower than middle system bandwidth then rxdataF pointed
// at (offset + c_br + symbol * ofdm_symbol_size): odd case
rxF = rxFbase + frame_parms->first_carrier_offset + 12 * (c_rb + n_BWP_start);
else if ((c_rb + n_BWP_start) > (frame_parms->N_RB_DL >> 1))
// number of RBs is odd and c_rb is higher than half system bandwidth + 1
// if these conditions are true the pointer has to be situated at the 1st part of
// the rxdataF just after the first IQ symbols of the RB containing DC
// we point at the 1st part of the rxdataF in symbol
rxF = rxFbase + 12 * (c_rb + n_BWP_start - (frame_parms->N_RB_DL >> 1)) - 6;
}
AssertFatal(rxF, "bug");
int j = 0;
for (i = 0; i < 12; i++) { for (int i = 0; i < 12; i++) {
if ((i != 1) && (i != 5) && (i != 9)) { if ((i != 1) && (i != 5) && (i != 9)) {
rxF_ext[j] = rxF[i]; rxF_ext[j] = rxF[i];
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n",
c_rb, i, j, *(short *) &rxF_ext[j],*(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
dl_ch0_ext[j] = dl_ch0[i]; dl_ch0_ext[j] = dl_ch0[i];
LOG_DSYMB("");
j++; j++;
} else { } else {
LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n", LOG_DSYMB("\t\t <==> DM-RS PDCCH, this is a pilot symbol\n");
c_rb, i, j, *(short *) &rxF_ext[j], *(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
} }
} }
dl_ch0_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
rxF_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
dl_ch0 += 12;
} }
dl_ch0_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
rxF_ext += NBR_RE_PER_RB_WITHOUT_DMRS;
dl_ch0 += 12;
} }
} }
} }
#define print_shorts(s,x) printf("%s %d,%d,%d,%d,%d,%d,%d,%d\n",s,(x)[0],(x)[1],(x)[2],(x)[3],(x)[4],(x)[5],(x)[6],(x)[7]) #define print_shorts(s,x) printf("%s %d,%d,%d,%d,%d,%d,%d,%d\n",s,(x)[0],(x)[1],(x)[2],(x)[3],(x)[4],(x)[5],(x)[6],(x)[7])
void nr_pdcch_channel_compensation(int32_t rx_size, int32_t rxdataF_ext[][rx_size], void nr_pdcch_channel_compensation(int32_t rx_size,
int32_t dl_ch_estimates_ext[][rx_size], c16_t rxdataF_ext[][rx_size],
int32_t rxdataF_comp[][rx_size], c16_t dl_ch_estimates_ext[][rx_size],
c16_t rxdataF_comp[][rx_size],
int32_t **rho, int32_t **rho,
NR_DL_FRAME_PARMS *frame_parms, NR_DL_FRAME_PARMS *frame_parms,
uint8_t symbol, uint8_t symbol,
uint8_t output_shift, uint8_t output_shift,
uint32_t coreset_nbr_rb) { uint32_t coreset_nbr_rb)
uint16_t rb; //,nb_rb=20; {
uint8_t aarx; for (int aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) {
simde__m128i mmtmpP0,mmtmpP1,mmtmpP2,mmtmpP3; simde__m128i *dl_ch128 = (simde__m128i *)&dl_ch_estimates_ext[aarx][symbol * coreset_nbr_rb * 12];
simde__m128i *dl_ch128,*rxdataF128,*rxdataF_comp128; simde__m128i *rxdataF128 = (simde__m128i *)&rxdataF_ext[aarx][symbol * coreset_nbr_rb * 12];
simde__m128i *rxdataF_comp128 = (simde__m128i *)&rxdataF_comp[aarx][symbol * coreset_nbr_rb * 12];
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
dl_ch128 = (simde__m128i *)&dl_ch_estimates_ext[aarx][symbol*coreset_nbr_rb*12];
rxdataF128 = (simde__m128i *)&rxdataF_ext[aarx][symbol*coreset_nbr_rb*12];
rxdataF_comp128 = (simde__m128i *)&rxdataF_comp[aarx][symbol*coreset_nbr_rb*12];
//printf("ch compensation dl_ch ext addr %p \n", &dl_ch_estimates_ext[(aatx<<1)+aarx][symbol*20*12]); //printf("ch compensation dl_ch ext addr %p \n", &dl_ch_estimates_ext[(aatx<<1)+aarx][symbol*20*12]);
//printf("rxdataf ext addr %p symbol %d\n", &rxdataF_ext[aarx][symbol*20*12], symbol); //printf("rxdataf ext addr %p symbol %d\n", &rxdataF_ext[aarx][symbol*20*12], symbol);
//printf("rxdataf_comp addr %p\n",&rxdataF_comp[(aatx<<1)+aarx][symbol*20*12]); //printf("rxdataf_comp addr %p\n",&rxdataF_comp[(aatx<<1)+aarx][symbol*20*12]);
for (rb=0; rb<(coreset_nbr_rb*3)>>2; rb++) { for (int rb = 0; rb < (coreset_nbr_rb * 3) >> 2; rb++) {
// multiply by conjugated channel // multiply by conjugated channel
mmtmpP0 = simde_mm_madd_epi16(dl_ch128[0],rxdataF128[0]); simde__m128i mmtmpP0 = simde_mm_madd_epi16(dl_ch128[0], rxdataF128[0]);
//print_ints("re",&mmtmpP0); //print_ints("re",&mmtmpP0);
// mmtmpP0 contains real part of 4 consecutive outputs (32-bit) // mmtmpP0 contains real part of 4 consecutive outputs (32-bit)
mmtmpP1 = simde_mm_shufflelo_epi16(dl_ch128[0], SIMDE_MM_SHUFFLE(2,3,0,1)); simde__m128i mmtmpP1 = simde_mm_shufflelo_epi16(dl_ch128[0], SIMDE_MM_SHUFFLE(2, 3, 0, 1));
mmtmpP1 = simde_mm_shufflehi_epi16(mmtmpP1, SIMDE_MM_SHUFFLE(2,3,0,1)); mmtmpP1 = simde_mm_shufflehi_epi16(mmtmpP1, SIMDE_MM_SHUFFLE(2,3,0,1));
mmtmpP1 = simde_mm_sign_epi16(mmtmpP1,*(simde__m128i *)&conjugate[0]); mmtmpP1 = simde_mm_sign_epi16(mmtmpP1,*(simde__m128i *)&conjugate[0]);
//print_ints("im",&mmtmpP1); //print_ints("im",&mmtmpP1);
...@@ -528,8 +460,8 @@ void nr_pdcch_channel_compensation(int32_t rx_size, int32_t rxdataF_ext[][rx_siz ...@@ -528,8 +460,8 @@ void nr_pdcch_channel_compensation(int32_t rx_size, int32_t rxdataF_ext[][rx_siz
// print_ints("re(shift)",&mmtmpP0); // print_ints("re(shift)",&mmtmpP0);
mmtmpP1 = simde_mm_srai_epi32(mmtmpP1,output_shift); mmtmpP1 = simde_mm_srai_epi32(mmtmpP1,output_shift);
// print_ints("im(shift)",&mmtmpP1); // print_ints("im(shift)",&mmtmpP1);
mmtmpP2 = simde_mm_unpacklo_epi32(mmtmpP0,mmtmpP1); simde__m128i mmtmpP2 = simde_mm_unpacklo_epi32(mmtmpP0, mmtmpP1);
mmtmpP3 = simde_mm_unpackhi_epi32(mmtmpP0,mmtmpP1); simde__m128i mmtmpP3 = simde_mm_unpackhi_epi32(mmtmpP0, mmtmpP1);
//print_ints("c0",&mmtmpP2); //print_ints("c0",&mmtmpP2);
//print_ints("c1",&mmtmpP3); //print_ints("c1",&mmtmpP3);
rxdataF_comp128[0] = simde_mm_packs_epi32(mmtmpP2,mmtmpP3); rxdataF_comp128[0] = simde_mm_packs_epi32(mmtmpP2,mmtmpP3);
...@@ -572,49 +504,43 @@ void nr_pdcch_channel_compensation(int32_t rx_size, int32_t rxdataF_ext[][rx_siz ...@@ -572,49 +504,43 @@ void nr_pdcch_channel_compensation(int32_t rx_size, int32_t rxdataF_ext[][rx_siz
for (int i=0; i<12 ; i++) for (int i=0; i<12 ; i++)
LOG_DDD("rxdataF128[%d]=(%d,%d) X dlch[%d]=(%d,%d) rxdataF_comp128[%d]=(%d,%d)\n", LOG_DDD("rxdataF128[%d]=(%d,%d) X dlch[%d]=(%d,%d) rxdataF_comp128[%d]=(%d,%d)\n",
(rb*12)+i, ((short *)rxdataF128)[i<<1],((short *)rxdataF128)[1+(i<<1)], (rb * 12) + i,
(rb*12)+i, ((short *)dl_ch128)[i<<1],((short *)dl_ch128)[1+(i<<1)], ((c16_t *)rxdataF128)[i].r,
(rb*12)+i, ((short *)rxdataF_comp128)[i<<1],((short *)rxdataF_comp128)[1+(i<<1)]); ((c16_t *)rxdataF128)[i].i,
(rb * 12) + i,
((c16_t *)dl_ch128)[i].r,
((c16_t *)dl_ch128)[i].i,
(rb * 12) + i,
((c16_t *)rxdataF_comp128)[i].r,
((c16_t *)rxdataF_comp128)[i].i);
dl_ch128+=3; dl_ch128+=3;
rxdataF128+=3; rxdataF128+=3;
rxdataF_comp128+=3; rxdataF_comp128+=3;
} }
} }
simde_mm_empty();
simde_m_empty();
} }
static void nr_pdcch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, int32_t rx_size, c16_t rxdataF_comp[][rx_size], int symbol)
void nr_pdcch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, {
int32_t rx_size,
int32_t rxdataF_comp[][rx_size],
uint8_t symbol) {
simde__m128i *rxdataF_comp128_0,*rxdataF_comp128_1;
int32_t i;
if (frame_parms->nb_antennas_rx>1) { if (frame_parms->nb_antennas_rx>1) {
rxdataF_comp128_0 = (simde__m128i *)&rxdataF_comp[0][symbol*frame_parms->N_RB_DL*12]; simde__m128i *rxdataF_comp128_0 = (simde__m128i *)&rxdataF_comp[0][symbol * frame_parms->N_RB_DL * 12];
rxdataF_comp128_1 = (simde__m128i *)&rxdataF_comp[1][symbol*frame_parms->N_RB_DL*12]; simde__m128i *rxdataF_comp128_1 = (simde__m128i *)&rxdataF_comp[1][symbol * frame_parms->N_RB_DL * 12];
const int sz = frame_parms->N_RB_DL * 3;
// MRC on each re of rb // MRC on each re of rb
for (i=0; i<frame_parms->N_RB_DL*3; i++) { for (int i = 0; i < sz; i++) {
rxdataF_comp128_0[i] = simde_mm_adds_epi16(simde_mm_srai_epi16(rxdataF_comp128_0[i],1),simde_mm_srai_epi16(rxdataF_comp128_1[i],1)); rxdataF_comp128_0[i] = simde_mm_adds_epi16(simde_mm_srai_epi16(rxdataF_comp128_0[i],1),simde_mm_srai_epi16(rxdataF_comp128_1[i],1));
} }
} }
simde_mm_empty();
simde_m_empty();
} }
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, void nr_rx_pdcch(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
int16_t *pdcch_e_rx, c16_t *pdcch_e_rx,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15,
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]) c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
{ {
NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
...@@ -626,22 +552,25 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -626,22 +552,25 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
// Pointers to extracted PDCCH symbols in frequency-domain. // Pointers to extracted PDCCH symbols in frequency-domain.
int32_t rx_size = ((4 * frame_parms->N_RB_DL * 12 + 31) >> 5) << 5; int32_t rx_size = ((4 * frame_parms->N_RB_DL * 12 + 31) >> 5) << 5;
__attribute__ ((aligned(32))) int32_t rxdataF_ext[frame_parms->nb_antennas_rx][rx_size]; __attribute__((aligned(32))) c16_t rxdataF_ext[frame_parms->nb_antennas_rx][rx_size];
__attribute__ ((aligned(32))) int32_t rxdataF_comp[frame_parms->nb_antennas_rx][rx_size]; __attribute__((aligned(32))) c16_t rxdataF_comp[frame_parms->nb_antennas_rx][rx_size];
__attribute__ ((aligned(32))) int32_t pdcch_dl_ch_estimates_ext[frame_parms->nb_antennas_rx][rx_size]; __attribute__((aligned(32))) c16_t pdcch_dl_ch_estimates_ext[frame_parms->nb_antennas_rx][rx_size];
memset(rxdataF_comp, 0, sizeof(rxdataF_comp)); memset(rxdataF_comp, 0, sizeof(rxdataF_comp));
// Pointer to llrs, 4-bit resolution. // Pointer to llrs, 4-bit resolution.
int32_t llr_size = 2*4*n_rb*9; int32_t llr_size = 4 * n_rb * 9;
int16_t llr[llr_size]; c16_t llr[llr_size];
memset(llr, 0, sizeof(llr)); memset(llr, 0, sizeof(llr));
LOG_D(PHY,"pdcch coreset: freq %x, n_rb %d, rb_offset %d\n", LOG_D(NR_PHY_DCI,
rel15->coreset.frequency_domain_resource[0],n_rb,rb_offset); "pdcch coreset: freq %x, n_rb %d, rb_offset %d\n",
rel15->coreset.frequency_domain_resource[0],
n_rb,
rb_offset);
for (int s=rel15->coreset.StartSymbolIndex; s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration); s++) { for (int s=rel15->coreset.StartSymbolIndex; s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration); s++) {
LOG_D(PHY,"in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n"); LOG_D(NR_PHY_DCI, "in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n");
nr_pdcch_extract_rbs_single(ue->frame_parms.samples_per_slot_wCP, nr_pdcch_extract_rbs_single(ue->frame_parms.samples_per_slot_wCP,
rxdataF, rxdataF,
...@@ -656,8 +585,11 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -656,8 +585,11 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
n_rb, n_rb,
rel15->BWPStart); rel15->BWPStart);
LOG_D(PHY,"we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP); LOG_D(NR_PHY_DCI,
LOG_D(PHY,"in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n"); "we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, "
"pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",
*avgP);
LOG_D(NR_PHY_DCI, "in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n");
// compute channel level based on ofdm symbol 0 // compute channel level based on ofdm symbol 0
nr_pdcch_channel_level(rx_size, nr_pdcch_channel_level(rx_size,
pdcch_dl_ch_estimates_ext, pdcch_dl_ch_estimates_ext,
...@@ -673,13 +605,13 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -673,13 +605,13 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx; log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx;
#ifdef UE_DEBUG_TRACE #ifdef UE_DEBUG_TRACE
LOG_D(PHY, "slot %d: pdcch log2_maxh = %d (%d,%d)\n", proc->nr_slot_rx, log2_maxh, avgP[0], avgs); LOG_D(NR_PHY_DCI, "slot %d: pdcch log2_maxh = %d (%d,%d)\n", proc->nr_slot_rx, log2_maxh, avgP[0], avgs);
#endif #endif
#if T_TRACER #if T_TRACER
T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(proc->frame_rx % 1024), T_INT(proc->nr_slot_rx), T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3])); T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(proc->frame_rx % 1024), T_INT(proc->nr_slot_rx), T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3]));
#endif #endif
LOG_D(PHY,"we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh); LOG_D(NR_PHY_DCI, "we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n", log2_maxh);
LOG_D(PHY,"in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n"); LOG_D(NR_PHY_DCI, "in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n");
// compute LLRs for ofdm symbol 0 only // compute LLRs for ofdm symbol 0 only
nr_pdcch_channel_compensation(rx_size, rxdataF_ext, nr_pdcch_channel_compensation(rx_size, rxdataF_ext,
pdcch_dl_ch_estimates_ext, pdcch_dl_ch_estimates_ext,
...@@ -693,12 +625,12 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -693,12 +625,12 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
UEscopeCopy(ue, pdcchRxdataF_comp, rxdataF_comp, sizeof(struct complex16), frame_parms->nb_antennas_rx, rx_size, 0); UEscopeCopy(ue, pdcchRxdataF_comp, rxdataF_comp, sizeof(struct complex16), frame_parms->nb_antennas_rx, rx_size, 0);
if (frame_parms->nb_antennas_rx > 1) { if (frame_parms->nb_antennas_rx > 1) {
LOG_D(PHY,"we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", frame_parms->nb_antennas_rx); LOG_D(NR_PHY_DCI, "we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", frame_parms->nb_antennas_rx);
nr_pdcch_detection_mrc(frame_parms, rx_size, rxdataF_comp,s); nr_pdcch_detection_mrc(frame_parms, rx_size, rxdataF_comp,s);
} }
LOG_D(PHY,"we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s); LOG_D(NR_PHY_DCI, "we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n", s);
LOG_D(PHY,"in nr_pdcch_llr(rxdataF_comp -> llr)\n"); LOG_D(NR_PHY_DCI, "in nr_pdcch_llr(rxdataF_comp -> llr)\n");
nr_pdcch_llr(frame_parms, nr_pdcch_llr(frame_parms,
rx_size, rx_size,
rxdataF_comp, rxdataF_comp,
...@@ -706,23 +638,15 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -706,23 +638,15 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
s, s,
n_rb); n_rb);
UEscopeCopy(ue, pdcchLlr, llr, sizeof(int16_t), 1, llr_size, 0); UEscopeCopy(ue, pdcchLlr, llr, sizeof(c16_t), 1, llr_size, 0);
#if T_TRACER
// T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL),
// T_INT(n_pdcch_symbols),
// T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4));
#endif
#ifdef DEBUG_DCI_DECODING #ifdef DEBUG_DCI_DECODING
printf("demapping: slot %u, mi %d\n",slot,get_mi(frame_parms,slot)); printf("demapping: slot %u, mi %d\n",slot,get_mi(frame_parms,slot));
#endif #endif
} }
LOG_D(PHY,"we enter nr_pdcch_demapping_deinterleaving(), number of candidates %d\n",rel15->number_of_candidates); nr_pdcch_demapping_deinterleaving(llr,
nr_pdcch_demapping_deinterleaving((uint32_t *) llr, pdcch_e_rx,
(uint32_t *) pdcch_e_rx,
rel15->coreset.duration, rel15->coreset.duration,
rel15->coreset.StartSymbolIndex, rel15->coreset.StartSymbolIndex,
n_rb, n_rb,
...@@ -732,18 +656,13 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -732,18 +656,13 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
rel15->number_of_candidates, rel15->number_of_candidates,
rel15->CCE, rel15->CCE,
rel15->L); rel15->L);
LOG_D(PHY,"we end nr_pdcch_demapping_deinterleaving()\n");
LOG_D(PHY,"Ending nr_rx_pdcch() function\n");
return (0);
} }
void nr_pdcch_unscrambling(int16_t *e_rx, static void nr_pdcch_unscrambling(c16_t *e_rx,
uint16_t scrambling_RNTI, uint16_t scrambling_RNTI,
uint32_t length, uint32_t length,
uint16_t pdcch_DMRS_scrambling_id, uint16_t pdcch_DMRS_scrambling_id,
int16_t *z2) int16_t *z2)
{ {
int i; int i;
uint8_t reset; uint8_t reset;
...@@ -755,8 +674,8 @@ void nr_pdcch_unscrambling(int16_t *e_rx, ...@@ -755,8 +674,8 @@ void nr_pdcch_unscrambling(int16_t *e_rx,
n_id = pdcch_DMRS_scrambling_id; n_id = pdcch_DMRS_scrambling_id;
x2 = ((rnti << 16) + n_id) % (1U << 31); // this is c_init in 38.211 v15.1.0 Section 7.3.2.3 x2 = ((rnti << 16) + n_id) % (1U << 31); // this is c_init in 38.211 v15.1.0 Section 7.3.2.3
LOG_D(PHY,"PDCCH Unscrambling x2 %x : scrambling_RNTI %x\n", x2, rnti); LOG_D(NR_PHY_DCI, "PDCCH Unscrambling x2 %x : scrambling_RNTI %x\n", x2, rnti);
int16_t *ptr = &e_rx[0].r;
for (i = 0; i < length; i++) { for (i = 0; i < length; i++) {
if ((i & 0x1f) == 0) { if ((i & 0x1f) == 0) {
s = lte_gold_generic(&x1, &x2, reset); s = lte_gold_generic(&x1, &x2, reset);
...@@ -764,9 +683,9 @@ void nr_pdcch_unscrambling(int16_t *e_rx, ...@@ -764,9 +683,9 @@ void nr_pdcch_unscrambling(int16_t *e_rx,
} }
if (((s >> (i % 32)) & 1) == 1) if (((s >> (i % 32)) & 1) == 1)
z2[i] = -e_rx[i]; z2[i] = -ptr[i];
else else
z2[i]=e_rx[i]; z2[i] = ptr[i];
} }
} }
...@@ -802,16 +721,14 @@ static uint16_t nr_dci_false_detection(uint64_t *dci, ...@@ -802,16 +721,14 @@ static uint16_t nr_dci_false_detection(uint64_t *dci,
return x; return x;
} }
uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int16_t *pdcch_e_rx, c16_t *pdcch_e_rx,
fapi_nr_dci_indication_t *dci_ind, fapi_nr_dci_indication_t *dci_ind,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15)
{ {
//int gNB_id = 0;
int16_t tmp_e[16*108];
rnti_t n_rnti;
int e_rx_cand_idx = 0; int e_rx_cand_idx = 0;
*dci_ind = (fapi_nr_dci_indication_t){.SFN = proc->frame_rx, .slot = proc->nr_slot_rx};
for (int j=0;j<rel15->number_of_candidates;j++) { for (int j=0;j<rel15->number_of_candidates;j++) {
int CCEind = rel15->CCE[j]; int CCEind = rel15->CCE[j];
...@@ -822,71 +739,88 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -822,71 +739,88 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
for (int k = 0; k < rel15->num_dci_options; k++) { for (int k = 0; k < rel15->num_dci_options; k++) {
// skip this candidate if we've already found one with the // skip this candidate if we've already found one with the
// same rnti and format at a different aggregation level // same rnti and format at a different aggregation level
int dci_found=0; int ind;
for (int ind=0;ind < dci_ind->number_of_dcis ; ind++) { for (ind = 0; ind < dci_ind->number_of_dcis; ind++) {
if (rel15->rnti== dci_ind->dci_list[ind].rnti && if (rel15->rnti == dci_ind->dci_list[ind].rnti && rel15->dci_format_options[k] == dci_ind->dci_list[ind].dci_format) {
rel15->dci_format_options[k]==dci_ind->dci_list[ind].dci_format) { break;
dci_found=1;
break;
} }
} }
if (dci_found == 1) if (ind < dci_ind->number_of_dcis)
continue; continue;
int dci_length = rel15->dci_length_options[k]; int dci_length = rel15->dci_length_options[k];
uint64_t dci_estimation[2]= {0}; uint64_t dci_estimation[2]= {0};
LOG_D(PHY, "(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %s\n", LOG_D(NR_PHY_DCI,
proc->frame_rx, proc->nr_slot_rx, j, rel15->number_of_candidates, CCEind, e_rx_cand_idx, L, dci_length, nr_dci_format_string[rel15->dci_format_options[k]]); "(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %s\n",
proc->frame_rx,
proc->nr_slot_rx,
j,
rel15->number_of_candidates,
CCEind,
e_rx_cand_idx,
L,
dci_length,
nr_dci_format_string[rel15->dci_format_options[k]]);
int16_t tmp_e[16 * 108];
nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e);
// this polar version decodes 64 bits max, dci_estimation[1] will never be filled
#ifdef DEBUG_DCI_DECODING
uint32_t *z = (uint32_t *) &e_rx[e_rx_cand_idx];
for (int index_z = 0; index_z < L*6; index_z++){
for (int i=0; i<9; i++) {
LOG_I(PHY,"z[%d]=(%d,%d) \n", (9*index_z + i), *(int16_t *) &z[9*index_z + i],*(1 + (int16_t *) &z[9*index_z + i]));
}
}
#endif
uint16_t crc = polar_decoder_int16(tmp_e, uint16_t crc = polar_decoder_int16(tmp_e,
dci_estimation, dci_estimation,
1, 1,
NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L); NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
n_rnti = rel15->rnti; rnti_t n_rnti = rel15->rnti;
LOG_D(PHY, "(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx )\n", LOG_D(NR_PHY_DCI,
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length, *(unsigned long long*)dci_estimation); "(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %lx, is rnti: %d )\n",
proc->frame_rx,
proc->nr_slot_rx,
n_rnti,
nr_dci_format_string[rel15->dci_format_options[k]],
CCEind,
dci_length,
dci_estimation[0],
crc == n_rnti);
if (crc == n_rnti) { if (crc == n_rnti) {
LOG_D(PHY, "(%i.%i) Received dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length,*(unsigned long long*)dci_estimation);
uint16_t mb = nr_dci_false_detection(dci_estimation,tmp_e,L*108,n_rnti, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L); uint16_t mb = nr_dci_false_detection(dci_estimation,tmp_e,L*108,n_rnti, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
ue->dci_thres = (ue->dci_thres + mb) / 2; ue->dci_thres = (ue->dci_thres + mb) / 2;
if (mb > (ue->dci_thres+30)) { if (mb > (ue->dci_thres+30)) {
LOG_W(PHY,"DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n",j,mb,L*108,ue->dci_thres); LOG_W(NR_PHY_DCI,
"DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n",
j,
mb,
L * 108,
ue->dci_thres);
continue; continue;
} else { } else {
dci_ind->SFN = proc->frame_rx; AssertFatal(dci_ind->number_of_dcis < sizeofArray(dci_ind->dci_list), "Fix allocation\n");
dci_ind->slot = proc->nr_slot_rx; fapi_nr_dci_indication_pdu_t *dci = dci_ind->dci_list + dci_ind->number_of_dcis;
dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti; *dci = (fapi_nr_dci_indication_pdu_t){
dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind; .rnti = n_rnti,
dci_ind->dci_list[dci_ind->number_of_dcis].N_CCE = L; .n_CCE = CCEind,
dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format_options[k]; .N_CCE = L,
dci_ind->dci_list[dci_ind->number_of_dcis].ss_type = rel15->ss_type_options[k]; .dci_format = rel15->dci_format_options[k],
dci_ind->dci_list[dci_ind->number_of_dcis].coreset_type = rel15->coreset.CoreSetType; .ss_type = rel15->ss_type_options[k],
.coreset_type = rel15->coreset.CoreSetType,
};
int n_rb, rb_offset; int n_rb, rb_offset;
get_coreset_rballoc(rel15->coreset.frequency_domain_resource, &n_rb, &rb_offset); get_coreset_rballoc(rel15->coreset.frequency_domain_resource, &n_rb, &rb_offset);
dci_ind->dci_list[dci_ind->number_of_dcis].cset_start = rel15->BWPStart + rb_offset; dci->cset_start = rel15->BWPStart + rb_offset;
dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length; dci->payloadSize = dci_length;
memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8); memcpy(dci->payloadBits, dci_estimation, (dci_length + 7) / 8);
dci_ind->number_of_dcis++; dci_ind->number_of_dcis++;
break; // If DCI is found, no need to check for remaining DCI lengths break; // If DCI is found, no need to check for remaining DCI lengths
} }
} else { } else {
LOG_D(PHY,"(%i.%i) Decoded crc %x does not match rnti %x for DCI format %d\n", proc->frame_rx, proc->nr_slot_rx, crc, n_rnti, rel15->dci_format_options[k]); LOG_D(NR_PHY_DCI,
"(%i.%i) Decoded crc %x does not match rnti %x for DCI format %d\n",
proc->frame_rx,
proc->nr_slot_rx,
crc,
n_rnti,
rel15->dci_format_options[k]);
} }
} }
e_rx_cand_idx += 9*L*6*2; //e_rx index for next candidate (L CCEs, 6 REGs per CCE and 9 REs per REG and 2 uint16_t per RE) e_rx_cand_idx += 9 * L * 6; // e_rx index for next candidate (L CCEs, 6 REGs per CCE and 9 REs per REG )
} }
return(dci_ind->number_of_dcis);
} }
...@@ -266,13 +266,13 @@ void nr_dlsch_unscrambling(int16_t* llr, ...@@ -266,13 +266,13 @@ void nr_dlsch_unscrambling(int16_t* llr,
uint32_t Nid, uint32_t Nid,
uint32_t n_RNTI); uint32_t n_RNTI);
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, void nr_rx_pdcch(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
int16_t *pdcch_e_rx, c16_t *pdcch_e_rx,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15,
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]); c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]);
/*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix) /*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix)
@param phy_vars_ue Pointer to UE variables @param phy_vars_ue Pointer to UE variables
...@@ -361,17 +361,11 @@ void nr_sl_rf_card_config_freq(PHY_VARS_NR_UE *ue, ...@@ -361,17 +361,11 @@ void nr_sl_rf_card_config_freq(PHY_VARS_NR_UE *ue,
openair0_config_t *openair0_cfg, openair0_config_t *openair0_cfg,
int freq_offset); int freq_offset);
void nr_pdcch_unscrambling(int16_t *z, void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
uint16_t scrambling_RNTI, const UE_nr_rxtx_proc_t *proc,
uint32_t length, c16_t *pdcch_e_rx,
uint16_t pdcch_DMRS_scrambling_id, fapi_nr_dci_indication_t *dci_ind,
int16_t *z2); fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15);
uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc,
int16_t *pdcch_e_rx,
fapi_nr_dci_indication_t *dci_ind,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15);
/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel /** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel
estimation. It performs estimation. It performs
......
...@@ -152,7 +152,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind, ...@@ -152,7 +152,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
nr_phy_data_t *phy_data, nr_phy_data_t *phy_data,
int n_ss, int n_ss,
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]); c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]);
......
...@@ -426,16 +426,13 @@ unsigned int nr_get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb ...@@ -426,16 +426,13 @@ unsigned int nr_get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb
int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
nr_phy_data_t *phy_data, nr_phy_data_t *phy_data,
int n_ss, int n_ss,
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]) c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
{ {
int frame_rx = proc->frame_rx; int frame_rx = proc->frame_rx;
int nr_slot_rx = proc->nr_slot_rx; int nr_slot_rx = proc->nr_slot_rx;
unsigned int dci_cnt=0;
fapi_nr_dci_indication_t dci_ind = {0};
nr_downlink_indication_t dl_indication;
NR_UE_PDCCH_CONFIG *phy_pdcch_config = &phy_data->phy_pdcch_config; NR_UE_PDCCH_CONFIG *phy_pdcch_config = &phy_data->phy_pdcch_config;
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15 = &phy_pdcch_config->pdcch_config[n_ss]; fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15 = &phy_pdcch_config->pdcch_config[n_ss];
...@@ -444,39 +441,26 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, ...@@ -444,39 +441,26 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
/// PDCCH/DCI e-sequence (input to rate matching). /// PDCCH/DCI e-sequence (input to rate matching).
int32_t pdcch_e_rx_size = NR_MAX_PDCCH_SIZE; int32_t pdcch_e_rx_size = NR_MAX_PDCCH_SIZE;
int16_t pdcch_e_rx[pdcch_e_rx_size]; c16_t pdcch_e_rx[pdcch_e_rx_size];
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_IN);
nr_rx_pdcch(ue, proc, pdcch_est_size, pdcch_dl_ch_estimates, pdcch_e_rx, rel15, rxdataF); nr_rx_pdcch(ue, proc, pdcch_est_size, pdcch_dl_ch_estimates, pdcch_e_rx, rel15, rxdataF);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN);
#ifdef NR_PDCCH_SCHED_DEBUG
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure for search space %d)\n",
n_ss);
#endif
dci_cnt = nr_dci_decoding_procedure(ue, proc, pdcch_e_rx, &dci_ind, rel15);
#ifdef NR_PDCCH_SCHED_DEBUG
LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT); fapi_nr_dci_indication_t dci_ind;
nr_dci_decoding_procedure(ue, proc, pdcch_e_rx, &dci_ind, rel15);
for (int i=0; i<dci_cnt; i++) { for (int i = 0; i < dci_ind.number_of_dcis; i++) {
LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d: DCI %i of %d total DCIs found --> rnti %x : format %d\n", LOG_D(PHY,
ue->Mod_id,frame_rx%1024,nr_slot_rx, "[UE %d] AbsSubFrame %d.%d: DCI %i of %d total DCIs found --> rnti %x : format %d\n",
ue->Mod_id,
frame_rx % 1024,
nr_slot_rx,
i + 1, i + 1,
dci_cnt, dci_ind.number_of_dcis,
dci_ind.dci_list[i].rnti, dci_ind.dci_list[i].rnti,
dci_ind.dci_list[i].dci_format); dci_ind.dci_list[i].dci_format);
} }
dci_ind.number_of_dcis = dci_cnt; nr_downlink_indication_t dl_indication;
// fill dl_indication message // fill dl_indication message
nr_fill_dl_indication(&dl_indication, &dci_ind, NULL, proc, ue, phy_data); nr_fill_dl_indication(&dl_indication, &dci_ind, NULL, proc, ue, phy_data);
// send to mac // send to mac
...@@ -485,7 +469,7 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, ...@@ -485,7 +469,7 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
stop_meas(&ue->dlsch_rx_pdcch_stats); stop_meas(&ue->dlsch_rx_pdcch_stats);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT);
return(dci_cnt); return (dci_ind.number_of_dcis);
} }
static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
...@@ -861,9 +845,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr ...@@ -861,9 +845,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr
const uint32_t rxdataF_sz = ue->frame_parms.samples_per_slot_wCP; const uint32_t rxdataF_sz = ue->frame_parms.samples_per_slot_wCP;
__attribute__ ((aligned(32))) c16_t rxdataF[ue->frame_parms.nb_antennas_rx][rxdataF_sz]; __attribute__ ((aligned(32))) c16_t rxdataF[ue->frame_parms.nb_antennas_rx][rxdataF_sz];
// checking if current frame is compatible with SSB periodicity // checking if current frame is compatible with SSB periodicity
if (cfg->ssb_table.ssb_period == 0 || if (cfg->ssb_table.ssb_period == 0 || !(frame_rx % (1 << (cfg->ssb_table.ssb_period - 1)))) {
!(frame_rx%(1<<(cfg->ssb_table.ssb_period-1)))){
const int estimateSz = fp->symbols_per_slot * fp->ofdm_symbol_size; const int estimateSz = fp->symbols_per_slot * fp->ofdm_symbol_size;
// loop over SSB blocks // loop over SSB blocks
for(int ssb_index=0; ssb_index<fp->Lmax; ssb_index++) { for(int ssb_index=0; ssb_index<fp->Lmax; ssb_index++) {
...@@ -874,9 +856,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr ...@@ -874,9 +856,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr
int ssb_slot = ssb_start_symbol/fp->symbols_per_slot; int ssb_slot = ssb_start_symbol/fp->symbols_per_slot;
int ssb_slot_2 = (cfg->ssb_table.ssb_period == 0) ? ssb_slot+(fp->slots_per_frame>>1) : -1; int ssb_slot_2 = (cfg->ssb_table.ssb_period == 0) ? ssb_slot+(fp->slots_per_frame>>1) : -1;
if (ssb_slot == nr_slot_rx || if (ssb_slot == nr_slot_rx || ssb_slot_2 == nr_slot_rx) {
ssb_slot_2 == nr_slot_rx) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP_PBCH, VCD_FUNCTION_IN); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP_PBCH, VCD_FUNCTION_IN);
LOG_D(PHY," ------ PBCH ChannelComp/LLR: frame.slot %d.%d ------ \n", frame_rx%1024, nr_slot_rx); LOG_D(PHY," ------ PBCH ChannelComp/LLR: frame.slot %d.%d ------ \n", frame_rx%1024, nr_slot_rx);
...@@ -990,7 +970,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr ...@@ -990,7 +970,7 @@ void pbch_pdcch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr
// Hold the channel estimates in frequency domain. // Hold the channel estimates in frequency domain.
int32_t pdcch_est_size = ((((fp->symbols_per_slot*(fp->ofdm_symbol_size+LTE_CE_FILTER_LENGTH))+15)/16)*16); int32_t pdcch_est_size = ((((fp->symbols_per_slot*(fp->ofdm_symbol_size+LTE_CE_FILTER_LENGTH))+15)/16)*16);
__attribute__ ((aligned(16))) int32_t pdcch_dl_ch_estimates[4*fp->nb_antennas_rx][pdcch_est_size]; __attribute__((aligned(16))) c16_t pdcch_dl_ch_estimates[4 * fp->nb_antennas_rx][pdcch_est_size];
uint8_t dci_cnt = 0; uint8_t dci_cnt = 0;
for(int n_ss = 0; n_ss<phy_pdcch_config->nb_search_space; n_ss++) { for(int n_ss = 0; n_ss<phy_pdcch_config->nb_search_space; n_ss++) {
......
...@@ -117,7 +117,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind, ...@@ -117,7 +117,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
const UE_nr_rxtx_proc_t *proc, const UE_nr_rxtx_proc_t *proc,
int32_t pdcch_est_size, int32_t pdcch_est_size,
int32_t pdcch_dl_ch_estimates[][pdcch_est_size], c16_t pdcch_dl_ch_estimates[][pdcch_est_size],
nr_phy_data_t *phy_data, nr_phy_data_t *phy_data,
int n_ss, int n_ss,
c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP]) c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
......
...@@ -497,7 +497,7 @@ int nr_ue_pusch_scheduler(const NR_UE_MAC_INST_t *mac, ...@@ -497,7 +497,7 @@ int nr_ue_pusch_scheduler(const NR_UE_MAC_INST_t *mac,
int *slot_tx, int *slot_tx,
const long k2); const long k2);
int get_rnti_type(NR_UE_MAC_INST_t *mac, uint16_t rnti); int get_rnti_type(const NR_UE_MAC_INST_t *mac, const uint16_t rnti);
// Configuration of Msg3 PDU according to clauses: // Configuration of Msg3 PDU according to clauses:
// - 8.3 of 3GPP TS 38.213 version 16.3.0 Release 16 // - 8.3 of 3GPP TS 38.213 version 16.3.0 Release 16
......
...@@ -44,7 +44,7 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss, ...@@ -44,7 +44,7 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15,
const uint32_t Y) const uint32_t Y)
{ {
LOG_D(NR_MAC,"Filling search candidates for DCI\n"); LOG_D(NR_MAC_DCI, "Filling search candidates for DCI\n");
int i = 0; int i = 0;
for (int maxL = 16; maxL > 0; maxL >>= 1) { for (int maxL = 16; maxL > 0; maxL >>= 1) {
...@@ -55,7 +55,7 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss, ...@@ -55,7 +55,7 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss,
maxL); maxL);
if (max_number_of_candidates == 0) if (max_number_of_candidates == 0)
continue; continue;
LOG_D(NR_MAC,"L %d, max number of candidates %d, aggregation %d\n", maxL, max_number_of_candidates, aggregation); LOG_D(NR_MAC_DCI, "L %d, max number of candidates %d, aggregation %d\n", maxL, max_number_of_candidates, aggregation);
int N_cce_sym = 0; // nb of rbs of coreset per symbol int N_cce_sym = 0; // nb of rbs of coreset per symbol
for (int f = 0; f < 6; f++) { for (int f = 0; f < 6; f++) {
for (int t = 0; t < 8; t++) { for (int t = 0; t < 8; t++) {
...@@ -67,13 +67,20 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss, ...@@ -67,13 +67,20 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss,
continue; continue;
for (int j = 0; j < max_number_of_candidates; j++) { for (int j = 0; j < max_number_of_candidates; j++) {
int first_cce = aggregation * ((Y + ((j * N_cces) / (aggregation * max_number_of_candidates)) + 0) % (N_cces / aggregation)); int first_cce = aggregation * ((Y + ((j * N_cces) / (aggregation * max_number_of_candidates)) + 0) % (N_cces / aggregation));
LOG_D(NR_MAC,"Candidate %d of %d first_cce %d (L %d N_cces %d Y %d)\n", j, max_number_of_candidates, first_cce, aggregation, N_cces, Y); LOG_D(NR_MAC_DCI,
"Candidate %d of %d first_cce %d (L %d N_cces %d Y %d)\n",
j,
max_number_of_candidates,
first_cce,
aggregation,
N_cces,
Y);
// to avoid storing more than one candidate with the same aggregation and starting CCE (duplicated candidate) // to avoid storing more than one candidate with the same aggregation and starting CCE (duplicated candidate)
bool duplicated = false; bool duplicated = false;
for (int k = 0; k < i; k++) { for (int k = 0; k < i; k++) {
if (rel15->CCE[k] == first_cce && rel15->L[k] == aggregation) { if (rel15->CCE[k] == first_cce && rel15->L[k] == aggregation) {
duplicated = true; duplicated = true;
LOG_D(NR_MAC, "Candidate %d of %d is duplicated\n", j, max_number_of_candidates); LOG_D(NR_MAC_DCI, "Candidate %d of %d is duplicated\n", j, max_number_of_candidates);
} }
} }
if (!duplicated) { if (!duplicated) {
...@@ -296,7 +303,9 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, ...@@ -296,7 +303,9 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
#ifdef DEBUG_DCI #ifdef DEBUG_DCI
for (int i = 0; i < rel15->num_dci_options; i++) { for (int i = 0; i < rel15->num_dci_options; i++) {
LOG_D(MAC, "[DCI_CONFIG] Configure DCI PDU: rnti_type %d BWPSize %d BWPStart %d rel15->SubcarrierSpacing %d rel15->dci_format %d rel15->dci_length %d sps %d monitoringSymbolsWithinSlot %d \n", LOG_D(NR_MAC_DCI,
"[DCI_CONFIG] Configure DCI PDU: rnti_type %d BWPSize %d BWPStart %d rel15->SubcarrierSpacing %d rel15->dci_format %d "
"rel15->dci_length %d sps %d monitoringSymbolsWithinSlot %d \n",
rnti_type, rnti_type,
rel15->BWPSize, rel15->BWPSize,
rel15->BWPStart, rel15->BWPStart,
...@@ -490,7 +499,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl ...@@ -490,7 +499,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
fill_coresetZero(mac->coreset0, &mac->type0_PDCCH_CSS_config); fill_coresetZero(mac->coreset0, &mac->type0_PDCCH_CSS_config);
fill_searchSpaceZero(mac->search_space_zero, slots_per_frame, &mac->type0_PDCCH_CSS_config); fill_searchSpaceZero(mac->search_space_zero, slots_per_frame, &mac->type0_PDCCH_CSS_config);
if (is_ss_monitor_occasion(frame, slot, slots_per_frame, mac->search_space_zero)) { if (is_ss_monitor_occasion(frame, slot, slots_per_frame, mac->search_space_zero)) {
LOG_D(NR_MAC, "Monitoring DCI for SIB1 in frame %d slot %d\n", frame, slot); LOG_D(NR_MAC_DCI, "Monitoring DCI for SIB1 in frame %d slot %d\n", frame, slot);
config_dci_pdu(mac, dl_config, TYPE_SI_RNTI_, slot, mac->search_space_zero); config_dci_pdu(mac, dl_config, TYPE_SI_RNTI_, slot, mac->search_space_zero);
} }
} }
...@@ -501,7 +510,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl ...@@ -501,7 +510,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
const NR_SearchSpace_t *ss = pdcch_config->otherSI_SS ? pdcch_config->otherSI_SS : mac->search_space_zero; const NR_SearchSpace_t *ss = pdcch_config->otherSI_SS ? pdcch_config->otherSI_SS : mac->search_space_zero;
// TODO configure SI-window // TODO configure SI-window
if (monitior_dci_for_other_SI(mac, ss, slots_per_frame, frame, slot)) { if (monitior_dci_for_other_SI(mac, ss, slots_per_frame, frame, slot)) {
LOG_D(NR_MAC, "Monitoring DCI for other SIs in frame %d slot %d\n", frame, slot); LOG_D(NR_MAC_DCI, "Monitoring DCI for other SIs in frame %d slot %d\n", frame, slot);
config_dci_pdu(mac, dl_config, TYPE_SI_RNTI_, slot, ss); config_dci_pdu(mac, dl_config, TYPE_SI_RNTI_, slot, ss);
} }
} }
......
...@@ -58,11 +58,9 @@ ...@@ -58,11 +58,9 @@
#include "common/utils/LOG/log.h" #include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h" #include "common/utils/LOG/vcd_signal_dumper.h"
//#define DEBUG_MIB // #define DEBUG_MIB
//#define ENABLE_MAC_PAYLOAD_DEBUG 1 // #define ENABLE_MAC_PAYLOAD_DEBUG 1
//#define DEBUG_EXTRACT_DCI // #define DEBUG_RAR
//#define DEBUG_RAR
extern uint32_t N_RB_DL; extern uint32_t N_RB_DL;
/* TS 38.213 9.2.5.2 UE procedure for multiplexing HARQ-ACK/SR and CSI in a PUCCH */ /* TS 38.213 9.2.5.2 UE procedure for multiplexing HARQ-ACK/SR and CSI in a PUCCH */
...@@ -165,33 +163,32 @@ const initial_pucch_resource_t initial_pucch_resource[16] = { ...@@ -165,33 +163,32 @@ const initial_pucch_resource_t initial_pucch_resource[16] = {
/* 15 */ { 1, 0, 14, 0, 4, { 0, 3, 6, 9 } }, /* 15 */ { 1, 0, 14, 0, 4, { 0, 3, 6, 9 } },
}; };
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nr_dci_format_t dci_format, const nr_dci_format_t dci_format,
uint8_t dci_size, const uint8_t dci_size,
uint16_t rnti, const uint16_t rnti,
int ss_type, const int ss_type,
uint64_t *dci_pdu, const uint8_t *dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int slot); const int slot);
int get_rnti_type(NR_UE_MAC_INST_t *mac, uint16_t rnti) int get_rnti_type(const NR_UE_MAC_INST_t *mac, const uint16_t rnti)
{ {
const RA_config_t *ra = &mac->ra;
RA_config_t *ra = &mac->ra; nr_rnti_type_t rnti_type;
nr_rnti_type_t rnti_type;
if (rnti == ra->ra_rnti) {
if (rnti == ra->ra_rnti) { rnti_type = TYPE_RA_RNTI_;
rnti_type = TYPE_RA_RNTI_; } else if (rnti == ra->t_crnti && (ra->ra_state == WAIT_RAR || ra->ra_state == WAIT_CONTENTION_RESOLUTION)) {
} else if (rnti == ra->t_crnti && (ra->ra_state == WAIT_RAR || ra->ra_state == WAIT_CONTENTION_RESOLUTION) ) { rnti_type = TYPE_TC_RNTI_;
rnti_type = TYPE_TC_RNTI_; } else if (rnti == mac->crnti) {
} else if (rnti == mac->crnti) { rnti_type = TYPE_C_RNTI_;
rnti_type = TYPE_C_RNTI_; } else if (rnti == 0xFFFE) {
} else if (rnti == 0xFFFE) { rnti_type = TYPE_P_RNTI_;
rnti_type = TYPE_P_RNTI_; } else if (rnti == 0xFFFF) {
} else if (rnti == 0xFFFF) { rnti_type = TYPE_SI_RNTI_;
rnti_type = TYPE_SI_RNTI_; } else {
} else { AssertFatal(1 == 0, "Not identified/handled rnti %d \n", rnti);
AssertFatal(1 == 0, "Not identified/handled rnti %d \n", rnti); }
}
LOG_D(MAC, "Returning rnti_type %s \n", rnti_types(rnti_type)); LOG_D(MAC, "Returning rnti_type %s \n", rnti_types(rnti_type));
...@@ -377,9 +374,21 @@ int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac, ...@@ -377,9 +374,21 @@ int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac,
{ {
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format]; dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format];
LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n", LOG_D(MAC,
dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits); "Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
const int ret = nr_extract_dci_info(mac, dci->dci_format, dci->payloadSize, dci->rnti, dci->ss_type, (uint64_t *)dci->payloadBits, def_dci_pdu_rel15, slot); dci->rnti,
dci->dci_format,
dci->n_CCE,
dci->payloadSize,
*(unsigned long long *)dci->payloadBits);
const int ret = nr_extract_dci_info(mac,
dci->dci_format,
dci->payloadSize,
dci->rnti,
dci->ss_type,
dci->payloadBits,
def_dci_pdu_rel15,
slot);
if ((ret & 1) == 1) if ((ret & 1) == 1)
return -1; return -1;
else if (ret == 2) { else if (ret == 2) {
...@@ -1359,10 +1368,11 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac, ...@@ -1359,10 +1368,11 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac,
// only for ack/nack // only for ack/nack
if (pucch->initial_pucch_id > -1 && if (pucch->initial_pucch_id > -1 &&
pucch->pucch_resource == NULL) { pucch->pucch_resource == NULL) {
int pucch_resourcecommon = *current_UL_BWP->pucch_ConfigCommon->pucch_ResourceCommon; const int idx = *current_UL_BWP->pucch_ConfigCommon->pucch_ResourceCommon;
pucch_pdu->format_type = initial_pucch_resource[pucch_resourcecommon].format; const initial_pucch_resource_t pucch_resourcecommon = initial_pucch_resource[idx];
pucch_pdu->start_symbol_index = initial_pucch_resource[pucch_resourcecommon].startingSymbolIndex; pucch_pdu->format_type = pucch_resourcecommon.format;
pucch_pdu->nr_of_symbols = initial_pucch_resource[pucch_resourcecommon].nrofSymbols; pucch_pdu->start_symbol_index = pucch_resourcecommon.startingSymbolIndex;
pucch_pdu->nr_of_symbols = pucch_resourcecommon.nrofSymbols;
pucch_pdu->bwp_size = current_UL_BWP->BWPSize; pucch_pdu->bwp_size = current_UL_BWP->BWPSize;
pucch_pdu->bwp_start = current_UL_BWP->BWPStart; pucch_pdu->bwp_start = current_UL_BWP->BWPStart;
...@@ -1372,18 +1382,20 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac, ...@@ -1372,18 +1382,20 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac,
if (pucch->initial_pucch_id == 15) if (pucch->initial_pucch_id == 15)
RB_BWP_offset = pucch_pdu->bwp_size >> 2; RB_BWP_offset = pucch_pdu->bwp_size >> 2;
else else
RB_BWP_offset = initial_pucch_resource[pucch_resourcecommon].PRB_offset; RB_BWP_offset = pucch_resourcecommon.PRB_offset;
int N_CS = initial_pucch_resource[pucch_resourcecommon].nb_CS_indexes; int N_CS = pucch_resourcecommon.nb_CS_indexes;
if (pucch->initial_pucch_id >> 3 == 0) { if (pucch->initial_pucch_id >> 3 == 0) {
pucch_pdu->prb_start = RB_BWP_offset + (pucch->initial_pucch_id / N_CS); const int tmp = pucch->initial_pucch_id / N_CS;
pucch_pdu->second_hop_prb = pucch_pdu->bwp_size - 1 - RB_BWP_offset - (pucch->initial_pucch_id / N_CS); pucch_pdu->prb_start = RB_BWP_offset + tmp;
pucch_pdu->initial_cyclic_shift = initial_pucch_resource[pucch_resourcecommon].initial_CS_indexes[pucch->initial_pucch_id % N_CS]; pucch_pdu->second_hop_prb = pucch_pdu->bwp_size - 1 - RB_BWP_offset - tmp;
pucch_pdu->initial_cyclic_shift = pucch_resourcecommon.initial_CS_indexes[pucch->initial_pucch_id % N_CS];
} else { } else {
pucch_pdu->prb_start = pucch_pdu->bwp_size - 1 - RB_BWP_offset - ((pucch->initial_pucch_id - 8) / N_CS); const int tmp = (pucch->initial_pucch_id - 8) / N_CS;
pucch_pdu->second_hop_prb = RB_BWP_offset + ((pucch->initial_pucch_id - 8) / N_CS); pucch_pdu->prb_start = pucch_pdu->bwp_size - 1 - RB_BWP_offset - tmp;
pucch_pdu->initial_cyclic_shift = initial_pucch_resource[pucch_resourcecommon].initial_CS_indexes[(pucch->initial_pucch_id - 8) % N_CS]; pucch_pdu->second_hop_prb = RB_BWP_offset + tmp;
pucch_pdu->initial_cyclic_shift = pucch_resourcecommon.initial_CS_indexes[(pucch->initial_pucch_id - 8) % N_CS];
} }
pucch_pdu->freq_hop_flag = 1; pucch_pdu->freq_hop_flag = 1;
pucch_pdu->time_domain_occ_idx = 0; pucch_pdu->time_domain_occ_idx = 0;
...@@ -1408,12 +1420,14 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac, ...@@ -1408,12 +1420,14 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac,
NR_PUSCH_Config_t *pusch_Config = current_UL_BWP ? current_UL_BWP->pusch_Config : NULL; NR_PUSCH_Config_t *pusch_Config = current_UL_BWP ? current_UL_BWP->pusch_Config : NULL;
if (pusch_Config) { if (pusch_Config) {
pusch_id = pusch_Config->dataScramblingIdentityPUSCH; pusch_id = pusch_Config->dataScramblingIdentityPUSCH;
if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL && struct NR_SetupRelease_DMRS_UplinkConfig *tmp = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA;
pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup->transformPrecodingDisabled != NULL) if (tmp && tmp->choice.setup->transformPrecodingDisabled != NULL)
id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup->transformPrecodingDisabled->scramblingID0; id0 = tmp->choice.setup->transformPrecodingDisabled->scramblingID0;
else if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL && else {
pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup->transformPrecodingDisabled != NULL) struct NR_SetupRelease_DMRS_UplinkConfig *tmp = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB;
id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup->transformPrecodingDisabled->scramblingID0; if (tmp && tmp->choice.setup->transformPrecodingDisabled != NULL)
id0 = tmp->choice.setup->transformPrecodingDisabled->scramblingID0;
}
} }
NR_PUCCH_Config_t *pucch_Config = current_UL_BWP->pucch_Config; NR_PUCCH_Config_t *pucch_Config = current_UL_BWP->pucch_Config;
...@@ -2881,21 +2895,33 @@ void nr_ue_send_sdu(NR_UE_MAC_INST_t *mac, nr_downlink_indication_t *dl_info, in ...@@ -2881,21 +2895,33 @@ void nr_ue_send_sdu(NR_UE_MAC_INST_t *mac, nr_downlink_indication_t *dl_info, in
} }
// #define EXTRACT_DCI_ITEM(val,size) val= readBits(dci_pdu, &pos, size);
#define EXTRACT_DCI_ITEM(val, size) \
val = readBits(dci_pdu, &pos, size); \
LOG_D(NR_MAC_DCI, " " #val ": %d\n", val);
// Fixme: Intel Endianess only procedure
static inline int readBits(const uint8_t *dci, int *start, int length)
{
const int mask[] = {0, 1, 3, 7, 0xf, 0x1f, 0x3f, 0x7f, 0xff, 0x1ff, 0x3ff, 0x7ff, 0xfff, 0x1fff, 0x3fff, 0x7fff, 0xffff};
uint64_t *tmp = (uint64_t *)dci;
*start -= length;
return *tmp >> *start & mask[length];
}
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nr_dci_format_t dci_format, const nr_dci_format_t dci_format,
uint8_t dci_size, const uint8_t dci_size,
uint16_t rnti, const uint16_t rnti,
int ss_type, const int ss_type,
uint64_t *dci_pdu, const uint8_t *dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int slot) const int slot)
{ {
LOG_D(MAC,"nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *dci_pdu, dci_size, dci_format); LOG_D(NR_MAC, "nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *(uint64_t *)dci_pdu, dci_size, dci_format);
int pos = 0; const int rnti_type = get_rnti_type(mac, rnti);
int fsize = 0; const NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
int rnti_type = get_rnti_type(mac, rnti); const NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
int N_RB; int N_RB;
if(current_DL_BWP) if(current_DL_BWP)
N_RB = get_rb_bwp_dci(dci_format, N_RB = get_rb_bwp_dci(dci_format,
...@@ -2912,173 +2938,82 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -2912,173 +2938,82 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
LOG_E(MAC, "DCI configuration error! N_RB = 0\n"); LOG_E(MAC, "DCI configuration error! N_RB = 0\n");
return 1; return 1;
} }
int pos = dci_size;
switch(dci_format) { switch(dci_format) {
case NR_DL_DCI_FORMAT_1_0: case NR_DL_DCI_FORMAT_1_0:
switch(rnti_type) { switch(rnti_type) {
case TYPE_RA_RNTI_: case TYPE_RA_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 RA rnti\n");
// Freq domain assignment // Freq domain assignment
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
pos = fsize; // Time domain assignment
dci_pdu_rel15->frequency_domain_assignment.val = *dci_pdu >> (dci_size - pos) & ((1 << fsize) - 1); EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
#ifdef DEBUG_EXTRACT_DCI // VRB to PRB mapping
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu); EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
#endif // MCS
// Time domain assignment EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
pos+=4; // TB scaling
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->tb_scaling, 2);
#ifdef DEBUG_EXTRACT_DCI break;
LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
#endif
// VRB to PRB mapping
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&0x1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
#endif
// MCS
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
#endif
// TB scaling
pos+=2;
dci_pdu_rel15->tb_scaling = (*dci_pdu>>(dci_size-pos))&0x3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
#endif
break;
case TYPE_C_RNTI_: case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 C rnti\n");
// Identifier for DCI formats // Identifier for DCI formats
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
// switch to DCI_0_0 // switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) { if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0]; dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
LOG_D(NR_MAC_DCI, "received dci 1_0 c_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot); return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
} }
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16) // Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1); bool is_ra = true;
for (int i = 0; i < dci_pdu_rel15->frequency_domain_assignment.val; i++)
#ifdef DEBUG_EXTRACT_DCI if (!((dci_pdu_rel15->frequency_domain_assignment.val >> i) & 1)) {
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); is_ra = false;
#endif break;
}
uint16_t is_ra = 1; if (is_ra) // fsize are all 1 38.212 p86
for (int i=0; i<fsize; i++) {
if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) { // ra_preamble_index 6 bits
is_ra = 0; EXTRACT_DCI_ITEM(dci_pdu_rel15->ra_preamble_index, 6);
break; // UL/SUL indicator 1 bit
} EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, 1);
if (is_ra) //fsize are all 1 38.212 p86 // SS/PBCH index 6 bits
{ EXTRACT_DCI_ITEM(dci_pdu_rel15->ss_pbch_index, 6);
// ra_preamble_index 6 bits // prach_mask_index 4 bits
pos+=6; EXTRACT_DCI_ITEM(dci_pdu_rel15->prach_mask_index, 4);
dci_pdu_rel15->ra_preamble_index = (*dci_pdu>>(dci_size-pos))&0x3f; } else {
// Time domain assignment 4bit
// UL/SUL indicator 1 bit EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
pos++; // VRB to PRB mapping 1bit
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&1; EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit //bit over 32, so dci_pdu ++
// SS/PBCH index 6 bits EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
pos+=6; // New data indicator 1bit
dci_pdu_rel15->ss_pbch_index = (*dci_pdu>>(dci_size-pos))&0x3f; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
// prach_mask_index 4 bits EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
pos+=4; // HARQ process number 4bit
dci_pdu_rel15->prach_mask_index = (*dci_pdu>>(dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index 2bit
} //end if EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
else { // TPC command for scheduled PUCCH 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// Time domain assignment 4bit // PUCCH resource indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
pos+=4; // PDSCH-to-HARQ_feedback timing indicator 3bit
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
#ifdef DEBUG_EXTRACT_DCI }
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu); break;
#endif
// VRB to PRB mapping 1bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
#endif
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// Downlink assignment index 2bit
pos+=2;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUCCH 2bit
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
#endif
// PUCCH resource indicator 3bit
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x7;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu);
#endif
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&0x7;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
#endif
} //end else
break;
case TYPE_P_RNTI_: case TYPE_P_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 P rnti\n");
/* /*
// Short Messages Indicator  E2 bits // Short Messages Indicator  E2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
...@@ -3107,340 +3042,197 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -3107,340 +3042,197 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
break; break;
case TYPE_SI_RNTI_: case TYPE_SI_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 SI rnti\n");
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
// Time domain assignment 4 bit // Time domain assignment 4 bit
pos += 4; EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 0x1; // MCS 5bit //bit over 32
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// MCS 5bit //bit over 32, so dci_pdu ++
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// Redundancy version 2 bit // Redundancy version 2 bit
pos += 2; EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
// System information indicator 1 bit // System information indicator 1 bit
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->system_info_indicator, 1);
dci_pdu_rel15->system_info_indicator = (*dci_pdu >> (dci_size - pos)) & 0x1;
LOG_D(MAC, "N_RB = %i\n", N_RB);
LOG_D(MAC, "dci_size = %i\n", dci_size);
LOG_D(MAC, "fsize = %i\n", fsize);
LOG_D(MAC, "dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(MAC, "dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(MAC, "dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(MAC, "dci_pdu_rel15->system_info_indicator = %i\n", dci_pdu_rel15->system_info_indicator);
break; break;
case TYPE_TC_RNTI_: case TYPE_TC_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
// switch to DCI_0_0 // switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) { if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0]; dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
LOG_D(NR_MAC_DCI, "received dci 1_0 tc_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot); return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
} }
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
pos+=fsize; // Time domain assignment - 4 bits
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1); EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping - 1 bit
// Time domain assignment - 4 bits EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
pos+=4; // MCS 5bit
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator - 1 bit
// VRB to PRB mapping - 1 bit EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
pos++; // Redundancy version - 2 bits
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1; EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number - 4 bits
// MCS 5bit //bit over 32, so dci_pdu ++ EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
pos+=5; // Downlink assignment index - 2 bits
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
// TPC command for scheduled PUCCH - 2 bits
// New data indicator - 1 bit EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
pos++; // PUCCH resource indicator - 3 bits
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1; EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
// Redundancy version - 2 bits EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
pos+=2; break;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3; default:
LOG_W(NR_MAC_DCI, "Received dci 1_0 unknown rnti type: %d\n", rnti_type);
// HARQ process number - 4 bits
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index - 2 bits
pos+=2;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
// TPC command for scheduled PUCCH - 2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// PUCCH resource indicator - 3 bits
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&7;
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
pos+=3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7;
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->format_indicator = %i\n", dci_pdu_rel15->format_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->dai[0].val = %i\n", dci_pdu_rel15->dai[0].val);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->pucch_resource_indicator = %i\n", dci_pdu_rel15->pucch_resource_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = %i\n", dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val);
break;
} }
break; break;
case NR_UL_DCI_FORMAT_0_0: case NR_UL_DCI_FORMAT_0_0:
switch(rnti_type) switch(rnti_type)
{ {
case TYPE_C_RNTI_: case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 0_0 C rnti\n");
// Identifier for DCI formats // Identifier for DCI formats
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
#endif
if (dci_pdu_rel15->format_indicator == 1) if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format return 1; // discard dci, format indicator not corresponding to dci_format
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
pos+=fsize; // Time domain assignment 4bit
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1); EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
#ifdef DEBUG_EXTRACT_DCI // Frequency hopping flag  E1 bit
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
#endif // MCS 5 bit
// Time domain assignment 4bit EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
pos+=4; // New data indicator 1bit
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
#ifdef DEBUG_EXTRACT_DCI // Redundancy version 2bit
LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
#endif // HARQ process number 4bit
// Frequency hopping flag  E1 bit EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
pos++; // TPC command for scheduled PUSCH  E2 bits
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1; EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
#ifdef DEBUG_EXTRACT_DCI // UL/SUL indicator  E1 bit
LOG_D(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu); /* commented for now (RK): need to get this from BWP descriptor
#endif if (cfg->pucch_config.pucch_GroupHopping.value)
// MCS 5 bit dci_pdu->= ((uint64_t)readBits(dci_pdu,>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
pos+=5; */
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f; break;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
#endif
// UL/SUL indicator  E1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break;
case TYPE_TC_RNTI_: case TYPE_TC_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
// Identifier for DCI formats // Identifier for DCI formats
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
#endif
//switch to DCI_1_0 //switch to DCI_1_0
if (dci_pdu_rel15->format_indicator == 1) { if (dci_pdu_rel15->format_indicator == 1) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_DL_DCI_FORMAT_1_0]; dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_DL_DCI_FORMAT_1_0];
LOG_D(NR_MAC_DCI, "received dci 0_0 tc_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_DL_DCI_FORMAT_1_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot); return 2 + nr_extract_dci_info(mac, NR_DL_DCI_FORMAT_1_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
} }
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
pos+=fsize; // Time domain assignment 4bit
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1); EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
#ifdef DEBUG_EXTRACT_DCI // Frequency hopping flag  E1 bit
LOG_I(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
#endif // MCS 5 bit
// Time domain assignment 4bit EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
pos+=4; // New data indicator 1bit
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
#ifdef DEBUG_EXTRACT_DCI // Redundancy version 2bit
LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
#endif // HARQ process number 4bit
// Frequency hopping flag  E1 bit EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
pos++; // TPC command for scheduled PUSCH  E2 bits
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1; EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
#ifdef DEBUG_EXTRACT_DCI break;
LOG_I(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu);
#endif default:
// MCS 5 bit LOG_W(NR_MAC_DCI, "Received dci 0_0 unknown rnti type: %d\n", rnti_type);
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
#endif
break;
} }
break; break;
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
switch(rnti_type) switch(rnti_type)
{ {
case TYPE_C_RNTI_: case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_1 C rnti\n");
// Identifier for DCI formats // Identifier for DCI formats
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1; if (dci_pdu_rel15->format_indicator == 0) {
if (dci_pdu_rel15->format_indicator == 0) LOG_W(NR_MAC_DCI, "Received dci 1_1 C rnti and format indicator 0, discarding\n");
return 1; // discard dci, format indicator not corresponding to dci_format return 1; // discard dci, format indicator not corresponding to dci_format
}
// Carrier indicator // Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits;
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1); EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits);
// BWP Indicator // BWP Indicator&
pos+=dci_pdu_rel15->bwp_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits);
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1);
// Frequency domain resource assignment // Frequency domain resource assignment
pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1);
// Time domain resource assignment // Time domain resource assignment
pos+=dci_pdu_rel15->time_domain_assignment.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1);
// VRB-to-PRB mapping // VRB-to-PRB mapping
pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, dci_pdu_rel15->vrb_to_prb_mapping.nbits);
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1);
// PRB bundling size indicator // PRB bundling size indicator
pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->prb_bundling_size_indicator.val, dci_pdu_rel15->prb_bundling_size_indicator.nbits);
dci_pdu_rel15->prb_bundling_size_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1);
// Rate matching indicator // Rate matching indicator
pos+=dci_pdu_rel15->rate_matching_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->rate_matching_indicator.val, dci_pdu_rel15->rate_matching_indicator.nbits);
dci_pdu_rel15->rate_matching_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1);
// ZP CSI-RS trigger // ZP CSI-RS trigger
pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->zp_csi_rs_trigger.val, dci_pdu_rel15->zp_csi_rs_trigger.nbits);
dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1); // TB1
//TB1 // MCS 5bit
// MCS 5bit EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator 1bit // New data indicator 1bit
pos+=1; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&0x1;
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
//TB2 //TB2
// MCS 5bit // MCS 5bit
pos+=dci_pdu_rel15->mcs2.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs2.val, dci_pdu_rel15->mcs2.nbits);
dci_pdu_rel15->mcs2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->mcs2.nbits)-1);
// New data indicator 1bit // New data indicator 1bit
pos+=dci_pdu_rel15->ndi2.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi2.val, dci_pdu_rel15->ndi2.nbits);
dci_pdu_rel15->ndi2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ndi2.nbits)-1);
// Redundancy version 2bit // Redundancy version 2bit
pos+=dci_pdu_rel15->rv2.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->rv2.val, dci_pdu_rel15->rv2.nbits);
dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rv2.nbits)-1);
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index // Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&0x3;
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x3;
// PDSCH-to-HARQ_feedback timing indicator // PDSCH-to-HARQ_feedback timing indicator
pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1); dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits);
// Antenna ports // Antenna ports
pos+=dci_pdu_rel15->antenna_ports.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->antenna_ports.nbits)-1);
// TCI // TCI
pos+=dci_pdu_rel15->transmission_configuration_indication.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->transmission_configuration_indication.val,
dci_pdu_rel15->transmission_configuration_indication.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1); dci_pdu_rel15->transmission_configuration_indication.nbits);
// SRS request // SRS request
pos+=dci_pdu_rel15->srs_request.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_request.nbits)-1);
// CBG transmission information // CBG transmission information
pos+=dci_pdu_rel15->cbgti.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgti.nbits)-1);
// CBG flushing out information // CBG flushing out information
pos+=dci_pdu_rel15->cbgfi.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgfi.val, dci_pdu_rel15->cbgfi.nbits);
dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgfi.nbits)-1);
// DMRS sequence init // DMRS sequence init
pos+=1; EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, 1);
dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&0x1;
break; break;
default:
LOG_W(NR_MAC_DCI, "Received dci 1_1 unknown rnti type: %d\n", rnti_type);
} }
break; break;
...@@ -3448,105 +3240,63 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -3448,105 +3240,63 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
switch(rnti_type) switch(rnti_type)
{ {
case TYPE_C_RNTI_: case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 0_1 C rnti\n");
//Identifier for DCI formats //Identifier for DCI formats
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; if (dci_pdu_rel15->format_indicator == 1) {
if (dci_pdu_rel15->format_indicator == 1) LOG_W(NR_MAC_DCI, "Received dci 0_1 C rnti and format indicator 1, discarding\n");
return 1; // discard dci, format indicator not corresponding to dci_format return 1; // discard dci, format indicator not corresponding to dci_format
}
// Carrier indicator // Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits);
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1);
// UL/SUL Indicator // UL/SUL Indicator
pos+=dci_pdu_rel15->ul_sul_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, dci_pdu_rel15->ul_sul_indicator.nbits);
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ul_sul_indicator.nbits)-1);
// BWP Indicator // BWP Indicator
pos+=dci_pdu_rel15->bwp_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits);
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment // Time domain assignment
//pos+=4; EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
pos+=dci_pdu_rel15->time_domain_assignment.nbits;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1);
// Not supported yet - skip for now // Not supported yet - skip for now
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
//pos++; // pos++;
//dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1; // dci_pdu_rel15->frequency_hopping_flag.val= (readBits(dci_pdu,>>(dci_size-pos))&1;
// MCS 5 bit // MCS 5 bit
pos+=5; EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator 1bit // New data indicator 1bit
pos++; EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// 1st Downlink assignment index // 1st Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
// 2nd Downlink assignment index // 2nd Downlink assignment index
pos+=dci_pdu_rel15->dai[1].nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[1].val, dci_pdu_rel15->dai[1].nbits);
dci_pdu_rel15->dai[1].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[1].nbits)-1);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
pos+=2; EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// SRS resource indicator // SRS resource indicator
pos+=dci_pdu_rel15->srs_resource_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_resource_indicator.val, dci_pdu_rel15->srs_resource_indicator.nbits);
dci_pdu_rel15->srs_resource_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_resource_indicator.nbits)-1);
// Precoding info and n. of layers // Precoding info and n. of layers
pos+=dci_pdu_rel15->precoding_information.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->precoding_information.val, dci_pdu_rel15->precoding_information.nbits);
dci_pdu_rel15->precoding_information.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->precoding_information.nbits)-1);
// Antenna ports // Antenna ports
pos+=dci_pdu_rel15->antenna_ports.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->antenna_ports.nbits)-1);
// SRS request // SRS request
pos+=dci_pdu_rel15->srs_request.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_request.nbits)-1);
// CSI request // CSI request
pos+=dci_pdu_rel15->csi_request.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->csi_request.val, dci_pdu_rel15->csi_request.nbits);
dci_pdu_rel15->csi_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->csi_request.nbits)-1);
// CBG transmission information // CBG transmission information
pos+=dci_pdu_rel15->cbgti.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgti.nbits)-1);
// PTRS DMRS association // PTRS DMRS association
pos+=dci_pdu_rel15->ptrs_dmrs_association.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->ptrs_dmrs_association.val, dci_pdu_rel15->ptrs_dmrs_association.nbits);
dci_pdu_rel15->ptrs_dmrs_association.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ptrs_dmrs_association.nbits)-1);
// Beta offset indicator // Beta offset indicator
pos+=dci_pdu_rel15->beta_offset_indicator.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->beta_offset_indicator.val, dci_pdu_rel15->beta_offset_indicator.nbits);
dci_pdu_rel15->beta_offset_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->beta_offset_indicator.nbits)-1);
// DMRS sequence initialization // DMRS sequence initialization
pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, dci_pdu_rel15->dmrs_sequence_initialization.nbits);
dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dmrs_sequence_initialization.nbits)-1);
// UL-SCH indicator // UL-SCH indicator
pos+=1; EXTRACT_DCI_ITEM(dci_pdu_rel15->ulsch_indicator, 1);
dci_pdu_rel15->ulsch_indicator = (*dci_pdu>>(dci_size-pos))&0x1;
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor /* commented for now (RK): need to get this from BWP descriptor
...@@ -3554,10 +3304,14 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -3554,10 +3304,14 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++); dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/ */
break; break;
default:
LOG_W(NR_MAC_DCI, "Received dci 0_1 unknown rnti type: %d\n", rnti_type);
} }
break; break;
default: // other DCI formats default: // other DCI formats
LOG_W(NR_MAC_DCI, "Received dci unknown format type: %d\n", dci_format);
break; break;
} }
......
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