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OpenXG-RAN
Commits
ce2dd17e
Commit
ce2dd17e
authored
Sep 22, 2020
by
Robert Schmidt
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Post-processor: enable multi-UE handling
parent
fdb4c692
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1
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168 additions
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168 deletions
+168
-168
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+168
-168
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
ce2dd17e
...
...
@@ -548,193 +548,193 @@ void nr_schedule_ue_spec(module_id_t module_id,
frame_t
frame
,
sub_frame_t
slot
,
int
num_slots_per_tdd
)
{
gNB_MAC_INST
*
gNB_mac
=
RC
.
nrmac
[
module_id
];
NR_UE_info_t
*
UE_info
=
&
gNB_mac
->
UE_info
;
if
(
UE_info
->
num_UEs
==
0
)
return
;
/* PREPROCESSOR */
nr_simple_dlsch_preprocessor
(
module_id
,
frame
,
slot
,
num_slots_per_tdd
);
gNB_MAC_INST
*
gNB_mac
=
RC
.
nrmac
[
module_id
];
NR_UE_info_t
*
UE_info
=
&
gNB_mac
->
UE_info
;
const
int
ta_len
=
gNB_mac
->
ta_len
;
const
int
UE_id
=
0
;
const
int
CC_id
=
0
;
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
if
(
sched_ctrl
->
rbSize
<
0
&&
!
get_softmodem_params
()
->
phy_test
)
return
;
/* POST processing */
struct
NR_PDSCH_TimeDomainResourceAllocationList
*
tdaList
=
sched_ctrl
->
active_bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
AssertFatal
(
sched_ctrl
->
time_domain_allocation
<
tdaList
->
list
.
count
,
"time_domain_allocation %d>=%d
\n
"
,
sched_ctrl
->
time_domain_allocation
,
tdaList
->
list
.
count
);
const
int
startSymbolAndLength
=
tdaList
->
list
.
array
[
sched_ctrl
->
time_domain_allocation
]
->
startSymbolAndLength
;
int
startSymbolIndex
,
nrOfSymbols
;
SLIV2SL
(
startSymbolAndLength
,
&
startSymbolIndex
,
&
nrOfSymbols
);
uint8_t
N_PRB_DMRS
=
getN_PRB_DMRS
(
sched_ctrl
->
active_bwp
,
sched_ctrl
->
numDmrsCdmGrpsNoData
);
const
uint32_t
TBS
=
nr_compute_tbs
(
nr_get_Qm_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
nr_get_code_rate_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
sched_ctrl
->
rbSize
,
nrOfSymbols
,
N_PRB_DMRS
,
// FIXME // This should be multiplied by the
// number of dmrs symbols
0
/* N_PRB_oh, 0 for initialBWP */
,
0
/* tb_scaling */
,
1
/* nrOfLayers */
)
>>
3
;
/* Get RLC data TODO: remove random data retrieval */
int
header_length_total
=
0
;
int
header_length_last
=
0
;
int
sdu_length_total
=
0
;
int
num_sdus
=
0
;
uint16_t
sdu_lengths
[
NB_RB_MAX
]
=
{
0
};
uint8_t
mac_sdus
[
MAX_NR_DLSCH_PAYLOAD_BYTES
];
unsigned
char
sdu_lcids
[
NB_RB_MAX
]
=
{
0
};
const
rnti_t
rnti
=
UE_info
->
rnti
[
UE_id
];
const
int
lcid
=
DL_SCH_LCID_DTCH
;
if
(
sched_ctrl
->
num_total_bytes
>
0
)
{
LOG_D
(
MAC
,
"[gNB %d][USER-PLANE DEFAULT DRB] Frame %d : DTCH->DLSCH, Requesting "
"%d bytes from RLC (lcid %d total hdr len %d), TBS: %d
\n
\n
"
,
NR_UE_list_t
*
UE_list
=
&
UE_info
->
list
;
for
(
int
UE_id
=
UE_list
->
head
;
UE_id
>=
0
;
UE_id
=
UE_list
->
next
[
UE_id
])
{
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
if
(
sched_ctrl
->
rbSize
<=
0
&&
!
get_softmodem_params
()
->
phy_test
)
continue
;
/* POST processing */
struct
NR_PDSCH_TimeDomainResourceAllocationList
*
tdaList
=
sched_ctrl
->
active_bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
AssertFatal
(
sched_ctrl
->
time_domain_allocation
<
tdaList
->
list
.
count
,
"time_domain_allocation %d>=%d
\n
"
,
sched_ctrl
->
time_domain_allocation
,
tdaList
->
list
.
count
);
const
int
startSymbolAndLength
=
tdaList
->
list
.
array
[
sched_ctrl
->
time_domain_allocation
]
->
startSymbolAndLength
;
int
startSymbolIndex
,
nrOfSymbols
;
SLIV2SL
(
startSymbolAndLength
,
&
startSymbolIndex
,
&
nrOfSymbols
);
uint8_t
N_PRB_DMRS
=
getN_PRB_DMRS
(
sched_ctrl
->
active_bwp
,
sched_ctrl
->
numDmrsCdmGrpsNoData
);
const
uint32_t
TBS
=
nr_compute_tbs
(
nr_get_Qm_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
nr_get_code_rate_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
sched_ctrl
->
rbSize
,
nrOfSymbols
,
N_PRB_DMRS
,
// FIXME // This should be multiplied by the
// number of dmrs symbols
0
/* N_PRB_oh, 0 for initialBWP */
,
0
/* tb_scaling */
,
1
/* nrOfLayers */
)
>>
3
;
/* Get RLC data TODO: remove random data retrieval */
int
header_length_total
=
0
;
int
header_length_last
=
0
;
int
sdu_length_total
=
0
;
int
num_sdus
=
0
;
uint16_t
sdu_lengths
[
NB_RB_MAX
]
=
{
0
};
uint8_t
mac_sdus
[
MAX_NR_DLSCH_PAYLOAD_BYTES
];
unsigned
char
sdu_lcids
[
NB_RB_MAX
]
=
{
0
};
const
rnti_t
rnti
=
UE_info
->
rnti
[
UE_id
];
const
int
lcid
=
DL_SCH_LCID_DTCH
;
if
(
sched_ctrl
->
num_total_bytes
>
0
)
{
LOG_D
(
MAC
,
"[gNB %d][USER-PLANE DEFAULT DRB] Frame %d : DTCH->DLSCH, Requesting "
"%d bytes from RLC (lcid %d total hdr len %d), TBS: %d
\n
\n
"
,
module_id
,
frame
,
TBS
-
ta_len
-
header_length_total
-
sdu_length_total
-
3
,
lcid
,
header_length_total
,
TBS
);
sdu_lengths
[
num_sdus
]
=
mac_rlc_data_req
(
module_id
,
rnti
,
module_id
,
frame
,
TBS
-
ta_len
-
header_length_total
-
sdu_length_total
-
3
,
ENB_FLAG_YES
,
MBMS_FLAG_NO
,
lcid
,
header_length_total
,
TBS
);
TBS
-
ta_len
-
header_length_total
-
sdu_length_total
-
3
,
(
char
*
)
&
mac_sdus
[
sdu_length_total
],
0
,
0
);
sdu_lengths
[
num_sdus
]
=
mac_rlc_data_req
(
module_id
,
rnti
,
module_id
,
frame
,
ENB_FLAG_YES
,
MBMS_FLAG_NO
,
lcid
,
TBS
-
ta_len
-
header_length_total
-
sdu_length_total
-
3
,
(
char
*
)
&
mac_sdus
[
sdu_length_total
],
0
,
0
);
LOG_D
(
MAC
,
"[gNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d
\n
"
,
module_id
,
sdu_lengths
[
num_sdus
],
lcid
);
LOG_D
(
MAC
,
"[gNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d
\n
"
,
module_id
,
sdu_lengths
[
num_sdus
],
lcid
);
sdu_lcids
[
num_sdus
]
=
lcid
;
sdu_length_total
+=
sdu_lengths
[
num_sdus
];
header_length_last
=
1
+
1
+
(
sdu_lengths
[
num_sdus
]
>=
128
);
header_length_total
+=
header_length_last
;
sdu_lcids
[
num_sdus
]
=
lcid
;
sdu_length_total
+=
sdu_lengths
[
num_sdus
];
header_length_last
=
1
+
1
+
(
sdu_lengths
[
num_sdus
]
>=
128
);
header_length_total
+=
header_length_last
;
num_sdus
++
;
num_sdus
++
;
//ue_sched_ctl->uplane_inactivity_timer = 0;
}
else
if
(
get_softmodem_params
()
->
phy_test
)
{
LOG_D
(
MAC
,
"Configuring DL_TX in %d.%d: random data
\n
"
,
frame
,
slot
);
// fill dlsch_buffer with random data
for
(
int
i
=
0
;
i
<
TBS
;
i
++
)
mac_sdus
[
i
]
=
(
unsigned
char
)
(
lrand48
()
&
0xff
);
sdu_lcids
[
0
]
=
0x3f
;
// DRB
sdu_lengths
[
0
]
=
TBS
-
ta_len
-
3
;
header_length_total
+=
2
+
(
sdu_lengths
[
0
]
>=
128
);
sdu_length_total
+=
sdu_lengths
[
0
];
num_sdus
+=
1
;
}
//ue_sched_ctl->uplane_inactivity_timer = 0;
}
else
if
(
get_softmodem_params
()
->
phy_test
)
{
LOG_D
(
MAC
,
"Configuring DL_TX in %d.%d: random data
\n
"
,
frame
,
slot
);
// fill dlsch_buffer with random data
for
(
int
i
=
0
;
i
<
TBS
;
i
++
)
mac_sdus
[
i
]
=
(
unsigned
char
)
(
lrand48
()
&
0xff
);
sdu_lcids
[
0
]
=
0x3f
;
// DRB
sdu_lengths
[
0
]
=
TBS
-
ta_len
-
3
;
header_length_total
+=
2
+
(
sdu_lengths
[
0
]
>=
128
);
sdu_length_total
+=
sdu_lengths
[
0
];
num_sdus
+=
1
;
}
// there is at least one SDU or TA command
// if (num_sdus > 0 ){
if
(
ta_len
+
sdu_length_total
+
header_length_total
==
0
)
{
// There is no data from RLC or MAC header, so don't schedule
return
;
}
// there is at least one SDU or TA command
// if (num_sdus > 0 ){
if
(
ta_len
+
sdu_length_total
+
header_length_total
==
0
)
{
// There is no data from RLC or MAC header, so don't schedule
return
;
}
// Check if there is data from RLC or CE
const
int
post_padding
=
TBS
>=
2
+
header_length_total
+
sdu_length_total
+
ta_len
;
// padding param currently not in use
//padding = TBS - header_length_total - sdu_length_total - ta_len - 1;
// Check if there is data from RLC or CE
const
int
post_padding
=
TBS
>=
2
+
header_length_total
+
sdu_length_total
+
ta_len
;
// padding param currently not in use
//padding = TBS - header_length_total - sdu_length_total - ta_len - 1;
const
int
offset
=
nr_generate_dlsch_pdu
(
module_id
,
(
unsigned
char
*
)
mac_sdus
,
(
unsigned
char
*
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
],
num_sdus
,
// num_sdus
sdu_lengths
,
sdu_lcids
,
255
,
// no drx
NULL
,
// contention res id
post_padding
);
// Padding: fill remainder of DLSCH with 0
if
(
post_padding
>
0
)
{
for
(
int
j
=
0
;
j
<
TBS
-
offset
;
j
++
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
][
offset
+
j
]
=
0
;
}
const
int
offset
=
nr_generate_dlsch_pdu
(
module_id
,
(
unsigned
char
*
)
mac_sdus
,
(
unsigned
char
*
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
],
num_sdus
,
// num_sdus
sdu_lengths
,
sdu_lcids
,
255
,
// no drx
NULL
,
// contention res id
post_padding
);
// Padding: fill remainder of DLSCH with 0
if
(
post_padding
>
0
)
{
for
(
int
j
=
0
;
j
<
TBS
-
offset
;
j
++
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
][
offset
+
j
]
=
0
;
}
const
int
current_harq_pid
=
sched_ctrl
->
current_harq_pid
;
NR_UE_harq_t
*
harq
=
&
sched_ctrl
->
harq_processes
[
current_harq_pid
];
NR_sched_pucch
*
pucch
=
&
sched_ctrl
->
sched_pucch
[
sched_ctrl
->
pucch_sched_idx
];
harq
->
feedback_slot
=
pucch
->
ul_slot
;
harq
->
is_waiting
=
1
;
UE_info
->
mac_stats
[
UE_id
].
dlsch_rounds
[
harq
->
round
]
++
;
if
(
harq
->
round
==
0
)
UE_info
->
mac_stats
[
UE_id
].
dlsch_total_bytes
+=
TBS
;
nfapi_nr_dl_tti_request_body_t
*
dl_req
=
&
gNB_mac
->
DL_req
[
CC_id
].
dl_tti_request_body
;
nr_fill_nfapi_dl_pdu
(
module_id
,
UE_id
,
sched_ctrl
->
active_bwp
->
bwp_Id
,
sched_ctrl
->
search_space
,
sched_ctrl
->
coreset
,
dl_req
,
pucch
,
1
/* nrOfLayers */
,
sched_ctrl
->
mcs
,
sched_ctrl
->
rbSize
,
sched_ctrl
->
rbStart
,
sched_ctrl
->
numDmrsCdmGrpsNoData
,
getDmrsConfigType
(
sched_ctrl
->
active_bwp
),
sched_ctrl
->
mcsTableIdx
,
nr_get_code_rate_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
nr_get_Qm_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
TBS
,
sched_ctrl
->
time_domain_allocation
,
startSymbolIndex
,
nrOfSymbols
,
sched_ctrl
->
aggregation_level
,
sched_ctrl
->
cce_index
,
current_harq_pid
,
harq
->
ndi
,
harq
->
round
);
nfapi_nr_pdu_t
*
tx_req
=
&
gNB_mac
->
TX_req
[
CC_id
].
pdu_list
[
gNB_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
];
configure_fapi_dl_Tx
(
module_id
,
frame
,
slot
,
dl_req
,
tx_req
,
TBS
,
gNB_mac
->
pdu_index
[
CC_id
]);
const
int
current_harq_pid
=
sched_ctrl
->
current_harq_pid
;
NR_UE_harq_t
*
harq
=
&
sched_ctrl
->
harq_processes
[
current_harq_pid
];
NR_sched_pucch
*
pucch
=
&
sched_ctrl
->
sched_pucch
[
sched_ctrl
->
pucch_sched_idx
];
harq
->
feedback_slot
=
pucch
->
ul_slot
;
harq
->
is_waiting
=
1
;
UE_info
->
mac_stats
[
UE_id
].
dlsch_rounds
[
harq
->
round
]
++
;
if
(
harq
->
round
==
0
)
UE_info
->
mac_stats
[
UE_id
].
dlsch_total_bytes
+=
TBS
;
nfapi_nr_dl_tti_request_body_t
*
dl_req
=
&
gNB_mac
->
DL_req
[
CC_id
].
dl_tti_request_body
;
nr_fill_nfapi_dl_pdu
(
module_id
,
UE_id
,
sched_ctrl
->
active_bwp
->
bwp_Id
,
sched_ctrl
->
search_space
,
sched_ctrl
->
coreset
,
dl_req
,
pucch
,
1
/* nrOfLayers */
,
sched_ctrl
->
mcs
,
sched_ctrl
->
rbSize
,
sched_ctrl
->
rbStart
,
sched_ctrl
->
numDmrsCdmGrpsNoData
,
getDmrsConfigType
(
sched_ctrl
->
active_bwp
),
sched_ctrl
->
mcsTableIdx
,
nr_get_code_rate_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
nr_get_Qm_dl
(
sched_ctrl
->
mcs
,
sched_ctrl
->
mcsTableIdx
),
TBS
,
sched_ctrl
->
time_domain_allocation
,
startSymbolIndex
,
nrOfSymbols
,
sched_ctrl
->
aggregation_level
,
sched_ctrl
->
cce_index
,
current_harq_pid
,
harq
->
ndi
,
harq
->
round
);
nfapi_nr_pdu_t
*
tx_req
=
&
gNB_mac
->
TX_req
[
CC_id
].
pdu_list
[
gNB_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
];
configure_fapi_dl_Tx
(
module_id
,
frame
,
slot
,
dl_req
,
tx_req
,
TBS
,
gNB_mac
->
pdu_index
[
CC_id
]);
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
if
(
frame
%
100
==
0
){
LOG_I
(
MAC
,
"%d.%d, first 10 payload bytes, TBS size: %d
\n
"
,
frame
,
slot
,
TBS
);
for
(
int
i
=
0
;
i
<
10
;
i
++
)
{
LOG_I
(
MAC
,
"byte %d : %x
\n
"
,
i
,((
uint8_t
*
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
])[
i
]);
if
(
frame
%
100
==
0
){
LOG_I
(
MAC
,
"%d.%d, first 10 payload bytes, TBS size: %d
\n
"
,
frame
,
slot
,
TBS
);
for
(
int
i
=
0
;
i
<
10
;
i
++
)
{
LOG_I
(
MAC
,
"byte %d : %x
\n
"
,
i
,((
uint8_t
*
)
gNB_mac
->
UE_info
.
DLSCH_pdu
[
0
][
0
].
payload
[
0
])[
i
]);
}
}
}
#endif
}
}
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