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Commit fa27f9ad authored by francescomani's avatar francescomani
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moving decision on DCI format type from L1 to MAC

parent 1cae1879
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Showing with 575 additions and 602 deletions
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
View file @ fa27f9ad
...@@ -55,6 +55,12 @@ typedef enum { ...@@ -55,6 +55,12 @@ typedef enum {
RLM_in_sync = 2 RLM_in_sync = 2
} rlm_t; } rlm_t;
typedef enum {
NFAPI_NR_FORMAT_0_0_AND_1_0,
NFAPI_NR_FORMAT_0_1_AND_1_1,
} nfapi_nr_dci_formats_e;
typedef struct { typedef struct {
uint32_t rsrp; uint32_t rsrp;
int rsrp_dBm; int rsrp_dBm;
...@@ -94,7 +100,7 @@ typedef struct { ...@@ -94,7 +100,7 @@ typedef struct {
typedef struct { typedef struct {
uint16_t rnti; uint16_t rnti;
uint8_t dci_format; nfapi_nr_dci_formats_e dci_format;
uint8_t coreset_type; uint8_t coreset_type;
int ss_type; int ss_type;
// n_CCE index of first CCE for PDCCH reception // n_CCE index of first CCE for PDCCH reception
...@@ -427,7 +433,7 @@ typedef struct { ...@@ -427,7 +433,7 @@ typedef struct {
// needs to monitor only upto 2 DCI lengths for a given search space. // needs to monitor only upto 2 DCI lengths for a given search space.
uint8_t num_dci_options; // Num DCIs the UE actually needs to decode (1 or 2) uint8_t num_dci_options; // Num DCIs the UE actually needs to decode (1 or 2)
uint8_t dci_length_options[2]; uint8_t dci_length_options[2];
uint8_t dci_format_options[2]; nfapi_nr_dci_formats_e dci_format_options[2];
uint8_t ss_type_options[2]; uint8_t ss_type_options[2];
} fapi_nr_dl_config_dci_dl_pdu_rel15_t; } fapi_nr_dl_config_dci_dl_pdu_rel15_t;
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ fa27f9ad
...@@ -43,15 +43,6 @@ ...@@ -43,15 +43,6 @@
#include "assertions.h" #include "assertions.h"
#include "T.h" #include "T.h"
static const char nr_dci_format_string[8][30] = {"NR_DL_DCI_FORMAT_1_0",
"NR_DL_DCI_FORMAT_1_1",
"NR_DL_DCI_FORMAT_2_0",
"NR_DL_DCI_FORMAT_2_1",
"NR_DL_DCI_FORMAT_2_2",
"NR_DL_DCI_FORMAT_2_3",
"NR_UL_DCI_FORMAT_0_0",
"NR_UL_DCI_FORMAT_0_1"};
//#define DEBUG_DCI_DECODING 1 //#define DEBUG_DCI_DECODING 1
//#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs //#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs
...@@ -699,24 +690,22 @@ static uint16_t nr_dci_false_detection(uint64_t *dci, ...@@ -699,24 +690,22 @@ static uint16_t nr_dci_false_detection(uint64_t *dci,
int rnti, int rnti,
int8_t messageType, int8_t messageType,
uint16_t messageLength, uint16_t messageLength,
uint8_t aggregation_level uint8_t aggregation_level)
) { {
uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
polar_encoder_fast(dci, (void*)encoder_output, rnti, 1, polar_encoder_fast(dci, (void *)encoder_output, rnti, 1, messageType, messageLength, aggregation_level);
messageType, messageLength, aggregation_level);
uint8_t *enout_p = (uint8_t*)encoder_output; uint8_t *enout_p = (uint8_t*)encoder_output;
uint16_t x = 0; uint16_t x = 0;
for (int i=0; i<encoded_length/8; i++) { for (int i=0; i<encoded_length/8; i++) {
x += ( enout_p[i] & 1 ) ^ ( ( soft_in[i*8] >> 15 ) & 1); x += (enout_p[i] & 1) ^ ((soft_in[i * 8] >> 15) & 1);
x += ( ( enout_p[i] >> 1 ) & 1 ) ^ ( ( soft_in[i*8+1] >> 15 ) & 1 ); x += ((enout_p[i] >> 1) & 1) ^ ((soft_in[i * 8 + 1] >> 15) & 1);
x += ( ( enout_p[i] >> 2 ) & 1 ) ^ ( ( soft_in[i*8+2] >> 15 ) & 1 ); x += ((enout_p[i] >> 2) & 1) ^ ((soft_in[i * 8 + 2] >> 15) & 1);
x += ( ( enout_p[i] >> 3 ) & 1 ) ^ ( ( soft_in[i*8+3] >> 15 ) & 1 ); x += ((enout_p[i] >> 3) & 1) ^ ((soft_in[i * 8 + 3] >> 15) & 1);
x += ( ( enout_p[i] >> 4 ) & 1 ) ^ ( ( soft_in[i*8+4] >> 15 ) & 1 ); x += ((enout_p[i] >> 4) & 1) ^ ((soft_in[i * 8 + 4] >> 15) & 1);
x += ( ( enout_p[i] >> 5 ) & 1 ) ^ ( ( soft_in[i*8+5] >> 15 ) & 1 ); x += ((enout_p[i] >> 5) & 1) ^ ((soft_in[i * 8 + 5] >> 15) & 1);
x += ( ( enout_p[i] >> 6 ) & 1 ) ^ ( ( soft_in[i*8+6] >> 15 ) & 1 ); x += ((enout_p[i] >> 6) & 1) ^ ((soft_in[i * 8 + 6] >> 15) & 1);
x += ( ( enout_p[i] >> 7 ) & 1 ) ^ ( ( soft_in[i*8+7] >> 15 ) & 1 ); x += ((enout_p[i] >> 7) & 1) ^ ((soft_in[i * 8 + 7] >> 15) & 1);
} }
return x; return x;
} }
...@@ -730,7 +719,7 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -730,7 +719,7 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
int e_rx_cand_idx = 0; int e_rx_cand_idx = 0;
*dci_ind = (fapi_nr_dci_indication_t){.SFN = proc->frame_rx, .slot = proc->nr_slot_rx}; *dci_ind = (fapi_nr_dci_indication_t){.SFN = proc->frame_rx, .slot = proc->nr_slot_rx};
for (int j=0;j<rel15->number_of_candidates;j++) { for (int j = 0; j < rel15->number_of_candidates; j++) {
int CCEind = rel15->CCE[j]; int CCEind = rel15->CCE[j];
int L = rel15->L[j]; int L = rel15->L[j];
...@@ -751,7 +740,7 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -751,7 +740,7 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
uint64_t dci_estimation[2]= {0}; uint64_t dci_estimation[2]= {0};
LOG_D(NR_PHY_DCI, LOG_D(NR_PHY_DCI,
"(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %s\n", "(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %d\n",
proc->frame_rx, proc->frame_rx,
proc->nr_slot_rx, proc->nr_slot_rx,
j, j,
...@@ -760,31 +749,31 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -760,31 +749,31 @@ void nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
e_rx_cand_idx, e_rx_cand_idx,
L, L,
dci_length, dci_length,
nr_dci_format_string[rel15->dci_format_options[k]]); rel15->dci_format_options[k]);
int16_t tmp_e[16 * 108]; int16_t tmp_e[16 * 108];
nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx],
// this polar version decodes 64 bits max, dci_estimation[1] will never be filled rel15->coreset.scrambling_rnti,
uint16_t crc = polar_decoder_int16(tmp_e, L * 108,
dci_estimation, rel15->coreset.pdcch_dmrs_scrambling_id,
1, tmp_e);
NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
uint16_t crc = polar_decoder_int16(tmp_e, dci_estimation, 1, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
rnti_t n_rnti = rel15->rnti; rnti_t n_rnti = rel15->rnti;
LOG_D(NR_PHY_DCI,
"(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %lx, is rnti: %d )\n",
proc->frame_rx,
proc->nr_slot_rx,
n_rnti,
nr_dci_format_string[rel15->dci_format_options[k]],
CCEind,
dci_length,
dci_estimation[0],
crc == n_rnti);
if (crc == n_rnti) { if (crc == n_rnti) {
uint16_t mb = nr_dci_false_detection(dci_estimation,tmp_e,L*108,n_rnti, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L); LOG_D(NR_PHY_DCI,
"(%i.%i) Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx,
proc->nr_slot_rx,
n_rnti,
rel15->dci_format_options[k],
CCEind,
dci_length,
*(unsigned long long *)dci_estimation);
uint16_t mb = nr_dci_false_detection(dci_estimation, tmp_e, L * 108, n_rnti, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
ue->dci_thres = (ue->dci_thres + mb) / 2; ue->dci_thres = (ue->dci_thres + mb) / 2;
if (mb > (ue->dci_thres+30)) { if (mb > (ue->dci_thres + 30)) {
LOG_W(NR_PHY_DCI, LOG_W(NR_PHY_DCI,
"DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n", "DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n",
j, j,
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
View file @ fa27f9ad
...@@ -39,8 +39,6 @@ ...@@ -39,8 +39,6 @@
extern const uint8_t nr_slots_per_frame[5]; extern const uint8_t nr_slots_per_frame[5];
extern dci_pdu_rel15_t *def_dci_pdu_rel15;
/* Scheduler */ /* Scheduler */
extern RAN_CONTEXT_t RC; extern RAN_CONTEXT_t RC;
extern uint8_t nfapi_mode; extern uint8_t nfapi_mode;
......
openair2/LAYER2/NR_MAC_UE/mac_extern.h
View file @ fa27f9ad
...@@ -66,8 +66,6 @@ extern const uint8_t table_7_3_2_3_3_4_twoCodeword[6][14]; ...@@ -66,8 +66,6 @@ extern const uint8_t table_7_3_2_3_3_4_twoCodeword[6][14];
extern const uint16_t table_7_2_1[16]; extern const uint16_t table_7_2_1[16];
extern dci_pdu_rel15_t *def_dci_pdu_rel15;
extern void mac_rlc_data_ind(const module_id_t module_idP, extern void mac_rlc_data_ind(const module_id_t module_idP,
const rnti_t rntiP, const rnti_t rntiP,
const eNB_index_t eNB_index, const eNB_index_t eNB_index,
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ fa27f9ad
...@@ -120,18 +120,8 @@ subframe number \param[in] slotP slot number ...@@ -120,18 +120,8 @@ subframe number \param[in] slotP slot number
*/ */
int8_t nr_ue_get_SR(NR_UE_MAC_INST_t *mac, frame_t frameP, slot_t slotP); int8_t nr_ue_get_SR(NR_UE_MAC_INST_t *mac, frame_t frameP, slot_t slotP);
int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac, nr_dci_format_t nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci);
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
fapi_nr_dci_indication_pdu_t *dci_ind);
int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac,
int cc_id,
int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci);
int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac, int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac,
frame_t frame, frame_t frame,
int slot, int slot,
......
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @ fa27f9ad
...@@ -107,7 +107,6 @@ NR_ControlResourceSet_t *ue_get_coreset(const NR_BWP_PDCCH_t *config, const int ...@@ -107,7 +107,6 @@ NR_ControlResourceSet_t *ue_get_coreset(const NR_BWP_PDCCH_t *config, const int
return coreset; return coreset;
} }
void config_dci_pdu(NR_UE_MAC_INST_t *mac, void config_dci_pdu(NR_UE_MAC_INST_t *mac,
fapi_nr_dl_config_request_t *dl_config, fapi_nr_dl_config_request_t *dl_config,
const int rnti_type, const int rnti_type,
...@@ -160,36 +159,40 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, ...@@ -160,36 +159,40 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
rel15->coreset.pdcch_dmrs_scrambling_id = mac->physCellId; rel15->coreset.pdcch_dmrs_scrambling_id = mac->physCellId;
} }
rel15->num_dci_options = (mac->ra.ra_state == nrRA_WAIT_RAR || rnti_type == TYPE_SI_RNTI_) ? 1 : 2; int temp_num_dci_options = (mac->ra.ra_state == nrRA_WAIT_RAR || rnti_type == TYPE_SI_RNTI_) ? 1 : 2;
int dci_format[2] = {0};
if (ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) { if (ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) {
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == if (ss->searchSpaceType->choice.ue_Specific->dci_Formats ==
NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) { NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) {
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; dci_format[0] = NR_DL_DCI_FORMAT_1_0;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0; dci_format[1] = NR_UL_DCI_FORMAT_0_0;
} }
else { else {
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_1; dci_format[0] = NR_DL_DCI_FORMAT_1_1;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_1; dci_format[1] = NR_UL_DCI_FORMAT_0_1;
} }
} }
else { // common else { // common
AssertFatal(ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0, AssertFatal(ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0,
"Only supporting format 10 and 00 for common SS\n"); "Only supporting format 10 and 00 for common SS\n");
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; dci_format[0] = NR_DL_DCI_FORMAT_1_0;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0; dci_format[1] = NR_UL_DCI_FORMAT_0_0;
} }
NR_UE_ServingCell_Info_t *sc_info = &mac->sc_info; NR_UE_ServingCell_Info_t *sc_info = &mac->sc_info;
// loop over RNTI type and configure resource allocation for DCI // loop over DCI options and configure resource allocation
for (int i = 0; i < rel15->num_dci_options; i++) { // need to configure mac->def_dci_pdu_rel15 for all possible format options
for (int i = 0; i < temp_num_dci_options; i++) {
rel15->ss_type_options[i] = ss->searchSpaceType->present; rel15->ss_type_options[i] = ss->searchSpaceType->present;
const int dci_format = rel15->dci_format_options[i]; if (dci_format[i] == NR_DL_DCI_FORMAT_1_0 || dci_format[i] == NR_UL_DCI_FORMAT_0_0)
rel15->dci_format_options[i] = NFAPI_NR_FORMAT_0_0_AND_1_0;
else
rel15->dci_format_options[i] = NFAPI_NR_FORMAT_0_1_AND_1_1;
uint16_t alt_size = 0; uint16_t alt_size = 0;
if(current_DL_BWP) { if(current_DL_BWP) {
// computing alternative size for padding // computing alternative size for padding or truncation
dci_pdu_rel15_t temp_pdu; dci_pdu_rel15_t temp_pdu;
if(dci_format == NR_DL_DCI_FORMAT_1_0) if (dci_format[i] == NR_DL_DCI_FORMAT_1_0)
alt_size = nr_dci_size(current_DL_BWP, alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP, current_UL_BWP,
sc_info, sc_info,
...@@ -202,7 +205,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, ...@@ -202,7 +205,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
ss->searchSpaceType->present, ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs, mac->type0_PDCCH_CSS_config.num_rbs,
0); 0);
if(dci_format == NR_UL_DCI_FORMAT_0_0) if (dci_format[i] == NR_UL_DCI_FORMAT_0_0)
alt_size = nr_dci_size(current_DL_BWP, alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP, current_UL_BWP,
sc_info, sc_info,
...@@ -221,8 +224,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, ...@@ -221,8 +224,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
current_UL_BWP, current_UL_BWP,
sc_info, sc_info,
mac->pdsch_HARQ_ACK_Codebook, mac->pdsch_HARQ_ACK_Codebook,
&mac->def_dci_pdu_rel15[dl_config->slot][dci_format], &mac->def_dci_pdu_rel15[dl_config->slot][dci_format[i]],
dci_format, dci_format[i],
rnti_type, rnti_type,
coreset, coreset,
dl_bwp_id, dl_bwp_id,
...@@ -234,6 +237,13 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, ...@@ -234,6 +237,13 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
rel15->dci_length_options[i] = dci_size; rel15->dci_length_options[i] = dci_size;
} }
// DCI 0_0 and 1_0 are same size, L1 just needs to look for 1 option
// L2 decides format based on format indicator in payload
if (rel15->dci_format_options[0] == NFAPI_NR_FORMAT_0_0_AND_1_0)
rel15->num_dci_options = 1;
else
rel15->num_dci_options = 2;
rel15->BWPStart = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.cset_start_rb : current_DL_BWP->BWPStart; rel15->BWPStart = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.cset_start_rb : current_DL_BWP->BWPStart;
rel15->BWPSize = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.num_rbs : current_DL_BWP->BWPSize; rel15->BWPSize = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.num_rbs : current_DL_BWP->BWPSize;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ fa27f9ad
...@@ -162,14 +162,14 @@ const initial_pucch_resource_t initial_pucch_resource[16] = { ...@@ -162,14 +162,14 @@ const initial_pucch_resource_t initial_pucch_resource[16] = {
/* 14 */ { 1, 0, 14, 4, 4, { 0, 3, 6, 9 } }, /* 14 */ { 1, 0, 14, 4, 4, { 0, 3, 6, 9 } },
/* 15 */ { 1, 0, 14, 0, 4, { 0, 3, 6, 9 } }, /* 15 */ { 1, 0, 14, 0, 4, { 0, 3, 6, 9 } },
}; };
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
const nr_dci_format_t dci_format, static nr_dci_format_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
const uint8_t dci_size, const nfapi_nr_dci_formats_e dci_format,
const uint16_t rnti, const uint8_t dci_size,
const int ss_type, const uint16_t rnti,
const uint8_t *dci_pdu, const int ss_type,
dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu,
const int slot); const int slot);
int get_rnti_type(const NR_UE_MAC_INST_t *mac, const uint16_t rnti) int get_rnti_type(const NR_UE_MAC_INST_t *mac, const uint16_t rnti)
{ {
...@@ -363,41 +363,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p ...@@ -363,41 +363,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
return 0; return 0;
} }
int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac,
int cc_id,
int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci)
{
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format];
LOG_D(MAC,
"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
dci->rnti,
dci->dci_format,
dci->n_CCE,
dci->payloadSize,
*(unsigned long long *)dci->payloadBits);
const int ret = nr_extract_dci_info(mac,
dci->dci_format,
dci->payloadSize,
dci->rnti,
dci->ss_type,
dci->payloadBits,
def_dci_pdu_rel15,
slot);
if ((ret & 1) == 1)
return -1;
else if (ret == 2) {
dci->dci_format = (dci->dci_format == NR_UL_DCI_FORMAT_0_0) ? NR_DL_DCI_FORMAT_1_0 : NR_UL_DCI_FORMAT_0_0;
def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format];
}
return nr_ue_process_dci(mac, cc_id, frame, slot, def_dci_pdu_rel15, dci);
}
static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac, static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame, frame_t frame,
int slot, int slot,
dci_pdu_rel15_t *dci, dci_pdu_rel15_t *dci,
...@@ -453,7 +419,6 @@ static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac, ...@@ -453,7 +419,6 @@ static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac,
} }
static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac, static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame, frame_t frame,
int slot, int slot,
dci_pdu_rel15_t *dci, dci_pdu_rel15_t *dci,
...@@ -526,7 +491,6 @@ static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac, ...@@ -526,7 +491,6 @@ static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac,
} }
static int nr_ue_process_dci_dl_10(NR_UE_MAC_INST_t *mac, static int nr_ue_process_dci_dl_10(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame, frame_t frame,
int slot, int slot,
dci_pdu_rel15_t *dci, dci_pdu_rel15_t *dci,
...@@ -866,7 +830,6 @@ static inline uint16_t packBits(const uint8_t *toPack, const int nb) ...@@ -866,7 +830,6 @@ static inline uint16_t packBits(const uint8_t *toPack, const int nb)
} }
static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac, static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame, frame_t frame,
int slot, int slot,
dci_pdu_rel15_t *dci, dci_pdu_rel15_t *dci,
...@@ -1242,31 +1205,31 @@ static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac, ...@@ -1242,31 +1205,31 @@ static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac,
return 0; return 0;
} }
int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac, static int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
int cc_id, frame_t frame,
frame_t frame, int slot,
int slot, dci_pdu_rel15_t *dci,
dci_pdu_rel15_t *dci, fapi_nr_dci_indication_pdu_t *dci_ind,
fapi_nr_dci_indication_pdu_t *dci_ind) const nr_dci_format_t format)
{ {
const char *dci_formats[] = {"1_0", "1_1", "2_0", "2_1", "2_2", "2_3", "0_0", "0_1"}; const char *dci_formats[] = {"1_0", "1_1", "2_0", "2_1", "2_2", "2_3", "0_0", "0_1"};
LOG_D(MAC, "Processing received DCI format %s\n", dci_formats[dci_ind->dci_format]); LOG_D(MAC, "Processing received DCI format %s\n", dci_formats[format]);
switch (dci_ind->dci_format) { switch (format) {
case NR_UL_DCI_FORMAT_0_0: case NR_UL_DCI_FORMAT_0_0:
return nr_ue_process_dci_ul_00(mac, cc_id, frame, slot, dci, dci_ind); return nr_ue_process_dci_ul_00(mac, frame, slot, dci, dci_ind);
break; break;
case NR_UL_DCI_FORMAT_0_1: case NR_UL_DCI_FORMAT_0_1:
return nr_ue_process_dci_ul_01(mac, cc_id, frame, slot, dci, dci_ind); return nr_ue_process_dci_ul_01(mac, frame, slot, dci, dci_ind);
break; break;
case NR_DL_DCI_FORMAT_1_0: case NR_DL_DCI_FORMAT_1_0:
return nr_ue_process_dci_dl_10(mac, cc_id, frame, slot, dci, dci_ind); return nr_ue_process_dci_dl_10(mac, frame, slot, dci, dci_ind);
break; break;
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
return nr_ue_process_dci_dl_11(mac, cc_id, frame, slot, dci, dci_ind); return nr_ue_process_dci_dl_11(mac, frame, slot, dci, dci_ind);
break; break;
case NR_DL_DCI_FORMAT_2_0: case NR_DL_DCI_FORMAT_2_0:
...@@ -1288,10 +1251,29 @@ int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac, ...@@ -1288,10 +1251,29 @@ int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
default: default:
break; break;
} }
return -1; return -1;
} }
nr_dci_format_t nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci)
{
LOG_D(NR_MAC,
"Received dci indication (rnti %x, dci format %d, n_CCE %d, payloadSize %d, payload %llx)\n",
dci->rnti,
dci->dci_format,
dci->n_CCE,
dci->payloadSize,
*(unsigned long long *)dci->payloadBits);
const nr_dci_format_t format =
nr_extract_dci_info(mac, dci->dci_format, dci->payloadSize, dci->rnti, dci->ss_type, dci->payloadBits, slot);
if (format == NR_DCI_NONE)
return NR_DCI_NONE;
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
int ret = nr_ue_process_dci(mac, frame, slot, def_dci_pdu_rel15, dci, format);
if (ret < 0)
return NR_DCI_NONE;
return format;
}
int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac, int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac,
frame_t frame, frame_t frame,
int slot, int slot,
...@@ -2923,19 +2905,287 @@ static inline int readBits(const uint8_t *dci, int *start, int length) ...@@ -2923,19 +2905,287 @@ static inline int readBits(const uint8_t *dci, int *start, int length)
return *tmp >> *start & mask[length]; return *tmp >> *start & mask[length];
} }
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, static void extract_10_ra_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos, const int N_RB)
const nr_dci_format_t dci_format, {
const uint8_t dci_size, LOG_D(NR_MAC_DCI, "Received dci 1_0 RA rnti\n");
const uint16_t rnti,
const int ss_type, // Freq domain assignment
const uint8_t *dci_pdu, EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
dci_pdu_rel15_t *dci_pdu_rel15, // Time domain assignment
const int slot) EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// TB scaling
EXTRACT_DCI_ITEM(dci_pdu_rel15->tb_scaling, 2);
}
static void extract_10_si_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos, const int N_RB)
{
LOG_D(NR_MAC_DCI, "Received dci 1_0 SI rnti\n");
// Freq domain assignment 0-16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment 4 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit //bit over 32
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// Redundancy version 2 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// System information indicator 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->system_info_indicator, 1);
}
static void extract_10_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos, const int N_RB)
{
LOG_D(NR_MAC_DCI, "Received dci 1_0 C rnti\n");
// Freq domain assignment (275rb >> fsize = 16)
int fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, fsize);
bool pdcch_order = true;
for (int i = 0; i < fsize; i++) {
if (!((dci_pdu_rel15->frequency_domain_assignment.val >> i) & 1)) {
pdcch_order = false;
break;
}
}
if (pdcch_order) { // Frequency domain resource assignment field are all 1 38.212 section 7.3.1.2.1
// ra_preamble_index 6 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->ra_preamble_index, 6);
// UL/SUL indicator 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, 1);
// SS/PBCH index 6 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->ss_pbch_index, 6);
// prach_mask_index 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->prach_mask_index, 4);
} // end if
else {
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit //bit over 32, so dci_pdu ++
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
// TPC command for scheduled PUCCH 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
} // end else
}
static void extract_00_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos)
{
LOG_D(NR_MAC_DCI, "Received dci 0_0 C rnti\n");
// Frequency domain assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// Frequency hopping flag  E1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// TPC command for scheduled PUSCH  E2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// UL/SUL indicator  E1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)readBits(dci_pdu,>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
}
static void extract_10_tc_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos, const int N_RB)
{
LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
// Freq domain assignment 0-16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment - 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping - 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator - 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number - 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
// TPC command for scheduled PUCCH - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator - 3 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
}
static void extract_00_tc_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos)
{ {
LOG_D(NR_MAC, "nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *(uint64_t *)dci_pdu, dci_size, dci_format); LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
const int rnti_type = get_rnti_type(mac, rnti);
const NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP; // Frequency domain assignment
const NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP; EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// Frequency hopping flag  E1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// TPC command for scheduled PUSCH  E2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
}
static void extract_11_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos)
{
LOG_D(NR_MAC_DCI, "Received dci 1_1 C rnti\n");
// Carrier indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits);
// BWP Indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits);
// Frequency domain resource assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
// Time domain resource assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
// VRB-to-PRB mapping
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, dci_pdu_rel15->vrb_to_prb_mapping.nbits);
// PRB bundling size indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->prb_bundling_size_indicator.val, dci_pdu_rel15->prb_bundling_size_indicator.nbits);
// Rate matching indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->rate_matching_indicator.val, dci_pdu_rel15->rate_matching_indicator.nbits);
// ZP CSI-RS trigger
EXTRACT_DCI_ITEM(dci_pdu_rel15->zp_csi_rs_trigger.val, dci_pdu_rel15->zp_csi_rs_trigger.nbits);
// TB1
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
//TB2
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs2.val, dci_pdu_rel15->mcs2.nbits);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi2.val, dci_pdu_rel15->ndi2.nbits);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv2.val, dci_pdu_rel15->rv2.nbits);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
// TPC command for scheduled PUCCH 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits);
// Antenna ports
EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
// TCI
EXTRACT_DCI_ITEM(dci_pdu_rel15->transmission_configuration_indication.val,
dci_pdu_rel15->transmission_configuration_indication.nbits);
// SRS request
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
// CBG transmission information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
// CBG flushing out information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgfi.val, dci_pdu_rel15->cbgfi.nbits);
// DMRS sequence init
EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, 1);
}
static void extract_01_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, const uint8_t *dci_pdu, int pos, const int N_RB)
{
LOG_D(NR_MAC_DCI, "Received dci 0_1 C rnti\n");
// Carrier indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits);
// UL/SUL Indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, dci_pdu_rel15->ul_sul_indicator.nbits);
// BWP Indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits);
// Freq domain assignment max 16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
// Not supported yet - skip for now
// Frequency hopping flag – 1 bit
// EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// 1st Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
// 2nd Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[1].val, dci_pdu_rel15->dai[1].nbits);
// TPC command for scheduled PUSCH – 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// SRS resource indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_resource_indicator.val, dci_pdu_rel15->srs_resource_indicator.nbits);
// Precoding info and n. of layers
EXTRACT_DCI_ITEM(dci_pdu_rel15->precoding_information.val, dci_pdu_rel15->precoding_information.nbits);
// Antenna ports
EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
// SRS request
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
// CSI request
EXTRACT_DCI_ITEM(dci_pdu_rel15->csi_request.val, dci_pdu_rel15->csi_request.nbits);
// CBG transmission information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
// PTRS DMRS association
EXTRACT_DCI_ITEM(dci_pdu_rel15->ptrs_dmrs_association.val, dci_pdu_rel15->ptrs_dmrs_association.nbits);
// Beta offset indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->beta_offset_indicator.val, dci_pdu_rel15->beta_offset_indicator.nbits);
// DMRS sequence initialization
EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, dci_pdu_rel15->dmrs_sequence_initialization.nbits);
// UL-SCH indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->ulsch_indicator, 1);
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
}
static int get_nrb_for_dci(NR_UE_MAC_INST_t *mac, nr_dci_format_t dci_format, int ss_type)
{
NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
int N_RB; int N_RB;
if(current_DL_BWP) if(current_DL_BWP)
N_RB = get_rb_bwp_dci(dci_format, N_RB = get_rb_bwp_dci(dci_format,
...@@ -2948,388 +3198,133 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -2948,388 +3198,133 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
else else
N_RB = mac->type0_PDCCH_CSS_config.num_rbs; N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
if (N_RB == 0) { if (N_RB == 0)
LOG_E(MAC, "DCI configuration error! N_RB = 0\n"); LOG_E(NR_MAC_DCI, "DCI configuration error! N_RB = 0\n");
return 1;
}
int pos = dci_size;
switch(dci_format) {
case NR_DL_DCI_FORMAT_1_0:
switch(rnti_type) {
case TYPE_RA_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 RA rnti\n");
// Freq domain assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// TB scaling
EXTRACT_DCI_ITEM(dci_pdu_rel15->tb_scaling, 2);
break;
case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 C rnti\n");
// Identifier for DCI formats
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
// switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
LOG_D(NR_MAC_DCI, "received dci 1_0 c_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
// Freq domain assignment (275rb >> fsize = 16) return N_RB;
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1))); }
bool is_ra = true;
for (int i = 0; i < dci_pdu_rel15->frequency_domain_assignment.val; i++)
if (!((dci_pdu_rel15->frequency_domain_assignment.val >> i) & 1)) {
is_ra = false;
break;
}
if (is_ra) // fsize are all 1 38.212 p86
{
// ra_preamble_index 6 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->ra_preamble_index, 6);
// UL/SUL indicator 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, 1);
// SS/PBCH index 6 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->ss_pbch_index, 6);
// prach_mask_index 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->prach_mask_index, 4);
} else {
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit //bit over 32, so dci_pdu ++
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
// TPC command for scheduled PUCCH 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
}
break;
case TYPE_P_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 P rnti\n");
/*
// Short Messages Indicator  E2 bits
for (int i=0; i<2; i++)
dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++);
// Short Messages  E8 bits
for (int i=0; i<8; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// TB scaling 2 bit
for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++);
*/
break;
case TYPE_SI_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 SI rnti\n");
// Freq domain assignment 0-16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment 4 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit //bit over 32
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// Redundancy version 2 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// System information indicator 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->system_info_indicator, 1);
break;
case TYPE_TC_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
// indicating a DL DCI format 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
// switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
LOG_D(NR_MAC_DCI, "received dci 1_0 tc_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
// Freq domain assignment 0-16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment - 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// VRB to PRB mapping - 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, 1);
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator - 1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number - 4 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, 2);
// TPC command for scheduled PUCCH - 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator - 3 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val, 3);
break;
default:
LOG_W(NR_MAC_DCI, "Received dci 1_0 unknown rnti type: %d\n", rnti_type);
}
break;
case NR_UL_DCI_FORMAT_0_0:
switch(rnti_type)
{
case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 0_0 C rnti\n");
// Identifier for DCI formats
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// Frequency hopping flag  E1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// TPC command for scheduled PUSCH  E2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// UL/SUL indicator  E1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)readBits(dci_pdu,>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break;
case TYPE_TC_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 1_0 TC rnti\n");
// Identifier for DCI formats
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
//switch to DCI_1_0
if (dci_pdu_rel15->format_indicator == 1) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_DL_DCI_FORMAT_1_0];
LOG_D(NR_MAC_DCI, "received dci 0_0 tc_ rnti, switching to dci 0_0\n");
return 2 + nr_extract_dci_info(mac, NR_DL_DCI_FORMAT_1_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits);
// Time domain assignment 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, 4);
// Frequency hopping flag  E1 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_hopping_flag.val, 1);
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// TPC command for scheduled PUSCH  E2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
break;
default: static nr_dci_format_t nr_extract_dci_00_10(NR_UE_MAC_INST_t *mac,
LOG_W(NR_MAC_DCI, "Received dci 0_0 unknown rnti type: %d\n", rnti_type); int pos,
const int rnti_type,
const uint8_t *dci_pdu,
const int slot,
const int ss_type)
{
nr_dci_format_t format = NR_DCI_NONE;
dci_pdu_rel15_t *dci_pdu_rel15 = NULL;
int format_indicator = -1;
int n_RB = 0;
switch (rnti_type) {
case TYPE_RA_RNTI_ :
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_ra_rnti(dci_pdu_rel15, dci_pdu, pos, n_RB);
break;
case TYPE_P_RNTI_ :
AssertFatal(false, "DCI for P-RNTI not handled yet\n");
break;
case TYPE_SI_RNTI_ :
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_si_rnti(dci_pdu_rel15, dci_pdu, pos, n_RB);
break;
case TYPE_C_RNTI_ :
// Identifier for DCI formats
EXTRACT_DCI_ITEM(format_indicator, 1);
if (format_indicator == 1) {
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
int n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_c_rnti(dci_pdu_rel15, dci_pdu, pos, n_RB);
} }
else {
format = NR_UL_DCI_FORMAT_0_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
extract_00_c_rnti(dci_pdu_rel15, dci_pdu, pos);
}
dci_pdu_rel15->format_indicator = format_indicator;
break;
case TYPE_TC_RNTI_ :
// Identifier for DCI formats
EXTRACT_DCI_ITEM(format_indicator, 1);
if (format_indicator == 1) {
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_tc_rnti(dci_pdu_rel15, dci_pdu, pos, n_RB);
}
else {
format = NR_UL_DCI_FORMAT_0_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
extract_00_tc_rnti(dci_pdu_rel15, dci_pdu, pos);
}
dci_pdu_rel15->format_indicator = format_indicator;
break;
default :
AssertFatal(false, "Invalid RNTI type\n");
}
return format;
}
break; static nr_dci_format_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
const nfapi_nr_dci_formats_e dci_format,
case NR_DL_DCI_FORMAT_1_1: const uint8_t dci_size,
switch(rnti_type) const uint16_t rnti,
{ const int ss_type,
case TYPE_C_RNTI_: const uint8_t *dci_pdu,
LOG_D(NR_MAC_DCI, "Received dci 1_1 C rnti\n"); const int slot)
{
LOG_D(NR_MAC_DCI,"nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *(uint64_t *)dci_pdu, dci_size, dci_format);
int rnti_type = get_rnti_type(mac, rnti);
int pos = dci_size;
nr_dci_format_t format = NR_DCI_NONE;
switch(dci_format) {
case NFAPI_NR_FORMAT_0_0_AND_1_0 :
format = nr_extract_dci_00_10(mac, pos, rnti_type, dci_pdu, slot, ss_type);
break;
case NFAPI_NR_FORMAT_0_1_AND_1_1 :
if (rnti_type == TYPE_C_RNTI_) {
// Identifier for DCI formats // Identifier for DCI formats
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1); int format_indicator = 0;
if (dci_pdu_rel15->format_indicator == 0) { EXTRACT_DCI_ITEM(format_indicator, 1);
LOG_W(NR_MAC_DCI, "Received dci 1_1 C rnti and format indicator 0, discarding\n"); if (format_indicator == 1) {
return 1; // discard dci, format indicator not corresponding to dci_format format = NR_DL_DCI_FORMAT_1_1;
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
def_dci_pdu_rel15->format_indicator = format_indicator;
extract_11_c_rnti(def_dci_pdu_rel15, dci_pdu, pos);
} }
// Carrier indicator else {
format = NR_UL_DCI_FORMAT_0_1;
EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits); dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
// BWP Indicator& def_dci_pdu_rel15->format_indicator = format_indicator;
EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits); int n_RB = get_nrb_for_dci(mac, format, ss_type);
// Frequency domain resource assignment if (n_RB == 0)
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.nbits); return NR_DCI_NONE;
// Time domain resource assignment extract_01_c_rnti(def_dci_pdu_rel15, dci_pdu, pos, n_RB);
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
// VRB-to-PRB mapping
EXTRACT_DCI_ITEM(dci_pdu_rel15->vrb_to_prb_mapping.val, dci_pdu_rel15->vrb_to_prb_mapping.nbits);
// PRB bundling size indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->prb_bundling_size_indicator.val, dci_pdu_rel15->prb_bundling_size_indicator.nbits);
// Rate matching indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->rate_matching_indicator.val, dci_pdu_rel15->rate_matching_indicator.nbits);
// ZP CSI-RS trigger
EXTRACT_DCI_ITEM(dci_pdu_rel15->zp_csi_rs_trigger.val, dci_pdu_rel15->zp_csi_rs_trigger.nbits);
// TB1
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
//TB2
// MCS 5bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs2.val, dci_pdu_rel15->mcs2.nbits);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi2.val, dci_pdu_rel15->ndi2.nbits);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv2.val, dci_pdu_rel15->rv2.nbits);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
// TPC command for scheduled PUCCH 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// PUCCH resource indicator 3bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->pucch_resource_indicator, 3);
// PDSCH-to-HARQ_feedback timing indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits);
// Antenna ports
EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
// TCI
EXTRACT_DCI_ITEM(dci_pdu_rel15->transmission_configuration_indication.val,
dci_pdu_rel15->transmission_configuration_indication.nbits);
// SRS request
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
// CBG transmission information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
// CBG flushing out information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgfi.val, dci_pdu_rel15->cbgfi.nbits);
// DMRS sequence init
EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, 1);
break;
default:
LOG_W(NR_MAC_DCI, "Received dci 1_1 unknown rnti type: %d\n", rnti_type);
}
break;
case NR_UL_DCI_FORMAT_0_1:
switch(rnti_type)
{
case TYPE_C_RNTI_:
LOG_D(NR_MAC_DCI, "Received dci 0_1 C rnti\n");
//Identifier for DCI formats
EXTRACT_DCI_ITEM(dci_pdu_rel15->format_indicator, 1);
if (dci_pdu_rel15->format_indicator == 1) {
LOG_W(NR_MAC_DCI, "Received dci 0_1 C rnti and format indicator 1, discarding\n");
return 1; // discard dci, format indicator not corresponding to dci_format
} }
// Carrier indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->carrier_indicator.val, dci_pdu_rel15->carrier_indicator.nbits);
// UL/SUL Indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->ul_sul_indicator.val, dci_pdu_rel15->ul_sul_indicator.nbits);
// BWP Indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->bwp_indicator.val, dci_pdu_rel15->bwp_indicator.nbits);
// Freq domain assignment max 16 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->frequency_domain_assignment.val, (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)));
// Time domain assignment
EXTRACT_DCI_ITEM(dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.nbits);
// Not supported yet - skip for now
// Frequency hopping flag – 1 bit
// pos++;
// dci_pdu_rel15->frequency_hopping_flag.val= (readBits(dci_pdu,>>(dci_size-pos))&1;
// MCS 5 bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->mcs, 5);
// New data indicator 1bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->ndi, 1);
// Redundancy version 2bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->rv, 2);
// HARQ process number 4bit
EXTRACT_DCI_ITEM(dci_pdu_rel15->harq_pid, 4);
// 1st Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[0].val, dci_pdu_rel15->dai[0].nbits);
// 2nd Downlink assignment index
EXTRACT_DCI_ITEM(dci_pdu_rel15->dai[1].val, dci_pdu_rel15->dai[1].nbits);
// TPC command for scheduled PUSCH – 2 bits
EXTRACT_DCI_ITEM(dci_pdu_rel15->tpc, 2);
// SRS resource indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_resource_indicator.val, dci_pdu_rel15->srs_resource_indicator.nbits);
// Precoding info and n. of layers
EXTRACT_DCI_ITEM(dci_pdu_rel15->precoding_information.val, dci_pdu_rel15->precoding_information.nbits);
// Antenna ports
EXTRACT_DCI_ITEM(dci_pdu_rel15->antenna_ports.val, dci_pdu_rel15->antenna_ports.nbits);
// SRS request
EXTRACT_DCI_ITEM(dci_pdu_rel15->srs_request.val, dci_pdu_rel15->srs_request.nbits);
// CSI request
EXTRACT_DCI_ITEM(dci_pdu_rel15->csi_request.val, dci_pdu_rel15->csi_request.nbits);
// CBG transmission information
EXTRACT_DCI_ITEM(dci_pdu_rel15->cbgti.val, dci_pdu_rel15->cbgti.nbits);
// PTRS DMRS association
EXTRACT_DCI_ITEM(dci_pdu_rel15->ptrs_dmrs_association.val, dci_pdu_rel15->ptrs_dmrs_association.nbits);
// Beta offset indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->beta_offset_indicator.val, dci_pdu_rel15->beta_offset_indicator.nbits);
// DMRS sequence initialization
EXTRACT_DCI_ITEM(dci_pdu_rel15->dmrs_sequence_initialization.val, dci_pdu_rel15->dmrs_sequence_initialization.nbits);
// UL-SCH indicator
EXTRACT_DCI_ITEM(dci_pdu_rel15->ulsch_indicator, 1);
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break;
default:
LOG_W(NR_MAC_DCI, "Received dci 0_1 unknown rnti type: %d\n", rnti_type);
} }
break; else {
LOG_E(NR_MAC_DCI, "RNTI type not supported for formats 01 or 11\n");
default: // other DCI formats return NR_DCI_NONE;
LOG_W(NR_MAC_DCI, "Received dci unknown format type: %d\n", dci_format); }
break;
break; default :
LOG_E(NR_MAC_DCI, "DCI format not supported\n");
} }
return format;
return 0;
} }
/////////////////////////////////// ///////////////////////////////////
......
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @ fa27f9ad
...@@ -1059,14 +1059,9 @@ static int handle_bcch_dlsch(NR_UE_MAC_INST_t *mac, ...@@ -1059,14 +1059,9 @@ static int handle_bcch_dlsch(NR_UE_MAC_INST_t *mac,
} }
// L2 Abstraction Layer // L2 Abstraction Layer
static int handle_dci(NR_UE_MAC_INST_t *mac, static nr_dci_format_t handle_dci(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci)
int cc_id,
unsigned int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci)
{ {
return nr_ue_process_dci_indication_pdu(mac, cc_id, gNB_index, frame, slot, dci); return nr_ue_process_dci_indication_pdu(mac, frame, slot, dci);
} }
static void handle_ssb_meas(NR_UE_MAC_INST_t *mac, uint8_t ssb_index, int16_t rsrp_dbm) static void handle_ssb_meas(NR_UE_MAC_INST_t *mac, uint8_t ssb_index, int16_t rsrp_dbm)
...@@ -1160,26 +1155,18 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info) ...@@ -1160,26 +1155,18 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info)
LOG_T(MAC, "[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); LOG_T(MAC, "[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
for (int i = 0; i < dl_info->dci_ind->number_of_dcis; i++) { for (int i = 0; i < dl_info->dci_ind->number_of_dcis; i++) {
LOG_T(MAC, ">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n", i, dl_info->dci_ind->number_of_dcis); LOG_T(MAC, ">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n", i, dl_info->dci_ind->number_of_dcis);
int8_t ret = handle_dci(mac, nr_dci_format_t dci_format = handle_dci(mac, dl_info->frame, dl_info->slot, dl_info->dci_ind->dci_list + i);
dl_info->cc_id,
dl_info->gNB_index,
dl_info->frame,
dl_info->slot,
dl_info->dci_ind->dci_list + i);
if (ret < 0)
continue;
fapi_nr_dci_indication_pdu_t *dci_index = dl_info->dci_ind->dci_list + i;
/* The check below filters out UL_DCIs which are being processed as DL_DCIs. */ /* The check below filters out UL_DCIs which are being processed as DL_DCIs. */
if (dci_index->dci_format != NR_DL_DCI_FORMAT_1_0 && dci_index->dci_format != NR_DL_DCI_FORMAT_1_1) { if (dci_format != NR_DL_DCI_FORMAT_1_0 && dci_format != NR_DL_DCI_FORMAT_1_1) {
LOG_D(NR_MAC, "We are filtering a UL_DCI to prevent it from being treated like a DL_DCI\n"); LOG_D(NR_MAC, "We are filtering a UL_DCI to prevent it from being treated like a DL_DCI\n");
continue; continue;
} }
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[dl_info->slot][dci_index->dci_format]; dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[dl_info->slot][dci_format];
g_harq_pid = def_dci_pdu_rel15->harq_pid; g_harq_pid = def_dci_pdu_rel15->harq_pid;
LOG_T(NR_MAC, "Setting harq_pid = %d and dci_index = %d (based on format)\n", g_harq_pid, dci_index->dci_format); LOG_T(NR_MAC, "Setting harq_pid = %d and dci_index = %d (based on format)\n", g_harq_pid, dci_format);
ret_mask |= (ret << FAPI_NR_DCI_IND); ret_mask |= (1 << FAPI_NR_DCI_IND);
AssertFatal(nr_ue_if_module_inst[dl_info->module_id] != NULL, "IF module is NULL!\n"); AssertFatal(nr_ue_if_module_inst[dl_info->module_id] != NULL, "IF module is NULL!\n");
fapi_nr_dl_config_request_t *dl_config = get_dl_config_request(mac, dl_info->slot); fapi_nr_dl_config_request_t *dl_config = get_dl_config_request(mac, dl_info->slot);
nr_scheduled_response_t scheduled_response = {.dl_config = dl_config, nr_scheduled_response_t scheduled_response = {.dl_config = dl_config,
...@@ -1191,71 +1178,71 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info) ...@@ -1191,71 +1178,71 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info)
memset(def_dci_pdu_rel15, 0, sizeof(*def_dci_pdu_rel15)); memset(def_dci_pdu_rel15, 0, sizeof(*def_dci_pdu_rel15));
} }
dl_info->dci_ind = NULL; dl_info->dci_ind = NULL;
} }
if (dl_info->rx_ind != NULL) { if (dl_info->rx_ind != NULL) {
for (int i = 0; i < dl_info->rx_ind->number_pdus; ++i) { for (int i = 0; i < dl_info->rx_ind->number_pdus; ++i) {
fapi_nr_rx_indication_body_t rx_indication_body = dl_info->rx_ind->rx_indication_body[i]; fapi_nr_rx_indication_body_t rx_indication_body = dl_info->rx_ind->rx_indication_body[i];
LOG_D(NR_MAC, LOG_D(NR_MAC,
"slot %d Sending DL indication to MAC. 1 PDU type %d of %d total number of PDUs \n", "slot %d Sending DL indication to MAC. 1 PDU type %d of %d total number of PDUs \n",
dl_info->slot, dl_info->slot,
rx_indication_body.pdu_type, rx_indication_body.pdu_type,
dl_info->rx_ind->number_pdus); dl_info->rx_ind->number_pdus);
switch(rx_indication_body.pdu_type){ switch(rx_indication_body.pdu_type){
case FAPI_NR_RX_PDU_TYPE_SSB: case FAPI_NR_RX_PDU_TYPE_SSB:
handle_rlm(rx_indication_body.ssb_pdu.radiolink_monitoring, handle_rlm(rx_indication_body.ssb_pdu.radiolink_monitoring,
dl_info->frame, dl_info->frame,
mac); mac);
if(rx_indication_body.ssb_pdu.decoded_pdu) { if(rx_indication_body.ssb_pdu.decoded_pdu) {
handle_ssb_meas(mac, handle_ssb_meas(mac,
rx_indication_body.ssb_pdu.ssb_index, rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.rsrp_dBm); rx_indication_body.ssb_pdu.rsrp_dBm);
ret_mask |= (handle_bcch_bch(mac, ret_mask |= (handle_bcch_bch(mac,
dl_info->cc_id, dl_info->cc_id,
dl_info->gNB_index, dl_info->gNB_index,
dl_info->phy_data, dl_info->phy_data,
rx_indication_body.ssb_pdu.pdu, rx_indication_body.ssb_pdu.pdu,
rx_indication_body.ssb_pdu.additional_bits, rx_indication_body.ssb_pdu.additional_bits,
rx_indication_body.ssb_pdu.ssb_index, rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.ssb_length, rx_indication_body.ssb_pdu.ssb_length,
rx_indication_body.ssb_pdu.ssb_start_subcarrier, rx_indication_body.ssb_pdu.ssb_start_subcarrier,
rx_indication_body.ssb_pdu.arfcn, rx_indication_body.ssb_pdu.arfcn,
rx_indication_body.ssb_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_SSB; rx_indication_body.ssb_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_SSB;
} }
break; break;
case FAPI_NR_RX_PDU_TYPE_SIB: case FAPI_NR_RX_PDU_TYPE_SIB:
ret_mask |= (handle_bcch_dlsch(mac, ret_mask |= (handle_bcch_dlsch(mac,
dl_info->cc_id, dl_info->gNB_index, dl_info->cc_id, dl_info->gNB_index,
rx_indication_body.pdsch_pdu.ack_nack, rx_indication_body.pdsch_pdu.ack_nack,
rx_indication_body.pdsch_pdu.pdu, rx_indication_body.pdsch_pdu.pdu,
rx_indication_body.pdsch_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB; rx_indication_body.pdsch_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB;
break; break;
case FAPI_NR_RX_PDU_TYPE_DLSCH: case FAPI_NR_RX_PDU_TYPE_DLSCH:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_DLSCH; ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
break; break;
case FAPI_NR_RX_PDU_TYPE_RAR: case FAPI_NR_RX_PDU_TYPE_RAR:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_RAR; ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_RAR;
if (!dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.ack_nack) if (!dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.ack_nack)
LOG_W(PHY, "Received a RAR-Msg2 but LDPC decode failed\n"); LOG_W(PHY, "Received a RAR-Msg2 but LDPC decode failed\n");
else else
LOG_I(PHY, "RAR-Msg2 decoded\n"); LOG_I(PHY, "RAR-Msg2 decoded\n");
break; break;
case FAPI_NR_CSIRS_IND: case FAPI_NR_CSIRS_IND:
ret_mask |= (handle_csirs_measurements(mac, ret_mask |= (handle_csirs_measurements(mac,
dl_info->frame, dl_info->frame,
dl_info->slot, dl_info->slot,
&rx_indication_body.csirs_measurements)) << FAPI_NR_CSIRS_IND; &rx_indication_body.csirs_measurements)) << FAPI_NR_CSIRS_IND;
break; break;
default: default:
break; break;
}
} }
dl_info->rx_ind = NULL;
} }
return ret_mask; dl_info->rx_ind = NULL;
}
return ret_mask;
} }
int nr_ue_dl_indication(nr_downlink_indication_t *dl_info) int nr_ue_dl_indication(nr_downlink_indication_t *dl_info)
......
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