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Commit 0b4716d7 authored by Raphael Defosseux's avatar Raphael Defosseux
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Merge remote-tracking branch 'origin/NR_UL_scheduling' into develop_integration_2020_w36

parents 88b3d0af 1a8e5314
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Showing with 124 additions and 104 deletions
openair1/PHY/NR_TRANSPORT/pucch_rx.c
View file @ 0b4716d7
......@@ -1440,12 +1440,15 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
}
printf("\n");
#endif
int64_t corr_tmp = 0;
for (int group=0;group<ngroup;group++) {
// do complex correlation
for (int aa=0;aa<Prx;aa++) {
prod_re[aa] = _mm256_srai_epi16(_mm256_adds_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp_re[aa][0]),
_mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp_im[aa][0])),5);
prod_im[aa] = _mm256_srai_epi16(_mm256_subs_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp2_im[aa][0]),
_mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp2_re[aa][0])),5);
prod_re[aa] = _mm256_srai_epi16(_mm256_adds_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp_re[aa][group]),
_mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp_im[aa][group])),5);
prod_im[aa] = _mm256_srai_epi16(_mm256_subs_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp2_im[aa][group]),
_mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp2_re[aa][group])),5);
#ifdef DEBUG_NR_PUCCH_RX
printf("prod_re[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa,
((int16_t*)&prod_re[aa])[0],((int16_t*)&prod_re[aa])[1],((int16_t*)&prod_re[aa])[2],((int16_t*)&prod_re[aa])[3],
......@@ -1470,26 +1473,27 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
}
int64_t corr_re=0,corr_im=0;
int64_t corr_tmp = 0;
for (int aa=0;aa<Prx;aa++) {
LOG_D(PHY,"pucch2 cw %d aa %d: (%d,%d)+(%d,%d) = (%d,%d)\n",cw,aa,
corr32_re[0][aa],corr32_im[0][aa],
LOG_D(PHY,"pucch2 cw %d group %d aa %d: (%d,%d)+(%d,%d) = (%d,%d)\n",cw,group,aa,
corr32_re[group][aa],corr32_im[0][aa],
((int16_t*)(&prod_re[aa]))[0],
((int16_t*)(&prod_im[aa]))[0],
corr32_re[0][aa]+((int16_t*)(&prod_re[0]))[0],
corr32_im[0][aa]+((int16_t*)(&prod_im[0]))[0]);
corr32_re[group][aa]+((int16_t*)(&prod_re[aa]))[0],
corr32_im[group][aa]+((int16_t*)(&prod_im[aa]))[0]);
corr_re = ( corr32_re[0][aa]+((int16_t*)(&prod_re[0]))[0]);
corr_im = ( corr32_im[0][aa]+((int16_t*)(&prod_im[0]))[0]);
corr_re = ( corr32_re[group][aa]+((int16_t*)(&prod_re[aa]))[0]);
corr_im = ( corr32_im[group][aa]+((int16_t*)(&prod_im[aa]))[0]);
corr_tmp += corr_re*corr_re + corr_im*corr_im;
}
} // aa loop
}// group loop
if (corr_tmp > corr) {
corr = corr_tmp;
cw_ML=cw;
}
}
} // cw loop
corr_dB = dB_fixed64((uint64_t)corr);
LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB);
decodedPayload[0]=(uint64_t)cw_ML;
......
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
View file @ 0b4716d7
......@@ -928,7 +928,17 @@ void nr_uci_encoding(uint64_t payload,
if (A<=11) {
// procedure in subclause 6.3.1.2.2 (UCI encoded by channel coding of small block lengths -> subclause 6.3.1.3.2)
// CRC bits are not attached, and coding small block lengths (subclause 5.3.3)
b[0] = encodeSmallBlock((uint16_t*)&payload,A);
uint64_t b0= encodeSmallBlock((uint16_t*)&payload,A);
// repetition for rate-matching up to 16 PRB
b[0] = b0 | (b0<<32);
b[1] = b[0];
b[2] = b[0];
b[3] = b[0];
b[4] = b[0];
b[5] = b[0];
b[6] = b[0];
b[7] = b[0];
AssertFatal(nrofPRB<=16,"Number of PRB >16\n");
} else if (A>=12) {
AssertFatal(A<65,"Polar encoding not supported yet for UCI with more than 64 bits\n");
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_UCI_PUCCH_MESSAGE_TYPE,
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ 0b4716d7
......@@ -38,6 +38,7 @@
#include "NR_MAC_gNB/nr_mac_gNB.h"
#include "NR_MAC_COMMON/nr_mac_extern.h"
#include "LAYER2/MAC/mac.h"
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
/*NFAPI*/
#include "nfapi_nr_interface.h"
......@@ -347,6 +348,70 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
return offset;
}
void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl, NR_mac_stats_t *stats, int target_snrx10) {
// TODO
int max_harq_rounds = 4; // TODO define macro
int num_ucis = UL_info->uci_ind.num_ucis;
nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list;
for (int i = 0; i < num_ucis; i++) {
switch (uci_list[i].pdu_type) {
case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break;
case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: {
//if (get_softmodem_params()->phy_test == 0) {
nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1;
// handle harq
int harq_idx_s = 0;
// tpc (power control)
sched_ctrl->tpc1 = nr_get_tpc(target_snrx10,uci_pdu->ul_cqi,30);
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) {
// search for the right harq process
for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES; harq_idx++) {
// if the gNB received ack with a good confidence
if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) &&
(uci_pdu->harq->harq_confidence_level == 0)) {
// toggle NDI and reset round
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
else
sched_ctrl->harq_processes[harq_idx].round++;
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
harq_idx_s = harq_idx + 1;
// if the max harq rounds was reached
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
stats->dlsch_errors++;
}
break;
}
// if feedback slot processing is aborted
else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) &&
(sched_ctrl->harq_processes[harq_idx].is_waiting)) {
sched_ctrl->harq_processes[harq_idx].round++;
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
}
}
}
//}
break;
}
case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break;
}
}
UL_info->uci_ind.num_ucis = 0;
}
/* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */
void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ 0b4716d7
......@@ -298,65 +298,6 @@ void handle_nr_ul_harq(uint16_t slot, NR_UE_sched_ctrl_t *sched_ctrl, NR_mac_sta
LOG_E(MAC,"Incorrect ULSCH HARQ process %d or invalid state %d\n",hrq_id,cur_harq->state);
}
void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl, int target_snrx10) {
// TODO
int max_harq_rounds = 4; // TODO define macro
int num_ucis = UL_info->uci_ind.num_ucis;
nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list;
for (int i = 0; i < num_ucis; i++) {
switch (uci_list[i].pdu_type) {
case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break;
case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: {
//if (get_softmodem_params()->phy_test == 0) {
nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1;
// handle harq
int harq_idx_s = 0;
// tpc (power control)
sched_ctrl->tpc1 = nr_get_tpc(target_snrx10,uci_pdu->ul_cqi,30);
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) {
// search for the right harq process
for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES; harq_idx++) {
// if the gNB received ack with a good confidence or if the max harq rounds was reached
if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
if (((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) &&
(uci_pdu->harq->harq_confidence_level == 0)) ||
(sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) {
// toggle NDI and reset round
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
else
sched_ctrl->harq_processes[harq_idx].round++;
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
harq_idx_s = harq_idx + 1;
break;
}
// if feedback slot processing is aborted
else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) &&
(sched_ctrl->harq_processes[harq_idx].is_waiting)) {
sched_ctrl->harq_processes[harq_idx].round++;
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
}
}
}
//}
break;
}
case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break;
}
}
UL_info->uci_ind.num_ucis = 0;
}
/*
* When data are received on PHY and transmitted to MAC
*/
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ 0b4716d7
......@@ -342,5 +342,5 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
void handle_nr_ul_harq(uint16_t slot, NR_UE_sched_ctrl_t *sched_ctrl, NR_mac_stats_t *stats, nfapi_nr_crc_t crc_pdu);
void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl, int target_snrx10);
void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl, NR_mac_stats_t *stats, int target_snrx10);
#endif /*__LAYER2_NR_MAC_PROTO_H__*/
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
View file @ 0b4716d7
......@@ -181,7 +181,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot);
handle_nr_rach(UL_info);
handle_nr_uci(UL_info,&mac->UE_list.UE_sched_ctrl[0],mac->pucch_target_snrx10);
handle_nr_uci(UL_info,&mac->UE_list.UE_sched_ctrl[0],&mac->UE_list.mac_stats[0],mac->pucch_target_snrx10);
// clear HI prior to handling ULSCH
mac->UL_dci_req[CC_id].numPdus = 0;
handle_nr_ulsch(UL_info, &mac->UE_list.UE_sched_ctrl[0],&mac->UE_list.mac_stats[0]);
......
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