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Commit 89e8ce29 authored by Niccolò Iardella's avatar Niccolò Iardella
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Split positioning() in positioning() and intraslice_sharing()

parent cb2b43ca
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openair2/LAYER2/MAC/pre_processor.c
View file @ 89e8ce29
...@@ -616,7 +616,6 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -616,7 +616,6 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int min_rb_unit[MAX_NUM_CCs], int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX]) uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX])
{ {
...@@ -630,6 +629,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -630,6 +629,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
uint16_t available_rbs; uint16_t available_rbs;
uint8_t rbs_retx[MAX_NUM_CCs]; uint8_t rbs_retx[MAX_NUM_CCs];
uint16_t average_rbs_per_user[MAX_NUM_CCs]; uint16_t average_rbs_per_user[MAX_NUM_CCs];
int total_ue_count[MAX_NUM_CCs];
int ue_count_newtx[MAX_NUM_CCs]; int ue_count_newtx[MAX_NUM_CCs];
int ue_count_retx[MAX_NUM_CCs]; int ue_count_retx[MAX_NUM_CCs];
uint8_t ue_retx_flag[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; uint8_t ue_retx_flag[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
...@@ -785,93 +785,55 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id, ...@@ -785,93 +785,55 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id,
slice_id_t slice_id, slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs], int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs], int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX], uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]) { uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]) {
int UE_id, CC_id; int UE_id, CC_id;
int i; int i;
uint8_t transmission_mode; uint8_t transmission_mode;
uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX]; uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX];
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
rnti_t rnti;
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
decode_slice_positioning(Mod_id, slice_id, slice_allocation_mask); decode_slice_positioning(Mod_id, slice_id, slice_allocation_mask);
//Allocation to UEs is done in 2 rounds, // Try to allocate accounted RBs
// 1st stage: average number of RBs allocated to each UE for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
// 2nd stage: remaining RBs are allocated to high priority UEs
for (int r1 = 0; r1 < 2; r1++) {
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[i][UE_id];
if (r1 == 0) {
nb_rbs_remaining[CC_id][UE_id] =
nb_rbs_accounted[CC_id][UE_id];
} else { // rb required based only on the buffer - rb allocated in the 1st round + extra reaming rb form the 1st round
nb_rbs_remaining[CC_id][UE_id] =
nb_rbs_required[CC_id][UE_id] -
nb_rbs_accounted[CC_id][UE_id] +
nb_rbs_remaining[CC_id][UE_id];
if (nb_rbs_remaining[CC_id][UE_id] < 0)
abort();
}
if (nb_rbs_required[CC_id][UE_id] > 0)
LOG_D(MAC,
"round %d : nb_rbs_remaining[%d][%d]= %d (accounted %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
r1, CC_id, UE_id,
nb_rbs_remaining[CC_id][UE_id],
nb_rbs_accounted[CC_id][UE_id],
nb_rbs_required[CC_id][UE_id],
UE_list->UE_sched_ctrl[UE_id].pre_nb_available_rbs[CC_id],
N_RBG[CC_id],
min_rb_unit[CC_id]);
}
}
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[i][UE_id];
// if there are UEs with traffic
if (total_ue_count[CC_id] > 0) {
rnti = UE_RNTI(Mod_id, UE_id); if (UE_RNTI(Mod_id, UE_id) == NOT_A_RNTI) continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue;
if (!ue_slice_membership(UE_id, slice_id)) continue;
// LOG_D(MAC,"UE %d rnti 0x\n", UE_id, rnti ); for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
if (rnti == NOT_A_RNTI) CC_id = UE_list->ordered_CCids[i][UE_id];
continue; nb_rbs_remaining[CC_id][UE_id] = nb_rbs_accounted[CC_id][UE_id];
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) transmission_mode = get_tmode(Mod_id, CC_id, UE_id);
continue;
if (!ue_slice_membership(UE_id, slice_id))
continue;
transmission_mode = get_tmode(Mod_id, CC_id, UE_id); if (nb_rbs_required[CC_id][UE_id] > 0)
LOG_D(MAC,
// retransmission in data channels "Step 1: nb_rbs_remaining[%d][%d]= %d (accounted %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
// control channel in the 1st transmission CC_id,
// data channel for all TM UE_id,
LOG_T(MAC, "calling dlsch_scheduler_pre_processor_allocate .. \n "); nb_rbs_remaining[CC_id][UE_id],
dlsch_scheduler_pre_processor_allocate(Mod_id, nb_rbs_accounted[CC_id][UE_id],
UE_id, nb_rbs_required[CC_id][UE_id],
CC_id, UE_list->UE_sched_ctrl[UE_id].pre_nb_available_rbs[CC_id],
N_RBG[CC_id], N_RBG[CC_id],
min_rb_unit[CC_id], min_rb_unit[CC_id]);
nb_rbs_required,
nb_rbs_remaining, LOG_T(MAC, "calling dlsch_scheduler_pre_processor_allocate .. \n ");
rballoc_sub, dlsch_scheduler_pre_processor_allocate(Mod_id,
slice_allocation_mask, UE_id,
MIMO_mode_indicator); CC_id,
N_RBG[CC_id],
min_rb_unit[CC_id],
nb_rbs_required,
nb_rbs_remaining,
rballoc_sub,
slice_allocation_mask,
MIMO_mode_indicator);
#ifdef TM5 #ifdef TM5
// data chanel TM5: to be revisited // data chanel TM5: to be revisited
...@@ -1035,10 +997,231 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id, ...@@ -1035,10 +997,231 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id,
} }
} }
#endif #endif
} // total_ue_count }
} // CC }
} // UE }
} // end of for for r1 and r2
void dlsch_scheduler_pre_processor_intraslice_sharing(module_id_t Mod_id,
slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]) {
int UE_id, CC_id;
int i;
uint8_t transmission_mode;
uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX];
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
decode_slice_positioning(Mod_id, slice_id, slice_allocation_mask);
// Remaining RBs are allocated to high priority UEs
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
if (UE_RNTI(Mod_id, UE_id) == NOT_A_RNTI) continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue;
if (!ue_slice_membership(UE_id, slice_id)) continue;
for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[i][UE_id];
nb_rbs_remaining[CC_id][UE_id] =
nb_rbs_required[CC_id][UE_id] - nb_rbs_accounted[CC_id][UE_id] + nb_rbs_remaining[CC_id][UE_id];
if (nb_rbs_remaining[CC_id][UE_id] < 0)
abort();
transmission_mode = get_tmode(Mod_id, CC_id, UE_id);
if (nb_rbs_required[CC_id][UE_id] > 0)
LOG_D(MAC,
"Step 2: nb_rbs_remaining[%d][%d]= %d (accounted %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
CC_id,
UE_id,
nb_rbs_remaining[CC_id][UE_id],
nb_rbs_accounted[CC_id][UE_id],
nb_rbs_required[CC_id][UE_id],
UE_list->UE_sched_ctrl[UE_id].pre_nb_available_rbs[CC_id],
N_RBG[CC_id],
min_rb_unit[CC_id]);
LOG_T(MAC, "calling dlsch_scheduler_pre_processor_allocate .. \n ");
dlsch_scheduler_pre_processor_allocate(Mod_id,
UE_id,
CC_id,
N_RBG[CC_id],
min_rb_unit[CC_id],
nb_rbs_required,
nb_rbs_remaining,
rballoc_sub,
slice_allocation_mask,
MIMO_mode_indicator);
#ifdef TM5
// data chanel TM5: to be revisited
if ((round == 0) &&
(transmission_mode == 5) &&
(ue_sched_ctl->dl_pow_off[CC_id] != 1)) {
for (j = 0; j < N_RBG[CC_id]; j += 2) {
if ((((j == (N_RBG[CC_id] - 1))
&& (rballoc_sub[CC_id][j] == 0)
&& (ue_sched_ctl->
rballoc_sub_UE[CC_id][j] == 0))
|| ((j < (N_RBG[CC_id] - 1))
&& (rballoc_sub[CC_id][j + 1] == 0)
&&
(ue_sched_ctl->rballoc_sub_UE
[CC_id][j + 1] == 0)))
&& (nb_rbs_remaining[CC_id][UE_id]
> 0)) {
for (i = UE_list->next[UE_id + 1]; i >= 0;
i = UE_list->next[i]) {
UE_id2 = i;
rnti2 = UE_RNTI(Mod_id, UE_id2);
ue_sched_ctl2 =
&UE_list->UE_sched_ctrl[UE_id2];
round2 = ue_sched_ctl2->round[CC_id];
if (rnti2 == NOT_A_RNTI)
continue;
if (UE_list->
UE_sched_ctrl
[UE_id2].ul_out_of_sync == 1)
continue;
eNB_UE_stats2 =
UE_list->
eNB_UE_stats[CC_id][UE_id2];
//mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,frameP,subframeP,&harq_pid2,&round2,0);
if ((mac_eNB_get_rrc_status
(Mod_id,
rnti2) >= RRC_RECONFIGURED)
&& (round2 == 0)
&&
(get_tmode(Mod_id, CC_id, UE_id2)
== 5)
&& (ue_sched_ctl->
dl_pow_off[CC_id] != 1)) {
if ((((j == (N_RBG[CC_id] - 1))
&&
(ue_sched_ctl->rballoc_sub_UE
[CC_id][j] == 0))
|| ((j < (N_RBG[CC_id] - 1))
&&
(ue_sched_ctl->
rballoc_sub_UE[CC_id][j +
1]
== 0)))
&&
(nb_rbs_remaining
[CC_id]
[UE_id2] > 0)) {
if ((((eNB_UE_stats2->
DL_pmi_single ^
eNB_UE_stats1->
DL_pmi_single)
<< (14 - j)) & 0xc000) == 0x4000) { //MU-MIMO only for 25 RBs configuration
rballoc_sub[CC_id][j] = 1;
ue_sched_ctl->
rballoc_sub_UE[CC_id]
[j] = 1;
ue_sched_ctl2->
rballoc_sub_UE[CC_id]
[j] = 1;
MIMO_mode_indicator[CC_id]
[j] = 0;
if (j < N_RBG[CC_id] - 1) {
rballoc_sub[CC_id][j +
1] =
1;
ue_sched_ctl->
rballoc_sub_UE
[CC_id][j + 1] = 1;
ue_sched_ctl2->rballoc_sub_UE
[CC_id][j + 1] = 1;
MIMO_mode_indicator
[CC_id][j + 1]
= 0;
}
ue_sched_ctl->
dl_pow_off[CC_id]
= 0;
ue_sched_ctl2->
dl_pow_off[CC_id]
= 0;
if ((j == N_RBG[CC_id] - 1)
&& ((N_RB_DL == 25)
|| (N_RB_DL ==
50))) {
nb_rbs_remaining
[CC_id][UE_id] =
nb_rbs_remaining
[CC_id][UE_id] -
min_rb_unit[CC_id]
+ 1;
ue_sched_ctl->pre_nb_available_rbs
[CC_id] =
ue_sched_ctl->pre_nb_available_rbs
[CC_id] +
min_rb_unit[CC_id]
- 1;
nb_rbs_remaining
[CC_id][UE_id2] =
nb_rbs_remaining
[CC_id][UE_id2] -
min_rb_unit[CC_id]
+ 1;
ue_sched_ctl2->pre_nb_available_rbs
[CC_id] =
ue_sched_ctl2->pre_nb_available_rbs
[CC_id] +
min_rb_unit[CC_id]
- 1;
} else {
nb_rbs_remaining
[CC_id][UE_id] =
nb_rbs_remaining
[CC_id][UE_id] - 4;
ue_sched_ctl->pre_nb_available_rbs
[CC_id] =
ue_sched_ctl->pre_nb_available_rbs
[CC_id] + 4;
nb_rbs_remaining
[CC_id][UE_id2] =
nb_rbs_remaining
[CC_id][UE_id2] -
4;
ue_sched_ctl2->pre_nb_available_rbs
[CC_id] =
ue_sched_ctl2->pre_nb_available_rbs
[CC_id] + 4;
}
break;
}
}
}
}
}
}
}
#endif
}
}
} }
// This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done // This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
...@@ -1056,10 +1239,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1056,10 +1239,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
int N_RBG[MAX_NUM_CCs]; int N_RBG[MAX_NUM_CCs];
int min_rb_unit[MAX_NUM_CCs]; int min_rb_unit[MAX_NUM_CCs];
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX]; uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX];
uint8_t total_ue_count[MAX_NUM_CCs];
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; // If TM5 is revisited, we can move this inside accounting uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; // If TM5 is revisited, we can move this inside accounting
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
UE_sched_ctrl *ue_sched_ctl; UE_sched_ctrl *ue_sched_ctl;
...@@ -1101,7 +1284,6 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1101,7 +1284,6 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
// This procedure decides the number of RBs to allocate // This procedure decides the number of RBs to allocate
dlsch_scheduler_pre_processor_accounting(Mod_id, slice_id, frameP, subframeP, dlsch_scheduler_pre_processor_accounting(Mod_id, slice_id, frameP, subframeP,
min_rb_unit, min_rb_unit,
total_ue_count,
nb_rbs_required, nb_rbs_required,
nb_rbs_accounted); nb_rbs_accounted);
// POSITIONING // POSITIONING
...@@ -1109,12 +1291,23 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1109,12 +1291,23 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
dlsch_scheduler_pre_processor_positioning(Mod_id, slice_id, dlsch_scheduler_pre_processor_positioning(Mod_id, slice_id,
N_RBG, N_RBG,
min_rb_unit, min_rb_unit,
total_ue_count,
nb_rbs_required, nb_rbs_required,
nb_rbs_accounted, nb_rbs_accounted,
nb_rbs_remaining,
rballoc_sub, rballoc_sub,
MIMO_mode_indicator); MIMO_mode_indicator);
// SHARING
// If there are available RBs left in the slice, allocate them to the highest priority UEs
dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id,
N_RBG,
min_rb_unit,
nb_rbs_required,
nb_rbs_accounted,
nb_rbs_remaining,
rballoc_sub,
MIMO_mode_indicator);
#ifdef TM5 #ifdef TM5
// This has to be revisited!!!! // This has to be revisited!!!!
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
......
openair2/LAYER2/MAC/proto.h
View file @ 89e8ce29
...@@ -233,7 +233,6 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, ...@@ -233,7 +233,6 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int min_rb_unit[MAX_NUM_CCs], int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX]); uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX]);
...@@ -241,12 +240,22 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id, ...@@ -241,12 +240,22 @@ void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id,
slice_id_t slice_id, slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs], int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs], int min_rb_unit[MAX_NUM_CCs],
uint8_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX], uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX], uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]); uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]);
void dlsch_scheduler_pre_processor_intraslice_sharing(module_id_t Mod_id,
slice_id_t slice_id,
int N_RBG[MAX_NUM_CCs],
int min_rb_unit[MAX_NUM_CCs],
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_accounted[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t nb_rbs_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint8_t rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],
uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]);
void dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id, void dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id,
int UE_id, int UE_id,
uint8_t CC_id, uint8_t CC_id,
......
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