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wangwenhui
OpenXG-RAN
Commits
8ba3ba91
Commit
8ba3ba91
authored
Sep 03, 2020
by
Florian Kaltenberger
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updating conf file for CI
parent
da3dd6b8
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1
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17 additions
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5 deletions
+17
-5
ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf
ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf
+17
-5
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ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf
View file @
8ba3ba91
...
...
@@ -71,6 +71,12 @@ gNBs =
initialDLBWPmappingType_2
=
0
;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2
=
54
;
initialDLBWPk0_3
=
0
;
initialDLBWPmappingType_3
=
0
;
#this is SS=1,L=4
initialDLBWPstartSymbolAndLength_3
=
57
;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand
=
78
;
...
...
@@ -105,8 +111,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow
=
4
;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#
0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7
=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
=
3
;
#
1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8
=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
=
4
;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB
=
15
;
#ra_ContentionResolutionTimer
...
...
@@ -114,8 +120,8 @@ gNBs =
ra_ContentionResolutionTimer
=
7
;
rsrp_ThresholdSSB
=
19
;
#prach-RootSequenceIndex_PR
#
0 = 839, 1
= 139
prach_RootSequenceIndex_PR
=
1
;
#
1 = 839, 2
= 139
prach_RootSequenceIndex_PR
=
2
;
prach_RootSequenceIndex
=
1
;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
...
...
@@ -135,6 +141,10 @@ gNBs =
# this is SS=0 L=12
initialULBWPstartSymbolAndLength_1
=
69
;
initialULBWPk2_2
=
7
;
initialULBWPmappingType_2
=
1
;
# this is SS=10 L=4
initialULBWPstartSymbolAndLength_2
=
52
;
msg3_DeltaPreamble
=
1
;
p0_NominalWithGrant
=-
90
;
...
...
@@ -237,6 +247,8 @@ RUs = (
max_pdschReferenceSignalPower
= -
27
;
max_rxgain
=
114
;
eNB_instances
= [
0
];
#beamforming 1x4 matrix:
bf_weights
= [
0
x00007fff
,
0
x0000
,
0
x0000
,
0
x0000
];
sdr_addrs
=
"addr=192.168.10.2,second_addr=192.168.20.2"
;
clock_src
=
"external"
;
}
...
...
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