Add phytest preprocessor

The phytest preprocessor schedules only one UE, as many RBs as possible
(largest continuous RB region), with a fixed MCS and time domain
allocation.

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c

@@ -500,7 +500,6 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
                                                     0);
   sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
   if (sched_ctrl->num_total_bytes == 0
-      && !get_softmodem_params()->phy_test
       && !sched_ctrl->ta_apply) /* If TA should be applied, give at least one RB */
     return;
   LOG_D(MAC,
@@ -645,7 +644,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
     if (frame >= (sched_ctrl->ta_frame + 10) % 1023)
       sched_ctrl->ta_apply = true; /* the timer is reset once TA CE is scheduled */
 
-    if (sched_ctrl->rbSize <= 0 && !get_softmodem_params()->phy_test)
+    if (sched_ctrl->rbSize <= 0)
       continue;
 
     const rnti_t rnti = UE_info->rnti[UE_id];
@@ -743,7 +742,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
        * nr_generate_dlsch_pdu() checks for ta_apply and add TA CE if necessary */
       const int ta_len = (sched_ctrl->ta_apply) ? 2 : 0;
 
-      /* Get RLC data TODO: remove random data retrieval */
+      /* Get RLC data */
       int header_length_total = 0;
       int header_length_last = 0;
       int sdu_length_total = 0;

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c

@@ -252,6 +252,106 @@ void nr_schedule_css_dlsch_phytest(module_id_t   module_idP,
   }
 }
 
+/* schedules whole bandwidth for first user, all the time */
+void nr_preprocessor_phytest(module_id_t module_id,
+                             frame_t frame,
+                             sub_frame_t slot,
+                             int num_slots_per_tdd)
+{
+  if (slot != 1)
+    return; /* only schedule in slot 1 for now */
+  NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
+  const int UE_id = 0;
+  const int CC_id = 0;
+  AssertFatal(UE_info->active[UE_id],
+              "%s(): expected UE %d to be active\n",
+              __func__,
+              UE_id);
+
+  NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+  /* find largest unallocated chunk */
+  const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
+  int rbStart = 0;
+  int tStart = 0;
+  int rbSize = 0;
+  uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
+  /* find largest unallocated RB region */
+  do {
+    /* advance to first free RB */
+    while (tStart < bwpSize && vrb_map[tStart])
+      tStart++;
+    /* find maximum rbSize at current rbStart */
+    int tSize = 1;
+    while (tStart + tSize < bwpSize && !vrb_map[tStart + tSize])
+      tSize++;
+    if (tSize > rbSize) {
+      rbStart = tStart;
+      rbSize = tSize;
+    }
+    tStart += tSize;
+  } while (tStart < bwpSize);
+
+  sched_ctrl->num_total_bytes = 0;
+  const int lcid = DL_SCH_LCID_DTCH;
+  const uint16_t rnti = UE_info->rnti[UE_id];
+  /* update sched_ctrl->num_total_bytes so that postprocessor schedules data,
+   * if available */
+  sched_ctrl->rlc_status[lcid] = mac_rlc_status_ind(module_id,
+                                                    rnti,
+                                                    module_id,
+                                                    frame,
+                                                    slot,
+                                                    ENB_FLAG_YES,
+                                                    MBMS_FLAG_NO,
+                                                    lcid,
+                                                    0,
+                                                    0);
+  sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
+
+  const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
+  sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
+  uint8_t nr_of_candidates;
+  find_aggregation_candidates(&sched_ctrl->aggregation_level,
+                              &nr_of_candidates,
+                              sched_ctrl->search_space);
+  sched_ctrl->coreset = get_coreset(
+      sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */);
+  const int cid = sched_ctrl->coreset->controlResourceSetId;
+  const uint16_t Y = UE_info->Y[UE_id][cid][RC.nrmac[module_id]->current_slot];
+  const int m = UE_info->num_pdcch_cand[UE_id][cid];
+  sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
+                                  sched_ctrl->active_bwp,
+                                  sched_ctrl->coreset,
+                                  sched_ctrl->aggregation_level,
+                                  Y,
+                                  m,
+                                  nr_of_candidates);
+  AssertFatal(sched_ctrl->cce_index >= 0,
+              "%s(): could not find CCE for UE %d\n",
+              __func__,
+              UE_id);
+
+  nr_acknack_scheduling(module_id,
+                        UE_id,
+                        frame,
+                        slot,
+                        num_slots_per_tdd,
+                        &sched_ctrl->pucch_sched_idx,
+                        &sched_ctrl->pucch_occ_idx);
+  AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
+
+  sched_ctrl->rbStart = rbStart;
+  sched_ctrl->rbSize = rbSize;
+  sched_ctrl->time_domain_allocation = 2;
+  sched_ctrl->mcsTableIdx = 0;
+  sched_ctrl->mcs = 9;
+  sched_ctrl->numDmrsCdmGrpsNoData = 1;
+
+  /* mark the corresponding RBs as used */
+  for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
+    vrb_map[rb + sched_ctrl->rbStart] = 1;
+}
+
 int configure_fapi_dl_pdu_phytest(int Mod_idP,
                                   nfapi_nr_dl_tti_request_body_t *dl_req,
                                   NR_sched_pucch *pucch_sched,

openair2/LAYER2/NR_MAC_gNB/mac_proto.h

@@ -130,6 +130,13 @@ uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs);
 
 /////// Phy test scheduler ///////
 
+/* \brief preprocessor for phytest: schedules UE_id 0 with fixed MCS on all
+ * freq resources */
+void nr_preprocessor_phytest(module_id_t module_id,
+                             frame_t frame,
+                             sub_frame_t slot,
+                             int num_slots_per_tdd);
+
 void nr_schedule_css_dlsch_phytest(module_id_t   module_idP,
                                    frame_t       frameP,
                                    sub_frame_t   subframeP);

openair2/LAYER2/NR_MAC_gNB/main.c

@@ -82,6 +82,9 @@ void mac_top_init_gNB(void)
         
       RC.nrmac[i]->ul_handle = 0;
 
+      if (get_softmodem_params()->phy_test)
+        RC.nrmac[i]->pre_processor_dl = nr_preprocessor_phytest;
+      else
         RC.nrmac[i]->pre_processor_dl = nr_simple_dlsch_preprocessor;
 
     }//END for (i = 0; i < RC.nb_nr_macrlc_inst; i++)