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Commit 4e8fa97d authored by Francesco Mani's avatar Francesco Mani
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getting rid of frame_rx and slot_rx in gnb scheduler

parent 96f78fee
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Showing with 67 additions and 86 deletions
openair1/SCHED_NR/phy_procedures_nr_gNB.c
View file @ 4e8fa97d
......@@ -294,11 +294,11 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
stop_meas(&gNB->ulsch_decoding_stats);
if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){
LOG_D(PHY, "ULSCH %d in error\n",ULSCH_id);
LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id);
nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1);
}
else if(gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->b!=NULL){
LOG_D(PHY, "ULSCH received ok \n");
LOG_I(PHY, "ULSCH received ok \n");
nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 0);
}
}
......
openair2/LAYER2/NR_MAC_gNB/config.c
View file @ 4e8fa97d
......@@ -298,30 +298,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
else LOG_I(PHY,"TDD has been properly configurated\n");
}
/*
// PDCCH-ConfigCommon
cfg->pdcch_config.controlResourceSetZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero;
cfg->pdcch_config.searchSpaceZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero;
// PDSCH-ConfigCommon
cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;
cfg->pdsch_config.dmrs_TypeA_Position.value = scc->dmrs_TypeA_Position;
AssertFatal(cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value<=NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS,"illegal TimeDomainAllocation count %d\n",cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value);
for (int i=0;i<cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value;i++) {
cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_k0[i].value=*scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0;
cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_mappingType[i].value=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType;
cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_startSymbolAndLength[i].value=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
}
// PUSCH-ConfigCommon
cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count;
cfg->pusch_config.dmrs_TypeA_Position.value = scc->dmrs_TypeA_Position+2;
AssertFatal(cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value<=NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS,"illegal TimeDomainAllocation count %d\n",cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value);
for (int i=0;i<cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value;i++) {
cfg->pusch_config.PUSCHTimeDomainResourceAllocation_k2[i].value=*scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2;
}*/
}
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @ 4e8fa97d
......@@ -290,12 +290,15 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
void nr_schedule_pusch(int Mod_idP,
int UE_id,
int num_slots_per_tdd,
int ul_slots,
frame_t frameP,
sub_frame_t slotP) {
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
NR_sched_pusch *pusch = UE_list->UE_sched_ctrl[UE_id].sched_pusch;
int k = slotP + ul_slots - num_slots_per_tdd;
NR_sched_pusch *pusch = &UE_list->UE_sched_ctrl[UE_id].sched_pusch[k];
if ((pusch->active == true) && (frameP == pusch->frame) && (slotP == pusch->slot)) {
UL_tti_req->SFN = pusch->frame;
UL_tti_req->Slot = pusch->slot;
......@@ -303,13 +306,15 @@ void nr_schedule_pusch(int Mod_idP,
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu = pusch->pusch_pdu;
UL_tti_req->n_pdus+=1;
memset((void *) UE_list->UE_sched_ctrl[UE_id].sched_pusch,
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pusch[k],
0, sizeof(NR_sched_pusch));
}
}
void nr_schedule_pucch(int Mod_idP,
int UE_id,
int nr_ulmix_slots,
frame_t frameP,
sub_frame_t slotP) {
......@@ -326,15 +331,12 @@ void nr_schedule_pucch(int Mod_idP,
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_sched_pucch *curr_pucch;
int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
nr_ulmix_slots++;
for (int k=0; k<nr_ulmix_slots; k++) {
curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP;
UL_tti_req->SFN = curr_pucch->frame;
UL_tti_req->Slot = curr_pucch->ul_slot;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t);
nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pucch_pdu;
......@@ -343,7 +345,7 @@ void nr_schedule_pucch(int Mod_idP,
O_ack = curr_pucch->dai_c;
O_uci = O_ack; // for now we are just sending acknacks in pucch
LOG_I(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP);
LOG_D(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP);
nr_configure_pucch(pucch_pdu,
scc,
......@@ -353,11 +355,15 @@ void nr_schedule_pucch(int Mod_idP,
O_ack,
SR_flag);
curr_pucch->dai_c = 0;
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
0,
sizeof(NR_sched_pucch));
}
}
}
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){
if((bitmap>>slot)&0x01)
......@@ -367,15 +373,12 @@ bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){
}
void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
frame_t frame_rxP,
sub_frame_t slot_rxP,
frame_t frame_txP,
sub_frame_t slot_txP){
frame_t frame,
sub_frame_t slot){
//printf("gNB_dlsch_ulsch_scheduler frameRX %d slotRX %d frameTX %d slotTX %d\n",frame_rxP,slot_rxP,frame_txP,slot_txP);
protocol_ctxt_t ctxt;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP);
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
int CC_id;
int UE_id;
......@@ -397,11 +400,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
nr_ulmix_slots++;
if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
if (slot== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
for (int k=0; k<nr_ulmix_slots; k++) {
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
0,
sizeof(NR_sched_pucch));
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pusch[k],
0,
sizeof(NR_sched_pusch));
}
}
......@@ -411,28 +417,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
pdcp_run(&ctxt);
//rrc_rx_tx(&ctxt, CC_id);
RC.nrmac[module_idP]->frame = frame_rxP;
RC.nrmac[module_idP]->slot = slot_rxP;
dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
// hardcoding dlsch to be in slot 1
if (!(slot_txP%num_slots_per_tdd)) {
if(slot_txP==0)
if (!(slot%num_slots_per_tdd)) {
if(slot==0) {
*dlsch_in_slot_bitmap = 0x02;
else
*dlsch_in_slot_bitmap = 0x00;
}
// hardcoding ulsch to be in slot 8
if (!(slot_rxP%num_slots_per_tdd)) {
if(slot_rxP==0)
*ulsch_in_slot_bitmap = 0x100;
else
}
else {
*dlsch_in_slot_bitmap = 0x00;
*ulsch_in_slot_bitmap = 0x00;
}
}
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
......@@ -443,7 +441,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
memset(cc[CC_id].vrb_map, 0, 100);
memset(cc[CC_id].vrb_map_UL, 0, 100);
clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP);
clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame, slot);
}
// refresh UE list based on UEs dropped by PHY in previous subframe
......@@ -461,13 +459,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
*/
// This schedules MIB
if((slot_txP == 0) && (frame_txP & 7) == 0){
schedule_nr_mib(module_idP, frame_txP, slot_txP);
if((slot == 0) && (frame & 7) == 0){
schedule_nr_mib(module_idP, frame, slot);
}
// This schedule PRACH if we are not in phy_test mode
if (get_softmodem_params()->phy_test == 0)
schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP);
schedule_nr_prach(module_idP, frame, slot);
// This schedule SR
// TODO
......@@ -478,8 +476,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// This schedule RA procedure if not in phy_test mode
// Otherwise already consider 5G already connected
if (get_softmodem_params()->phy_test == 0) {
nr_schedule_RA(module_idP, frame_txP, slot_txP);
nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP);
nr_schedule_RA(module_idP, frame, slot);
nr_schedule_reception_msg3(module_idP, 0, frame, slot);
}
else
UE_list->fiveG_connected[UE_id] = true;
......@@ -504,20 +502,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// This schedules the DCI for Uplink and subsequently PUSCH
if (UE_list->fiveG_connected[UE_id]) {
int tda = 1; // time domain assignment hardcoded for now
schedule_fapi_ul_pdu(module_idP, frame_txP, slot_txP, num_slots_per_tdd, tda);
nr_schedule_pusch(module_idP, UE_id, frame_rxP, slot_rxP);
schedule_fapi_ul_pdu(module_idP, frame, slot, num_slots_per_tdd, nr_ulmix_slots, tda);
nr_schedule_pusch(module_idP, UE_id, num_slots_per_tdd, nr_ulmix_slots, frame, slot);
}
if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd;
nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched);
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot%num_slots_per_tdd))) {
ue_sched_ctl->current_harq_pid = slot % num_slots_per_tdd;
nr_update_pucch_scheduling(module_idP, UE_id, frame, slot, num_slots_per_tdd,&pucch_sched);
nr_schedule_uss_dlsch_phytest(module_idP, frame, slot, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
// resetting ta flag
gNB->ta_len = 0;
}
if (UE_list->fiveG_connected[UE_id])
nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
nr_schedule_pucch(module_idP, UE_id, nr_ulmix_slots, frame, slot);
/*
// Allocate CCEs for good after scheduling is done
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ 4e8fa97d
......@@ -800,6 +800,7 @@ void schedule_fapi_ul_pdu(int Mod_idP,
frame_t frameP,
sub_frame_t slotP,
int num_slots_per_tdd,
int ul_slots,
int time_domain_assignment) {
gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
......@@ -847,7 +848,8 @@ void schedule_fapi_ul_pdu(int Mod_idP,
uint16_t rnti = UE_list->rnti[UE_id];
NR_sched_pusch *pusch_sched = UE_list->UE_sched_ctrl[UE_id].sched_pusch;
int first_ul_slot = num_slots_per_tdd - ul_slots;
NR_sched_pusch *pusch_sched = &UE_list->UE_sched_ctrl[UE_id].sched_pusch[slotP+K2-first_ul_slot];
pusch_sched->frame = frameP;
pusch_sched->slot = slotP + K2;
pusch_sched->active = true;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 4e8fa97d
......@@ -1467,7 +1467,15 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
sizeof(NR_UE_sched_ctrl_t));
UE_list->UE_sched_ctrl[UE_id].ul_rssi = 0;
UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch));
UE_list->UE_sched_ctrl[UE_id].sched_pusch = (NR_sched_pusch *)malloc(sizeof(NR_sched_pusch));
UE_list->UE_sched_ctrl[UE_id].sched_pusch = (NR_sched_pusch *)malloc(num_slots_ul*sizeof(NR_sched_pusch));
for (int k=0; k<num_slots_ul; k++) {
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
0,
sizeof(NR_sched_pucch));
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pusch[k],
0,
sizeof(NR_sched_pusch));
}
LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
mod_idP,
UE_id,
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ 4e8fa97d
......@@ -306,6 +306,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
UE_scheduling_control->tpc0 = nr_get_tpc(target_snrx10,ul_cqi,30);
UE_scheduling_control->ta_update = timing_advance;
UE_scheduling_control->ul_rssi = rssi;
LOG_D(MAC, "[UE %d] PUSCH TPC %d and TA %d\n",UE_id,UE_scheduling_control->tpc0,UE_scheduling_control->ta_update);
}
else{
UE_scheduling_control->tpc0 = 1;
......@@ -322,7 +323,6 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
#endif
if (sduP != NULL){
LOG_I(MAC, "[UE %d] PUSCH TPC %d and TA %d\n",UE_id,UE_scheduling_control->tpc0,UE_scheduling_control->ta_update);
LOG_D(MAC, "Received PDU at MAC gNB \n");
nr_process_mac_pdu(gnb_mod_idP, current_rnti, CC_idP, frameP, sduP, sdu_lenP);
}
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ 4e8fa97d
......@@ -64,7 +64,6 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
sub_frame_t subframeP);
void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
frame_t frame_txP, sub_frame_t slot_txP,
frame_t frame_rxP, sub_frame_t slot_rxP);
int nr_generate_dlsch_pdu(module_id_t Mod_idP,
......@@ -158,6 +157,14 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
void nr_schedule_pusch(int Mod_idP,
int UE_id,
int num_slots_per_tdd,
int ul_slots,
frame_t frameP,
sub_frame_t slotP);
void nr_schedule_pucch(int Mod_idP,
int UE_id,
int nr_ulmix_slots,
frame_t frameP,
sub_frame_t slotP);
......@@ -297,6 +304,7 @@ void schedule_fapi_ul_pdu(int Mod_idP,
frame_t frameP,
sub_frame_t slotP,
int num_slots_per_tdd,
int ul_slots,
int time_domain_assignment);
void nr_process_mac_pdu(
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 4e8fa97d
......@@ -251,6 +251,7 @@ typedef struct NR_sched_pucch {
uint8_t dai_c;
uint8_t timing_indicator;
uint8_t resource_indicator;
bool active;
} NR_sched_pucch;
typedef struct NR_sched_pusch {
......@@ -330,10 +331,6 @@ typedef struct gNB_MAC_INST_s {
eth_params_t eth_params_s;
/// Module
module_id_t Mod_id;
/// frame counter
frame_t frame;
/// slot counter
int slot;
/// timing advance group
NR_TAG_t *tag;
/// Pointer to IF module instance for PHY
......
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
View file @ 4e8fa97d
......@@ -290,8 +290,6 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
nfapi_nr_config_request_scf_t *cfg = &mac->config[CC_id];
int spf = get_spf(cfg);
gNB_dlsch_ulsch_scheduler(module_id,
UL_info->frame,
UL_info->slot,
(UL_info->frame+((UL_info->slot>(spf-1-sl_ahead))?1:0)) % 1024,
(UL_info->slot+sl_ahead)%spf);
......@@ -303,13 +301,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
sched_info->DL_req = &mac->DL_req[CC_id];
sched_info->UL_dci_req = &mac->UL_dci_req[CC_id];
if ((mac->common_channels[CC_id].ServingCellConfigCommon->tdd_UL_DL_ConfigurationCommon==NULL) ||
(is_nr_UL_slot(mac->common_channels[CC_id].ServingCellConfigCommon,UL_info->slot)>0)) {
//printf("NR_UL_indication: this is an UL slot. UL_info: frame %d, slot %d. UL_tti_req: frame %d, slot %d\n",UL_info->frame,UL_info->slot,mac->UL_tti_req[CC_id].SFN,mac->UL_tti_req[CC_id].Slot);
sched_info->UL_tti_req = &mac->UL_tti_req[CC_id];
}
else
sched_info->UL_tti_req = NULL;
sched_info->TX_req = &mac->TX_req[CC_id];
#ifdef DUMP_FAPI
......
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