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OpenXG-RAN
Commit 631fa2be authored by Raymond Knopp's avatar Raymond Knopp
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updates from Agilent IoT 

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4649 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent bf343691
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Showing with 68 additions and 40 deletions
openair2/LAYER2/MAC/defs.h
View file @ 631fa2be
...@@ -557,8 +557,9 @@ typedef struct { ...@@ -557,8 +557,9 @@ typedef struct {
u8 generate_rar; u8 generate_rar;
/// Subframe where Msg3 is to be sent /// Subframe where Msg3 is to be sent
u8 Msg3_subframe; u8 Msg3_subframe;
u8 preamble_subframe;
/// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC. This is triggered by first ULSCH reception at eNB for new user. /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC. This is triggered by first ULSCH reception at eNB for new user.
u8 generate_Msg4; u8 generate_Msg4;
/// Flag to indicate the eNB should generate the DCI for Msg4, after getting the SDU from RRC. /// Flag to indicate the eNB should generate the DCI for Msg4, after getting the SDU from RRC.
u8 generate_Msg4_dci; u8 generate_Msg4_dci;
/// Flag to indicate that eNB is waiting for ACK that UE has received Msg3. /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3.
......
openair2/LAYER2/MAC/eNB_scheduler.c
View file @ 631fa2be
...@@ -391,8 +391,8 @@ s8 add_new_ue(unsigned char Mod_id, u16 rnti) { ...@@ -391,8 +391,8 @@ s8 add_new_ue(unsigned char Mod_id, u16 rnti) {
if (eNB_mac_inst[Mod_id].UE_template[i].rnti==0) { if (eNB_mac_inst[Mod_id].UE_template[i].rnti==0) {
eNB_mac_inst[Mod_id].UE_template[i].rnti=rnti; eNB_mac_inst[Mod_id].UE_template[i].rnti=rnti;
for (j=0;j<8;j++) { for (j=0;j<8;j++) {
eNB_mac_inst[Mod_id].UE_template[i].oldNDI[j]=1; eNB_mac_inst[Mod_id].UE_template[i].oldNDI[j]=0;
eNB_mac_inst[Mod_id].UE_template[i].oldNDI_UL[j]=1; eNB_mac_inst[Mod_id].UE_template[i].oldNDI_UL[j]=0;
} }
eNB_ulsch_info[Mod_id][i].status = S_UL_WAITING; eNB_ulsch_info[Mod_id][i].status = S_UL_WAITING;
eNB_dlsch_info[Mod_id][i].status = S_UL_WAITING; eNB_dlsch_info[Mod_id][i].status = S_UL_WAITING;
...@@ -2180,19 +2180,22 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2180,19 +2180,22 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
if (eNB_UE_stats==NULL) if (eNB_UE_stats==NULL)
mac_xface->macphy_exit("[MAC][eNB] Cannot find eNB_UE_stats\n"); mac_xface->macphy_exit("[MAC][eNB] Cannot find eNB_UE_stats\n");
LOG_D(MAC,"[eNB %d] Scheduler Frame %d, subframe %d, nCCE %d: Checking ULSCH next UE_id %d mode id %d (rnti %x,mode %s), format 0\n",Mod_id,frame,subframe,*nCCE,next_ue,Mod_id, rnti,mode_string[eNB_UE_stats->mode]); LOG_I(MAC,"[eNB %d] Scheduler Frame %d, subframe %d, nCCE %d: Checking ULSCH next UE_id %d mode id %d (rnti %x,mode %s), format 0\n",Mod_id,frame,subframe,*nCCE,next_ue,Mod_id, rnti,mode_string[eNB_UE_stats->mode]);
if (eNB_UE_stats->mode == PUSCH) { // ue has a ulsch channel if (eNB_UE_stats->mode == PUSCH) { // ue has a ulsch channel
s8 ret; s8 ret;
// Get candidate harq_pid from PHY // Get candidate harq_pid from PHY
ret = mac_xface->get_ue_active_harq_pid(Mod_id,rnti,subframe,&harq_pid,&round,1); ret = mac_xface->get_ue_active_harq_pid(Mod_id,rnti,subframe,&harq_pid,&round,1);
// printf("Got harq_pid %d, round %d, next_ue %d\n",harq_pid,round,next_ue); LOG_I(MAC,"Got harq_pid %d, round %d, next_ue %d\n",harq_pid,round,next_ue);
/* [SR] 01/07/13: Don't schedule UE if we cannot get harq pid */ /* [SR] 01/07/13: Don't schedule UE if we cannot get harq pid */
if ((((UE_is_to_be_scheduled(Mod_id,UE_id)>0)) || (round>0) || ((frame%10)==0)) && (ret == 0)) { #ifndef EXMIMO_IOT
if ((((UE_is_to_be_scheduled(Mod_id,UE_id)>0)) || (round>0) || ((frame%10)==0)) && (ret == 0))
// if there is information on bsr of DCCH, DTCH or if there is UL_SR, or if there is a packet to retransmit, or we want to schedule a periodic feedback every 10 frames // if there is information on bsr of DCCH, DTCH or if there is UL_SR, or if there is a packet to retransmit, or we want to schedule a periodic feedback every 10 frames
#else
if (round==0)
#endif
{
LOG_D(MAC,"[eNB %d][PUSCH %x] Frame %d subframe %d Scheduling UE %d (SR %d)\n", LOG_D(MAC,"[eNB %d][PUSCH %x] Frame %d subframe %d Scheduling UE %d (SR %d)\n",
Mod_id,rnti,frame,subframe,UE_id, Mod_id,rnti,frame,subframe,UE_id,
eNB_mac_inst[Mod_id].UE_template[UE_id].ul_SR); eNB_mac_inst[Mod_id].UE_template[UE_id].ul_SR);
...@@ -2235,7 +2238,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2235,7 +2238,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
(eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID1] == 0) && (eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID1] == 0) &&
(eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID2] == 0) && (eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID2] == 0) &&
(eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID3] == 0))? (eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID3] == 0))?
BSR_TABLE[1] : // This is when we've received SR and buffers are fully served BSR_TABLE[10] : // This is when we've received SR and buffers are fully served
BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID0]]+ BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID0]]+
BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID1]]+ BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID1]]+
BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID2]]+ BSR_TABLE[eNB_mac_inst[Mod_id].UE_template[UE_id].bsr_info[LCGID2]]+
...@@ -2357,6 +2360,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2357,6 +2360,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi; ((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi;
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1; ((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1;
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift; ((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift;
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->padding = 0;
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe]; ((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe];
((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_1_5MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -2380,6 +2384,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2380,6 +2384,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi; ((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi;
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1; ((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1;
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift; ((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift;
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->padding = 0;
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe]; ((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe];
((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_5MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -2402,6 +2407,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2402,6 +2407,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi; ((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi;
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1; ((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1;
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift; ((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift;
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->padding = 0;
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe]; ((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe];
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -2424,6 +2430,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2424,6 +2430,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi; ((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->ndi = ndi;
((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1; ((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->TPC = 1;
((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift; ((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->cshift = cshift;
((DCI0_10MHz_TDD_1_6_t *)ULSCH_dci)->padding = 0;
((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe]; ((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->dai = eNB_mac_inst[Mod_id].UE_template[next_ue].DAI_ul[sched_subframe];
((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_20MHz_TDD_1_6_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -2452,6 +2459,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2452,6 +2459,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_5MHz_FDD_t *)ULSCH_dci)->ndi = ndi; ((DCI0_5MHz_FDD_t *)ULSCH_dci)->ndi = ndi;
((DCI0_5MHz_FDD_t *)ULSCH_dci)->TPC = 1; ((DCI0_5MHz_FDD_t *)ULSCH_dci)->TPC = 1;
((DCI0_5MHz_FDD_t *)ULSCH_dci)->cshift = cshift; ((DCI0_5MHz_FDD_t *)ULSCH_dci)->cshift = cshift;
((DCI0_5MHz_FDD_t *)ULSCH_dci)->padding = 0;
((DCI0_5MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_5MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req;
add_ue_spec_dci(DCI_pdu, add_ue_spec_dci(DCI_pdu,
...@@ -2473,6 +2481,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2473,6 +2481,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->ndi = ndi; ((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->ndi = ndi;
((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->TPC = 1; ((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->TPC = 1;
((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->cshift = cshift; ((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->cshift = cshift;
((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->padding = 0;
((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_1_5MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req;
add_ue_spec_dci(DCI_pdu, add_ue_spec_dci(DCI_pdu,
...@@ -2493,6 +2502,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2493,6 +2502,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_10MHz_FDD_t *)ULSCH_dci)->mcs = mcs; ((DCI0_10MHz_FDD_t *)ULSCH_dci)->mcs = mcs;
((DCI0_10MHz_FDD_t *)ULSCH_dci)->ndi = ndi; ((DCI0_10MHz_FDD_t *)ULSCH_dci)->ndi = ndi;
((DCI0_10MHz_FDD_t *)ULSCH_dci)->TPC = 1; ((DCI0_10MHz_FDD_t *)ULSCH_dci)->TPC = 1;
((DCI0_10MHz_FDD_t *)ULSCH_dci)->padding = 0;
((DCI0_10MHz_FDD_t *)ULSCH_dci)->cshift = cshift; ((DCI0_10MHz_FDD_t *)ULSCH_dci)->cshift = cshift;
((DCI0_10MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_10MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -2514,6 +2524,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u ...@@ -2514,6 +2524,7 @@ void schedule_ulsch_rnti(u8 Mod_id, unsigned char cooperation_flag, u32 frame, u
((DCI0_20MHz_FDD_t *)ULSCH_dci)->mcs = mcs; ((DCI0_20MHz_FDD_t *)ULSCH_dci)->mcs = mcs;
((DCI0_20MHz_FDD_t *)ULSCH_dci)->ndi = ndi; ((DCI0_20MHz_FDD_t *)ULSCH_dci)->ndi = ndi;
((DCI0_20MHz_FDD_t *)ULSCH_dci)->TPC = 1; ((DCI0_20MHz_FDD_t *)ULSCH_dci)->TPC = 1;
((DCI0_20MHz_FDD_t *)ULSCH_dci)->padding = 0;
((DCI0_20MHz_FDD_t *)ULSCH_dci)->cshift = cshift; ((DCI0_20MHz_FDD_t *)ULSCH_dci)->cshift = cshift;
((DCI0_20MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req; ((DCI0_20MHz_FDD_t *)ULSCH_dci)->cqi_req = cqi_req;
...@@ -3008,7 +3019,8 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3008,7 +3019,8 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type=0; ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_1_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3019,6 +3031,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3019,6 +3031,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3029,6 +3042,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3029,6 +3042,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_10MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3049,6 +3063,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3049,6 +3063,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_5MHz_TDD_1_6_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3064,6 +3079,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3064,6 +3079,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_1_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3074,6 +3090,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3074,6 +3090,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_5MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3084,6 +3101,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3084,6 +3101,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_10MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -3094,6 +3112,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R ...@@ -3094,6 +3112,7 @@ void fill_DLSCH_dci(unsigned char Mod_id,u32 frame, unsigned char subframe,u32 R
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0; ((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rv=0;
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0; ((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1; ((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->TPC=1;
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->padding=0;
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4); ((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_DL,first_rb,4);
rballoc |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type, rballoc |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->vrb_type,
((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc); ((DCI1A_20MHz_FDD_t*)&eNB_mac_inst[Mod_id].RA_template[i].RA_alloc_pdu2[0])->rballoc);
...@@ -4333,7 +4352,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4333,7 +4352,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
schedule_RA(Mod_id,frame,subframe,2,&nprb,&nCCE); schedule_RA(Mod_id,frame,subframe,2,&nprb,&nCCE);
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
// schedule_ulsch(Mod_id,frame,cooperation_flag,subframe,4,&nCCE);//,calibration_flag); schedule_ulsch(Mod_id,frame,cooperation_flag,0,4,&nCCE);//,calibration_flag);
} }
else if ((mac_xface->lte_frame_parms->tdd_config == TDD) || //TDD else if ((mac_xface->lte_frame_parms->tdd_config == TDD) || //TDD
(mac_xface->lte_frame_parms->tdd_config == 3) || (mac_xface->lte_frame_parms->tdd_config == 3) ||
...@@ -4365,7 +4384,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4365,7 +4384,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
//schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE); schedule_ulsch(Mod_id,frame,cooperation_flag,1,5,&nCCE);
// schedule_ue_spec(Mod_id,subframe,nprb,&nCCE,mbsfn_status); // schedule_ue_spec(Mod_id,subframe,nprb,&nCCE,mbsfn_status);
// fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status); // fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4375,7 +4394,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4375,7 +4394,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
// TDD, nothing // TDD, nothing
// FDD, normal UL/DLSCH // FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
// schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE); schedule_ulsch(Mod_id,frame,cooperation_flag,2,6,&nCCE);
// schedule_ue_spec(Mod_id,subframe,nprb,&nCCE,mbsfn_status); // schedule_ue_spec(Mod_id,subframe,nprb,&nCCE,mbsfn_status);
// fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status); // fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4398,7 +4417,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4398,7 +4417,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
// schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE,calibration_flag); // schedule_ulsch(Mod_id,frame,cooperation_flag,3,7,&nCCE);
// schedule_ue_spec(Mod_id,subframe,0,0,mbsfn_status); // schedule_ue_spec(Mod_id,subframe,0,0,mbsfn_status);
// fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status); // fill_DLSCH_dci(Mod_id,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4425,10 +4444,11 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4425,10 +4444,11 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
else { else {
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
schedule_RA(Mod_id,frame,subframe,0,&nprb,&nCCE); schedule_RA(Mod_id, frame, subframe, 0, &nprb, &nCCE);
// schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE,calibration_flag); // schedule_ulsch(Mod_id, frame, cooperation_flag, 4, 8, &nCCE);
// schedule_ue_spec(Mod_id,subframe,nprb,&nCCE,mbsfn_status); //schedule_ue_spec(Mod_id, frame, subframe, nprb, &nCCE, mbsfn_status);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,1,mbsfn_status); fill_DLSCH_dci(Mod_id, frame, subframe, RBalloc, 1, mbsfn_status);
} }
} }
break; break;
...@@ -4442,7 +4462,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4442,7 +4462,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
//schedule_RA(Mod_id,frame,subframe,5,&nprb,&nCCE); //schedule_RA(Mod_id,frame,subframe,5,&nprb,&nCCE);
if ((mac_xface->lte_frame_parms->frame_type == FDD) ) { if ((mac_xface->lte_frame_parms->frame_type == FDD) ) {
// schedule_RA(Mod_id,frame,subframe,1,&nprb,&nCCE); // schedule_RA(Mod_id,frame,subframe,1,&nprb,&nCCE);
//schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE); // schedule_ulsch(Mod_id,frame,cooperation_flag,5,9,&nCCE);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status); fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4491,7 +4511,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4491,7 +4511,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
// schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE,calibration_flag); // schedule_ulsch(Mod_id,frame,cooperation_flag,6,0,&nCCE);
schedule_ue_spec(Mod_id,frame,subframe,nprb,&nCCE,mbsfn_status); schedule_ue_spec(Mod_id,frame,subframe,nprb,&nCCE,mbsfn_status);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status); fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4517,7 +4537,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4517,7 +4537,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
// schedule_ulsch(Mod_id,cooperation_flag,subframe,&nCCE,calibration_flag); // schedule_ulsch(Mod_id,frame,cooperation_flag,7,1,&nCCE);
schedule_ue_spec(Mod_id,frame,subframe,nprb,&nCCE,mbsfn_status); schedule_ue_spec(Mod_id,frame,subframe,nprb,&nCCE,mbsfn_status);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status); fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4544,7 +4564,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4544,7 +4564,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
schedule_ulsch(Mod_id,frame,cooperation_flag,subframe,2,&nCCE); // schedule_ulsch(Mod_id,frame,cooperation_flag,8,2,&nCCE);
schedule_ue_spec(Mod_id,frame,subframe,0,&nCCE,mbsfn_status); schedule_ue_spec(Mod_id,frame,subframe,0,&nCCE,mbsfn_status);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status); fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status);
} }
...@@ -4583,7 +4603,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf ...@@ -4583,7 +4603,7 @@ void eNB_dlsch_ulsch_scheduler(u8 Mod_id,u8 cooperation_flag, u32 frame, u8 subf
} }
} }
else { //FDD else { //FDD
schedule_ulsch(Mod_id,frame,cooperation_flag,subframe,3,&nCCE); // schedule_ulsch(Mod_id,frame,cooperation_flag,9,3,&nCCE);
schedule_ue_spec(Mod_id,frame,subframe,0,&nCCE,mbsfn_status); schedule_ue_spec(Mod_id,frame,subframe,0,&nCCE,mbsfn_status);
fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status); fill_DLSCH_dci(Mod_id,frame,subframe,RBalloc,0,mbsfn_status);
} }
......
openair2/LAYER2/MAC/rar_tools.c
View file @ 631fa2be
...@@ -43,9 +43,6 @@ ...@@ -43,9 +43,6 @@
#include "UTIL/LOG/log.h" #include "UTIL/LOG/log.h"
#include "OCG.h" #include "OCG.h"
#include "OCG_extern.h" #include "OCG_extern.h"
#if defined(USER_MODE) && defined(OAI_EMU)
# include "UTIL/OPT/opt.h"
#endif
#define DEBUG_RAR #define DEBUG_RAR
...@@ -65,11 +62,9 @@ unsigned short fill_rar(u8 Mod_id, ...@@ -65,11 +62,9 @@ unsigned short fill_rar(u8 Mod_id,
RA_HEADER_RAPID *rarh = (RA_HEADER_RAPID *)dlsch_buffer; RA_HEADER_RAPID *rarh = (RA_HEADER_RAPID *)dlsch_buffer;
// RAR_PDU *rar = (RAR_PDU *)(dlsch_buffer+1); // RAR_PDU *rar = (RAR_PDU *)(dlsch_buffer+1);
uint8_t *rar = (uint8_t *)(dlsch_buffer+1); uint8_t *rar = (uint8_t *)(dlsch_buffer+1);
int i; int i,ra_idx;
int ra_idx = -1;
uint16_t rballoc; uint16_t rballoc;
uint8_t mcs,TPC,ULdelay,cqireq; uint8_t mcs,TPC,cqi_req,ULdelay,cqireq;
//uint8_t cqi_req;
for (i=0;i<NB_RA_PROC_MAX;i++) { for (i=0;i<NB_RA_PROC_MAX;i++) {
if (eNB_mac_inst[Mod_id].RA_template[i].generate_rar == 1) { if (eNB_mac_inst[Mod_id].RA_template[i].generate_rar == 1) {
...@@ -96,22 +91,26 @@ unsigned short fill_rar(u8 Mod_id, ...@@ -96,22 +91,26 @@ unsigned short fill_rar(u8 Mod_id,
*/ */
rar[4] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti>>8); rar[4] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti>>8);
rar[5] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti&0xff); rar[5] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti&0xff);
eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset = 0;
//eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset /= 16;
rar[0] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset>>(2+4)); // 7 MSBs of timing advance + divide by 4 rar[0] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset>>(2+4)); // 7 MSBs of timing advance + divide by 4
rar[1] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset<<(4-2))&0xf0; // 4 LSBs of timing advance + divide by 4 rar[1] = (uint8_t)(eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset<<(4-2))&0xf0; // 4 LSBs of timing advance + divide by 4
rballoc = mac_xface->computeRIV(N_RB_UL,1,1); // first PRB only for UL Grant rballoc = mac_xface->computeRIV(N_RB_UL,1,1); // first PRB only for UL Grant
rar[1] |= (rballoc>>7)&7; // Hopping = 0 (bit 3), 3 MSBs of rballoc rar[1] |= (rballoc>>7)&7; // Hopping = 0 (bit 3), 3 MSBs of rballoc
rar[2] = ((uint8_t)(rballoc&0xff))<<1; // 7 LSBs of rballoc rar[2] = ((uint8_t)(rballoc&0xff))<<1; // 7 LSBs of rballoc
mcs = 9; mcs = 10;
TPC = 4; TPC = 3;
ULdelay = 0; ULdelay = 0;
cqireq = 0; cqireq = 0;
rar[2] |= ((mcs&0xf)>>3); // mcs 10 rar[2] |= ((mcs&0x8)>>3); // mcs 10
rar[3] = (((mcs&0xff)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1); rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
LOG_I(MAC,"[eNB %d][RAPROC] Frame %d Generating RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for CRNTI %x,preamble %d/%d\n",Mod_id,frame, LOG_I(MAC,"[eNB %d][RAPROC] Frame %d Generating RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for ra_idx %d, CRNTI %x,preamble %d/%d,TIMING OFFSET %d\n",Mod_id,frame,
*(uint8_t*)rarh,rar[0],rar[1],rar[2],rar[3],rar[4],rar[5], *(uint8_t*)rarh,rar[0],rar[1],rar[2],rar[3],rar[4],rar[5],
ra_idx,
eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti, eNB_mac_inst[Mod_id].RA_template[ra_idx].rnti,
rarh->RAPID,eNB_mac_inst[Mod_id].RA_template[0].preamble_index); rarh->RAPID,eNB_mac_inst[Mod_id].RA_template[0].preamble_index,
eNB_mac_inst[Mod_id].RA_template[ra_idx].timing_offset);
#if defined(USER_MODE) && defined(OAI_EMU) #if defined(USER_MODE) && defined(OAI_EMU)
if (oai_emulation.info.opt_enabled){ if (oai_emulation.info.opt_enabled){
......
openair2/RRC/LITE/MESSAGES/asn1_msg.c
View file @ 631fa2be
...@@ -425,7 +425,7 @@ uint8_t do_SIB1(LTE_DL_FRAME_PARMS *frame_parms, uint8_t *buffer, ...@@ -425,7 +425,7 @@ uint8_t do_SIB1(LTE_DL_FRAME_PARMS *frame_parms, uint8_t *buffer,
(*sib1)->cellSelectionInfo.q_RxLevMin=-65; (*sib1)->cellSelectionInfo.q_RxLevMin=-65;
(*sib1)->cellSelectionInfo.q_RxLevMinOffset=NULL; (*sib1)->cellSelectionInfo.q_RxLevMinOffset=NULL;
(*sib1)->freqBandIndicator = 38; (*sib1)->freqBandIndicator = 7;
schedulingInfo.si_Periodicity=SchedulingInfo__si_Periodicity_rf8; schedulingInfo.si_Periodicity=SchedulingInfo__si_Periodicity_rf8;
...@@ -727,7 +727,7 @@ uint8_t do_SIB23(uint8_t Mod_id, ...@@ -727,7 +727,7 @@ uint8_t do_SIB23(uint8_t Mod_id,
#endif #endif
(*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.preambleTransMax=RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n10; (*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.preambleTransMax=RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n10;
(*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.ra_ResponseWindowSize=RACH_ConfigCommon__ra_SupervisionInfo__ra_ResponseWindowSize_sf4; (*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.ra_ResponseWindowSize=RACH_ConfigCommon__ra_SupervisionInfo__ra_ResponseWindowSize_sf10;
(*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.mac_ContentionResolutionTimer=RACH_ConfigCommon__ra_SupervisionInfo__mac_ContentionResolutionTimer_sf48; (*sib2)->radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.mac_ContentionResolutionTimer=RACH_ConfigCommon__ra_SupervisionInfo__mac_ContentionResolutionTimer_sf48;
...@@ -753,7 +753,7 @@ uint8_t do_SIB23(uint8_t Mod_id, ...@@ -753,7 +753,7 @@ uint8_t do_SIB23(uint8_t Mod_id,
// PDSCH-Config // PDSCH-Config
#ifdef EXMIMO #ifdef EXMIMO
(*sib2)->radioResourceConfigCommon.pdsch_ConfigCommon.referenceSignalPower=0; (*sib2)->radioResourceConfigCommon.pdsch_ConfigCommon.referenceSignalPower=-32;
#else #else
(*sib2)->radioResourceConfigCommon.pdsch_ConfigCommon.referenceSignalPower=15; (*sib2)->radioResourceConfigCommon.pdsch_ConfigCommon.referenceSignalPower=15;
#endif #endif
......
openair2/UTIL/LOG/vcd_signal_dumper.c
View file @ 631fa2be
...@@ -153,9 +153,13 @@ const char* eurecomFunctionsNames[] = { ...@@ -153,9 +153,13 @@ const char* eurecomFunctionsNames[] = {
"phy_ue_config_sib2", "phy_ue_config_sib2",
"phy_ue_compute_prach", "phy_ue_compute_prach",
"phy_enb_ulsch_decoding", "phy_enb_ulsch_decoding",
"phy_enb_sfgen",
"phy_enb_prach_rx",
"phy_enb_pdcch_tx",
"phy_enb_rs_tx",
"phy_ue_ulsch_modulation", "phy_ue_ulsch_modulation",
"phy_ue_ulsch_encoding", "phy_ue_ulsch_encoding",
"phy_ue_ulsch_scramblig", "phy_ue_ulsch_scrambling",
"phy_eNB_dlsch_modulation", "phy_eNB_dlsch_modulation",
"phy_eNB_dlsch_encoding", "phy_eNB_dlsch_encoding",
"phy_eNB_dlsch_scramblig", "phy_eNB_dlsch_scramblig",
......
openair2/UTIL/LOG/vcd_signal_dumper.h
View file @ 631fa2be
...@@ -124,6 +124,10 @@ typedef enum ...@@ -124,6 +124,10 @@ typedef enum
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_CONFIG_SIB2, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_CONFIG_SIB2,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_SFGEN,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_RS_TX,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_MODULATION, VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_MODULATION,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_ENCODING, VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_ENCODING,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_SCRAMBLING, VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_SCRAMBLING,
......
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