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zzha zzha
OpenXG-RAN
Commits
8fdc21b2
Commit
8fdc21b2
authored
Jul 03, 2019
by
Padarthi Naga Prasanth
Committed by
Raphael Defosseux
Jul 03, 2019
Browse files
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Plain Diff
PUCCH format 1 receiver
parent
1ce0700e
Changes
6
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Showing
6 changed files
with
672 additions
and
139 deletions
+672
-139
cmake_targets/CMakeLists.txt
cmake_targets/CMakeLists.txt
+1
-1
cmake_targets/autotests/test_case_list.xml
cmake_targets/autotests/test_case_list.xml
+23
-0
openair1/PHY/NR_TRANSPORT/pucch_rx.c
openair1/PHY/NR_TRANSPORT/pucch_rx.c
+485
-5
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
+41
-39
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
+17
-2
openair1/SIMULATION/NR_PHY/pucchsim.c
openair1/SIMULATION/NR_PHY/pucchsim.c
+105
-92
No files found.
cmake_targets/CMakeLists.txt
View file @
8fdc21b2
...
@@ -1302,7 +1302,7 @@ set(PHY_SRC_UE
...
@@ -1302,7 +1302,7 @@ set(PHY_SRC_UE
${
PHY_POLARSRC
}
${
PHY_POLARSRC
}
${
PHY_SMALLBLOCKSRC
}
${
PHY_SMALLBLOCKSRC
}
${
PHY_LDPCSRC
}
${
PHY_LDPCSRC
}
${
OPENAIR1_DIR
}
/PHY/NR_TRANSPORT/pucch_rx.c
# added by prasanth
${
OPENAIR1_DIR
}
/PHY/NR_TRANSPORT/pucch_rx.c
)
)
set
(
PHY_NR_UE_SRC
set
(
PHY_NR_UE_SRC
...
...
cmake_targets/autotests/test_case_list.xml
View file @
8fdc21b2
...
@@ -1160,6 +1160,29 @@
...
@@ -1160,6 +1160,29 @@
<nruns>
3
</nruns>
<nruns>
3
</nruns>
</testCase>
</testCase>
<testCase
id=
"015109"
>
<class>
execution
</class>
<desc>
nr_nr_pucchsim Test cases. (Test1: Format 0 ACK miss 106 PRB),
(Test2: Format 1 ACK miss 106 PRB),
(Test3: Format 1 ACK miss 273 PRB),
(Test4: Format 1 NACKtoACK 106 PRB)
</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>
$OPENAIR_DIR/cmake_targets/build_oai
</compile_prog>
<compile_prog_args>
--phy_simulators -c
</compile_prog_args>
<pre_exec>
$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash
</pre_exec>
<pre_exec_args></pre_exec_args>
<main_exec>
$OPENAIR_DIR/targets/bin/nr_pucchsim.Rel15
</main_exec>
<main_exec_args>
-R 106 -i 1 -P 0 -b 1 -s3 -n100
-R 106 -i 14 -P 1 -b 1 -s-6 -n 100
-R 273 -i 14 -P 1 -b 1 -s-6 -n100
-R 106 -i 14 -P 1 -b 1 -s-6 -T 0.001 -n1000
</main_exec_args>
<tags>
nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4
</tags>
<search_expr_true>
PUCCH test OK
</search_expr_true>
<search_expr_false>
segmentation fault|assertion|exiting|fatal
</search_expr_false>
<nruns>
3
</nruns>
</testCase>
<testCase
id=
"015110"
>
<testCase
id=
"015110"
>
<class>
execution
</class>
<class>
execution
</class>
<desc>
dlsim_tm4 test cases (Test 1: 10 MHz, R2.FDD (MCS 5), EVA5, -1dB),
<desc>
dlsim_tm4 test cases (Test 1: 10 MHz, R2.FDD (MCS 5), EVA5, -1dB),
...
...
openair1/PHY/NR_TRANSPORT/pucch_rx.c
View file @
8fdc21b2
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
View file @
8fdc21b2
...
@@ -366,7 +366,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -366,7 +366,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
d_im
=
-
(
int16_t
)(((
int32_t
)
amp
*
ONE_OVER_SQRT2
)
>>
15
);
d_im
=
-
(
int16_t
)(((
int32_t
)
amp
*
ONE_OVER_SQRT2
)
>>
15
);
}
}
}
}
// printf("d_re=%d\td_im=%d\n",(int)d_re,(int)d_im);
#ifdef DEBUG_NR_PUCCH_TX
#ifdef DEBUG_NR_PUCCH_TX
printf
(
"
\t
[nr_generate_pucch1] sequence modulation: payload=%x
\t
de_re=%d
\t
de_im=%d
\n
"
,
payload
,
d_re
,
d_im
);
printf
(
"
\t
[nr_generate_pucch1] sequence modulation: payload=%x
\t
de_re=%d
\t
de_im=%d
\n
"
,
payload
,
d_re
,
d_im
);
#endif
#endif
...
@@ -451,11 +451,13 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -451,11 +451,13 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
+
(((
int32_t
)(
round
(
32767
*
sin
(
alpha
*
n
)))
*
table_5_2_2_2_2_Re
[
u
][
n
])
>>
15
)));
// Im part of DMRS base sequence shifted by alpha
+
(((
int32_t
)(
round
(
32767
*
sin
(
alpha
*
n
)))
*
table_5_2_2_2_2_Re
[
u
][
n
])
>>
15
)));
// Im part of DMRS base sequence shifted by alpha
r_u_v_alpha_delta_dmrs_re
[
n
]
=
(
int16_t
)(((
int32_t
)(
amp
*
r_u_v_alpha_delta_dmrs_re
[
n
]))
>>
15
);
r_u_v_alpha_delta_dmrs_re
[
n
]
=
(
int16_t
)(((
int32_t
)(
amp
*
r_u_v_alpha_delta_dmrs_re
[
n
]))
>>
15
);
r_u_v_alpha_delta_dmrs_im
[
n
]
=
(
int16_t
)(((
int32_t
)(
amp
*
r_u_v_alpha_delta_dmrs_im
[
n
]))
>>
15
);
r_u_v_alpha_delta_dmrs_im
[
n
]
=
(
int16_t
)(((
int32_t
)(
amp
*
r_u_v_alpha_delta_dmrs_im
[
n
]))
>>
15
);
// printf("symbol=%d\tr_u_v_re=%d\tr_u_v_im=%d\n",l,r_u_v_alpha_delta_re[n],r_u_v_alpha_delta_im[n]);
// PUCCH sequence = DM-RS sequence multiplied by d(0)
// PUCCH sequence = DM-RS sequence multiplied by d(0)
y_n_re
[
n
]
=
(
int16_t
)(((((
int32_t
)(
r_u_v_alpha_delta_re
[
n
])
*
d_re
)
>>
15
)
y_n_re
[
n
]
=
(
int16_t
)(((((
int32_t
)(
r_u_v_alpha_delta_re
[
n
])
*
d_re
)
>>
15
)
-
(((
int32_t
)(
r_u_v_alpha_delta_im
[
n
])
*
d_im
)
>>
15
)));
// Re part of y(n)
-
(((
int32_t
)(
r_u_v_alpha_delta_im
[
n
])
*
d_im
)
>>
15
)));
// Re part of y(n)
y_n_im
[
n
]
=
(
int16_t
)(((((
int32_t
)(
r_u_v_alpha_delta_re
[
n
])
*
d_im
)
>>
15
)
y_n_im
[
n
]
=
(
int16_t
)(((((
int32_t
)(
r_u_v_alpha_delta_re
[
n
])
*
d_im
)
>>
15
)
+
(((
int32_t
)(
r_u_v_alpha_delta_im
[
n
])
*
d_re
)
>>
15
)));
// Im part of y(n)
+
(((
int32_t
)(
r_u_v_alpha_delta_im
[
n
])
*
d_re
)
>>
15
)));
// Im part of y(n)
// printf("symbol=%d\tr_u_v_dmrs_re=%d\tr_u_v_dmrs_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n],r_u_v_alpha_delta_dmrs_im[n]);
#ifdef DEBUG_NR_PUCCH_TX
#ifdef DEBUG_NR_PUCCH_TX
printf
(
"
\t
[nr_generate_pucch1] sequence generation
\t
u=%d
\t
v=%d
\t
alpha=%lf
\t
r_u_v_alpha_delta[n=%d]=(%d,%d)
\t
y_n[n=%d]=(%d,%d)
\n
"
,
printf
(
"
\t
[nr_generate_pucch1] sequence generation
\t
u=%d
\t
v=%d
\t
alpha=%lf
\t
r_u_v_alpha_delta[n=%d]=(%d,%d)
\t
y_n[n=%d]=(%d,%d)
\n
"
,
u
,
v
,
alpha
,
n
,
r_u_v_alpha_delta_re
[
n
],
r_u_v_alpha_delta_im
[
n
],
n
,
y_n_re
[
n
],
y_n_im
[
n
]);
u
,
v
,
alpha
,
n
,
r_u_v_alpha_delta_re
[
n
],
r_u_v_alpha_delta_im
[
n
],
n
,
y_n_re
[
n
],
y_n_im
[
n
]);
...
@@ -520,10 +522,10 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -520,10 +522,10 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_DMRS_1
;
m
++
)
{
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_DMRS_1
;
m
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
)
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_
DMRS_
1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
)
-
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
));
-
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_
DMRS_
1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
));
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
)
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_
DMRS_
1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
)
+
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
));
+
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_
DMRS_
1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
));
#ifdef DEBUG_NR_PUCCH_TX
#ifdef DEBUG_NR_PUCCH_TX
printf
(
"
\t
[nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)
\n
"
,
printf
(
"
\t
[nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)
\n
"
,
mprime
,
m
,
n
,
(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
,
mprime
,
m
,
n
,
(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
,
...
@@ -531,6 +533,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -531,6 +533,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
],
r_u_v_alpha_delta_dmrs_im
[
n
],
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
],
r_u_v_alpha_delta_dmrs_re
[
n
],
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
],
r_u_v_alpha_delta_dmrs_im
[
n
],
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_1
][
w_index
][
m
],
r_u_v_alpha_delta_dmrs_re
[
n
],
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
],
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
]);
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
],
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
]);
#endif
#endif
// printf("gNB entering l=%d\tdmrs_re=%d\tdmrs_im=%d\n",l,z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n],z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n]);
}
}
}
}
}
}
...
@@ -549,7 +552,6 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -549,7 +552,6 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
w_index
,
N_SF_mprime_PUCCH_1
,
N_SF_mprime_PUCCH_DMRS_1
,
N_SF_mprime0_PUCCH_1
,
N_SF_mprime0_PUCCH_DMRS_1
);
w_index
,
N_SF_mprime_PUCCH_1
,
N_SF_mprime_PUCCH_DMRS_1
,
N_SF_mprime0_PUCCH_1
,
N_SF_mprime0_PUCCH_DMRS_1
);
#endif
#endif
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_1
;
m
++
)
{
for
(
mprime
=
0
;
mprime
<
2
;
mprime
++
)
{
// mprime can get values {0,1}
for
(
mprime
=
0
;
mprime
<
2
;
mprime
++
)
{
// mprime can get values {0,1}
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_1
;
m
++
)
{
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_1
;
m
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
...
@@ -569,10 +571,10 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -569,10 +571,10 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_DMRS_1
;
m
++
)
{
for
(
int
m
=
0
;
m
<
N_SF_mprime_PUCCH_DMRS_1
;
m
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
for
(
int
n
=
0
;
n
<
12
;
n
++
)
{
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
)
z_dmrs_re
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_DMRS
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
)
-
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
));
-
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_DMRS
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
));
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
)
z_dmrs_im
[(
mprime
*
12
*
N_SF_mprime0_PUCCH_DMRS_1
)
+
(
m
*
12
)
+
n
]
=
(
int16_t
)((((
int32_t
)(
table_6_3_2_4_1_2_Wi_Re
[
N_SF_mprime_PUCCH_DMRS
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_im
[
n
])
>>
15
)
+
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
));
+
(((
int32_t
)(
table_6_3_2_4_1_2_Wi_Im
[
N_SF_mprime_PUCCH_DMRS
_1
][
w_index
][
m
])
*
r_u_v_alpha_delta_dmrs_re
[
n
])
>>
15
));
#ifdef DEBUG_NR_PUCCH_TX
#ifdef DEBUG_NR_PUCCH_TX
printf
(
"
\t
[nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)
\n
"
,
printf
(
"
\t
[nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)
\n
"
,
mprime
,
m
,
n
,
(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
,
mprime
,
m
,
n
,
(
mprime
*
12
*
N_SF_mprime0_PUCCH_1
)
+
(
m
*
12
)
+
n
,
...
@@ -587,7 +589,6 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -587,7 +589,6 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
N_SF_mprime_PUCCH_DMRS_1
=
table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m1Hop
[
nrofSymbols
-
1
];
// only if intra-slot hopping enabled mprime = 1 (DM-RS)
N_SF_mprime_PUCCH_DMRS_1
=
table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m1Hop
[
nrofSymbols
-
1
];
// only if intra-slot hopping enabled mprime = 1 (DM-RS)
}
}
}
}
}
if
((
intraSlotFrequencyHopping
==
1
)
&&
(
l
<
floor
(
nrofSymbols
/
2
)))
{
// intra-slot hopping enabled, we need to calculate new offset PRB
if
((
intraSlotFrequencyHopping
==
1
)
&&
(
l
<
floor
(
nrofSymbols
/
2
)))
{
// intra-slot hopping enabled, we need to calculate new offset PRB
startingPRB
=
startingPRB
+
startingPRB_intraSlotHopping
;
startingPRB
=
startingPRB
+
startingPRB_intraSlotHopping
;
...
@@ -638,6 +639,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
...
@@ -638,6 +639,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
amp
,
frame_parms
->
ofdm_symbol_size
,
frame_parms
->
N_RB_DL
,
frame_parms
->
first_carrier_offset
,
i
+
n
,
re_offset
,
amp
,
frame_parms
->
ofdm_symbol_size
,
frame_parms
->
N_RB_DL
,
frame_parms
->
first_carrier_offset
,
i
+
n
,
re_offset
,
l
,
n
,((
int16_t
*
)
&
txdataF
[
0
][
re_offset
])[
0
],((
int16_t
*
)
&
txdataF
[
0
][
re_offset
])[
1
]);
l
,
n
,((
int16_t
*
)
&
txdataF
[
0
][
re_offset
])[
0
],((
int16_t
*
)
&
txdataF
[
0
][
re_offset
])[
1
]);
#endif
#endif
// printf("gNb l=%d\ti=%d\treoffset=%d\tre=%d\tim=%d\n",l,i,re_offset,z_dmrs_re[i+n],z_dmrs_im[i+n]);
}
}
re_offset
++
;
re_offset
++
;
...
...
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
View file @
8fdc21b2
...
@@ -42,10 +42,25 @@
...
@@ -42,10 +42,25 @@
#include "T.h"
#include "T.h"
#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2)
#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2)
void
nr_decode_pucch1
(
int32_t
**
rxdataF
,
pucch_GroupHopping_t
pucch_GroupHopping
,
uint32_t
n_id
,
// hoppingID higher layer parameter
uint64_t
*
payload
,
NR_DL_FRAME_PARMS
*
frame_parms
,
int16_t
amp
,
int
nr_tti_tx
,
uint8_t
m0
,
uint8_t
nrofSymbols
,
uint8_t
startingSymbolIndex
,
uint16_t
startingPRB
,
uint16_t
startingPRB_intraSlotHopping
,
uint8_t
timeDomainOCC
,
uint8_t
nr_bit
);
void
nr_decode_pucch0
(
int32_t
**
rxdataF
,
void
nr_decode_pucch0
(
int32_t
**
rxdataF
,
pucch_GroupHopping_t
PUCCH_GroupHopping
,
pucch_GroupHopping_t
PUCCH_GroupHopping
,
uint32_t
n_id
,
//PHY_VARS_gNB *gNB, generally rxdataf is in gNB->common_vars
uint32_t
n_id
,
//PHY_VARS_gNB *gNB, generally rxdataf is in gNB->common_vars
uint
8
_t
*
payload
,
uint
64
_t
*
payload
,
NR_DL_FRAME_PARMS
*
frame_parms
,
NR_DL_FRAME_PARMS
*
frame_parms
,
int16_t
amp
,
int16_t
amp
,
int
nr_tti_tx
,
int
nr_tti_tx
,
...
...
openair1/SIMULATION/NR_PHY/pucchsim.c
View file @
8fdc21b2
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