Merge branch 'develop-uedirectorysplit' of...

Merge branch 'develop-uedirectorysplit' of https://gitlab.eurecom.fr/oai/openairinterface5g into develop-uedirectorysplit

Conflicts:
	cmake_targets/CMakeLists.txt
	openair1/PHY/LTE_ESTIMATION/lte_adjust_sync.c
	openair1/PHY/LTE_UE_TRANSPORT/dci_ue.c

cmake_targets/CMakeLists.txt

@@ -1159,7 +1159,7 @@ set(PHY_SRC_UE
   ${OPENAIR1_DIR}/PHY/MODULATION/ul_7_5_kHz_ue.c
   ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_sync_time.c
   ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_sync_timefreq.c
-  ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_adjust_sync.c
+  ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c
   ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_dl_channel_estimation.c
   ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_dl_bf_channel_estimation.c
   ${OPENAIR1_DIR}/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c
@@ -1281,12 +1281,12 @@ set(L2_SRC_UE
 set (MAC_SRC
   ${PHY_INTERFACE_DIR}/IF_Module.c
   ${MAC_DIR}/main.c
-  ${MAC_DIR}/main_ue.c
-  ${MAC_DIR}/ue_procedures.c
-  ${MAC_DIR}/ra_procedures.c
+  #${MAC_DIR}/main_ue.c
+  #${MAC_DIR}/ue_procedures.c
+  #${MAC_DIR}/ra_procedures.c
   ${MAC_DIR}/l1_helpers.c
   ${MAC_DIR}/rar_tools.c
-  ${MAC_DIR}/rar_tools_ue.c
+  #${MAC_DIR}/rar_tools_ue.c
   ${MAC_DIR}/eNB_scheduler.c
   ${MAC_DIR}/eNB_scheduler_dlsch.c
   ${MAC_DIR}/eNB_scheduler_ulsch.c
@@ -1296,7 +1296,7 @@ set (MAC_SRC
   ${MAC_DIR}/eNB_scheduler_RA.c
   ${MAC_DIR}/pre_processor.c
   ${MAC_DIR}/config.c
-  ${MAC_DIR}/config_ue.c
+  #${MAC_DIR}/config_ue.c
  )
 
 set (MAC_SRC_UE

openair1/PHY/LTE_ESTIMATION/lte_adjust_sync.c

@@ -135,5 +135,3 @@ void lte_adjust_synch(LTE_DL_FRAME_PARMS *frame_parms,
       VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ADJUST_SYNCH, VCD_FUNCTION_OUT);
   }
 }
-
-

openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#include "PHY/types.h"
+#include "PHY/defs_eNB.h"
+#include "PHY/phy_extern.h"
+
+#include "UTIL/LOG/vcd_signal_dumper.h"
+
+#define DEBUG_PHY
+
+int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms,
+                           LTE_eNB_SRS *lte_eNB_srs,
+                           unsigned int  *eNB_id,
+                           unsigned char clear,
+                           unsigned char number_of_cards,
+                           short coef)
+
+{
+
+  static int max_pos_fil2 = 0;
+  int temp, i, aa, max_pos = 0,ind;
+  int max_val=0;
+  short Re,Im,ncoef;
+#ifdef DEBUG_PHY
+  char fname[100],vname[100];
+#endif
+
+  ncoef = 32768 - coef;
+
+  for (ind=0; ind<number_of_cards; ind++) {
+
+    if (ind==0)
+      max_val=0;
+
+
+    for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
+      // do ifft of channel estimate
+      switch(frame_parms->N_RB_DL) {
+      case 6:
+	dft128((int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
+	       (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
+	       1);
+	break;
+      case 25:
+	dft512((int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
+	       (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
+	       1);
+	break;
+      case 50:
+	dft1024((int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
+		(int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
+		1);
+	break;
+      case 100:
+	dft2048((int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
+	       (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
+	       1);
+	break;
+      }
+#ifdef DEBUG_PHY
+      sprintf(fname,"srs_ch_estimates_time_%d%d.m",ind,aa);
+      sprintf(vname,"srs_time_%d%d",ind,aa);
+      write_output(fname,vname,lte_eNB_srs->srs_ch_estimates_time[aa],frame_parms->ofdm_symbol_size*2,2,1);
+#endif
+    }
+
+    // we only use channel estimates from tx antenna 0 here
+    // remember we fixed the SRS to use only every second subcarriers
+    for (i = 0; i < frame_parms->ofdm_symbol_size/2; i++) {
+      temp = 0;
+
+      for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
+        Re = ((int16_t*)lte_eNB_srs->srs_ch_estimates_time[aa])[(i<<1)];
+        Im = ((int16_t*)lte_eNB_srs->srs_ch_estimates_time[aa])[1+(i<<1)];
+        temp += (Re*Re/2) + (Im*Im/2);
+      }
+
+      if (temp > max_val) {
+        max_pos = i;
+        max_val = temp;
+        *eNB_id = ind;
+      }
+    }
+  }
+
+  // filter position to reduce jitter
+  if (clear == 1)
+    max_pos_fil2 = max_pos;
+  else
+    max_pos_fil2 = ((max_pos_fil2 * coef) + (max_pos * ncoef)) >> 15;
+
+  return(max_pos_fil2);
+}
+
+
+int lte_est_timing_advance_pusch(PHY_VARS_eNB* eNB,uint8_t UE_id)
+{
+  int temp, i, aa, max_pos=0, max_val=0;
+  short Re,Im;
+
+  LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
+  LTE_eNB_PUSCH *eNB_pusch_vars = eNB->pusch_vars[UE_id];
+  int32_t **ul_ch_estimates_time=  eNB_pusch_vars->drs_ch_estimates_time;
+  uint8_t cyclic_shift = 0;
+  int sync_pos = (frame_parms->ofdm_symbol_size-cyclic_shift*frame_parms->ofdm_symbol_size/12)%(frame_parms->ofdm_symbol_size);
+
+  AssertFatal(frame_parms->ofdm_symbol_size > 127,"frame_parms->ofdm_symbol_size %d<128\n",frame_parms->ofdm_symbol_size);
+  AssertFatal(frame_parms->nb_antennas_rx >0 && frame_parms->nb_antennas_rx<3,"frame_parms->nb_antennas_rx %d not in [0,1]\n",
+	      frame_parms->nb_antennas_rx);
+  for (i = 0; i < frame_parms->ofdm_symbol_size; i++) {
+    temp = 0;
+
+    for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
+      Re = ((int16_t*)ul_ch_estimates_time[aa])[(i<<1)];
+      Im = ((int16_t*)ul_ch_estimates_time[aa])[1+(i<<1)];
+      temp += (Re*Re/2) + (Im*Im/2);
+    }
+
+    if (temp > max_val) {
+      max_pos = i;
+      max_val = temp;
+    }
+  }
+
+  if (max_pos>frame_parms->ofdm_symbol_size/2)
+    max_pos = max_pos-frame_parms->ofdm_symbol_size;
+
+  //#ifdef DEBUG_PHY
+  LOG_D(PHY,"frame %d: max_pos = %d, sync_pos=%d\n",eNB->proc.frame_rx,max_pos,sync_pos);
+  //#endif //DEBUG_PHY
+
+  return max_pos - sync_pos;
+}
+

openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#include "PHY/types.h"
+#include "PHY/defs_UE.h"
+#include "PHY/LTE_ESTIMATION/lte_estimation_defs.h"
+#include "PHY/impl_defs_top.h"
+
+#include "UTIL/LOG/vcd_signal_dumper.h"
+
+#define DEBUG_PHY
+
+// Adjust location synchronization point to account for drift
+// The adjustment is performed once per frame based on the
+// last channel estimate of the receiver
+
+void lte_adjust_synch(LTE_DL_FRAME_PARMS *frame_parms,
+                      PHY_VARS_UE *ue,
+                      unsigned char eNB_id,
+					  uint8_t subframe,
+                      unsigned char clear,
+                      short coef)
+{
+
+  static int max_pos_fil = 0;
+  static int count_max_pos_ok = 0;
+  static int first_time = 1;
+  int temp = 0, i, aa, max_val = 0, max_pos = 0;
+  int diff;
+  short Re,Im,ncoef;
+
+  VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ADJUST_SYNCH, VCD_FUNCTION_IN);
+
+  ncoef = 32767 - coef;
+
+#ifdef DEBUG_PHY
+  LOG_D(PHY,"AbsSubframe %d.%d: rx_offset (before) = %d\n",ue->proc.proc_rxtx[0].frame_rx%1024,subframe,ue->rx_offset);
+#endif //DEBUG_PHY
+
+
+  // we only use channel estimates from tx antenna 0 here
+  for (i = 0; i < frame_parms->nb_prefix_samples; i++) {
+    temp = 0;
+
+    for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
+      Re = ((int16_t*)ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_id][aa])[(i<<2)];
+      Im = ((int16_t*)ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_id][aa])[1+(i<<2)];
+      temp += (Re*Re/2) + (Im*Im/2);
+    }
+
+    if (temp > max_val) {
+      max_pos = i;
+      max_val = temp;
+    }
+  }
+
+  // filter position to reduce jitter
+  if (clear == 1)
+    max_pos_fil = max_pos;
+  else
+    max_pos_fil = ((max_pos_fil * coef) + (max_pos * ncoef)) >> 15;
+
+  // do not filter to have proactive timing adjustment
+  max_pos_fil = max_pos;
+
+  if(subframe == 6)
+  {
+      diff = max_pos_fil - (frame_parms->nb_prefix_samples>>3);
+
+      if ( abs(diff) < SYNCH_HYST )
+          ue->rx_offset = 0;
+      else
+          ue->rx_offset = diff;
+
+      if(abs(diff)<5)
+          count_max_pos_ok ++;
+      else
+          count_max_pos_ok = 0;
+
+      if(count_max_pos_ok > 10 && first_time == 1)
+      {
+          first_time = 0;
+          ue->time_sync_cell = 1;
+          if (ue->mac_enabled==1) {
+              LOG_I(PHY,"[UE%d] Sending synch status to higher layers\n",ue->Mod_id);
+              //mac_resynch();
+              dl_phy_sync_success(ue->Mod_id,ue->proc.proc_rxtx[0].frame_rx,0,1);//ue->common_vars.eNb_id);
+              ue->UE_mode[0] = PRACH;
+          }
+          else {
+              ue->UE_mode[0] = PUSCH;
+          }
+      }
+
+      if ( ue->rx_offset < 0 )
+          ue->rx_offset += FRAME_LENGTH_COMPLEX_SAMPLES;
+
+      if ( ue->rx_offset >= FRAME_LENGTH_COMPLEX_SAMPLES )
+          ue->rx_offset -= FRAME_LENGTH_COMPLEX_SAMPLES;
+
+
+
+      #ifdef DEBUG_PHY
+      LOG_D(PHY,"AbsSubframe %d.%d: ThreadId %d diff =%i rx_offset (final) = %i : clear %d,max_pos = %d,max_pos_fil = %d (peak %d) max_val %d target_pos %d \n",
+              ue->proc.proc_rxtx[ue->current_thread_id[subframe]].frame_rx,
+              subframe,
+              ue->current_thread_id[subframe],
+              diff,
+              ue->rx_offset,
+              clear,
+              max_pos,
+              max_pos_fil,
+              temp,max_val,
+              (frame_parms->nb_prefix_samples>>3));
+      #endif //DEBUG_PHY
+
+      VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ADJUST_SYNCH, VCD_FUNCTION_OUT);
+  }
+}

openair1/PHY/LTE_TRANSPORT/dci_tools_common.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/LTE_TRANSPORT/dci_tools.c
+ * \brief PHY Support routines (eNB/UE) for filling PDSCH/PUSCH/DLSCH/ULSCH data structures based on DCI PDUs generated by eNB MAC scheduler.
+ * \author R. Knopp
+ * \date 2011
+ * \version 0.1
+ * \company Eurecom
+ * \email: knopp@eurecom.fr
+ * \note
+ * \warning
+ */
+
+#include "PHY/defs_eNB.h"
+#include "PHY/phy_extern.h"
+#include "SCHED/sched_eNB.h"
+#ifdef DEBUG_DCI_TOOLS
+#include "PHY/phy_vars.h"
+#endif
+#include "assertions.h"
+#include "nfapi_interface.h"
+
+//#define DEBUG_HARQ
+
+
+#include "LAYER2/MAC/mac.h"
+
+//#define DEBUG_DCI
+
+uint32_t localRIV2alloc_LUT6[32];
+uint32_t distRIV2alloc_even_LUT6[32];
+uint32_t distRIV2alloc_odd_LUT6[32];
+uint16_t RIV2nb_rb_LUT6[32];
+uint16_t RIV2first_rb_LUT6[32];
+uint16_t RIV_max6=0;
+
+uint32_t localRIV2alloc_LUT25[512];
+uint32_t distRIV2alloc_even_LUT25[512];
+uint32_t distRIV2alloc_odd_LUT25[512];
+uint16_t RIV2nb_rb_LUT25[512];
+uint16_t RIV2first_rb_LUT25[512];
+uint16_t RIV_max25=0;
+
+
+uint32_t localRIV2alloc_LUT50_0[1600];
+uint32_t localRIV2alloc_LUT50_1[1600];
+uint32_t distRIV2alloc_gap0_even_LUT50_0[1600];
+uint32_t distRIV2alloc_gap0_odd_LUT50_0[1600];
+uint32_t distRIV2alloc_gap0_even_LUT50_1[1600];
+uint32_t distRIV2alloc_gap0_odd_LUT50_1[1600];
+uint32_t distRIV2alloc_gap1_even_LUT50_0[1600];
+uint32_t distRIV2alloc_gap1_odd_LUT50_0[1600];
+uint32_t distRIV2alloc_gap1_even_LUT50_1[1600];
+uint32_t distRIV2alloc_gap1_odd_LUT50_1[1600];
+uint16_t RIV2nb_rb_LUT50[1600];
+uint16_t RIV2first_rb_LUT50[1600];
+uint16_t RIV_max50=0;
+
+uint32_t localRIV2alloc_LUT100_0[6000];
+uint32_t localRIV2alloc_LUT100_1[6000];
+uint32_t localRIV2alloc_LUT100_2[6000];
+uint32_t localRIV2alloc_LUT100_3[6000];
+uint32_t distRIV2alloc_gap0_even_LUT100_0[6000];
+uint32_t distRIV2alloc_gap0_odd_LUT100_0[6000];
+uint32_t distRIV2alloc_gap0_even_LUT100_1[6000];
+uint32_t distRIV2alloc_gap0_odd_LUT100_1[6000];
+uint32_t distRIV2alloc_gap0_even_LUT100_2[6000];
+uint32_t distRIV2alloc_gap0_odd_LUT100_2[6000];
+uint32_t distRIV2alloc_gap0_even_LUT100_3[6000];
+uint32_t distRIV2alloc_gap0_odd_LUT100_3[6000];
+uint32_t distRIV2alloc_gap1_even_LUT100_0[6000];
+uint32_t distRIV2alloc_gap1_odd_LUT100_0[6000];
+uint32_t distRIV2alloc_gap1_even_LUT100_1[6000];
+uint32_t distRIV2alloc_gap1_odd_LUT100_1[6000];
+uint32_t distRIV2alloc_gap1_even_LUT100_2[6000];
+uint32_t distRIV2alloc_gap1_odd_LUT100_2[6000];
+uint32_t distRIV2alloc_gap1_even_LUT100_3[6000];
+uint32_t distRIV2alloc_gap1_odd_LUT100_3[6000];
+uint16_t RIV2nb_rb_LUT100[6000];
+uint16_t RIV2first_rb_LUT100[6000];
+uint16_t RIV_max100=0;
+
+
+extern uint32_t current_dlsch_cqi;
+
+// Table 8.6.3-3 36.213
+uint16_t beta_cqi[16] = {0,   //reserved
+                         0,   //reserved
+                         9,   //1.125
+                         10,  //1.250
+                         11,  //1.375
+                         13,  //1.625
+                         14,  //1.750
+                         16,  //2.000
+                         18,  //2.250
+                         20,  //2.500
+                         23,  //2.875
+                         25,  //3.125
+                         28,  //3.500
+                         32,  //4.000
+                         40,  //5.000
+                         50
+                        }; //6.250
+
+// Table 8.6.3-2 36.213
+uint16_t beta_ri[16] = {10,   //1.250
+                        13,   //1.625
+                        16,   //2.000
+                        20,   //2.500
+                        25,   //3.125
+                        32,   //4.000
+                        40,   //5.000
+                        50,   //6.250
+                        64,   //8.000
+                        80,   //10.000
+                        101,  //12.625
+                        127,  //15.875
+                        160,  //20.000
+                        0,    //reserved
+                        0,    //reserved
+                        0
+                       };   //reserved
+
+// Table 8.6.3-2 36.213
+uint16_t beta_ack[16] = {16,  //2.000
+                         20,  //2.500
+                         25,  //3.125
+                         32,  //4.000
+                         40,  //5.000
+                         50,  //6.250
+                         64,  //8.000
+                         80,  //10.000
+                         101, //12.625
+                         127, //15.875
+                         160, //20.000
+                         248, //31.000
+                         400, //50.000
+                         640, //80.000
+                         808
+                        };//126.00
+
+int8_t delta_PUSCH_abs[4] = {-4,-1,1,4};
+int8_t delta_PUSCH_acc[4] = {-1,0,1,3};
+
+int8_t *delta_PUCCH_lut = delta_PUSCH_acc;
+
+uint32_t check_phich_reg(LTE_DL_FRAME_PARMS *frame_parms,uint32_t kprime,uint8_t lprime,uint8_t mi)
+{
+
+  uint16_t i;
+  uint16_t Ngroup_PHICH = (frame_parms->phich_config_common.phich_resource*frame_parms->N_RB_DL)/48;
+  uint16_t mprime;
+  uint16_t *pcfich_reg = frame_parms->pcfich_reg;
+
+  if ((lprime>0) && (frame_parms->Ncp==0) )
+    return(0);
+
+  //  printf("check_phich_reg : mi %d\n",mi);
+
+  // compute REG based on symbol
+  if ((lprime == 0)||
+      ((lprime==1)&&(frame_parms->nb_antenna_ports_eNB == 4)))
+    mprime = kprime/6;
+  else
+    mprime = kprime>>2;
+
+  // check if PCFICH uses mprime
+  if ((lprime==0) &&
+      ((mprime == pcfich_reg[0]) ||
+       (mprime == pcfich_reg[1]) ||
+       (mprime == pcfich_reg[2]) ||
+       (mprime == pcfich_reg[3]))) {
+#ifdef DEBUG_DCI_ENCODING
+    printf("[PHY] REG %d allocated to PCFICH\n",mprime);
+#endif
+    return(1);
+  }
+
+  // handle Special subframe case for TDD !!!
+
+  //  printf("Checking phich_reg %d\n",mprime);
+  if (mi > 0) {
+    if (((frame_parms->phich_config_common.phich_resource*frame_parms->N_RB_DL)%48) > 0)
+      Ngroup_PHICH++;
+
+    if (frame_parms->Ncp == 1) {
+      Ngroup_PHICH<<=1;
+    }
+
+
+
+    for (i=0; i<Ngroup_PHICH; i++) {
+      if ((mprime == frame_parms->phich_reg[i][0]) ||
+          (mprime == frame_parms->phich_reg[i][1]) ||
+          (mprime == frame_parms->phich_reg[i][2]))  {
+#ifdef DEBUG_DCI_ENCODING
+        printf("[PHY] REG %d (lprime %d) allocated to PHICH\n",mprime,lprime);
+#endif
+        return(1);
+      }
+    }
+  }
+
+  return(0);
+}
+
+uint16_t get_nquad(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uint8_t mi)
+{
+
+  uint16_t Nreg=0;
+  uint8_t Ngroup_PHICH = (frame_parms->phich_config_common.phich_resource*frame_parms->N_RB_DL)/48;
+
+  if (((frame_parms->phich_config_common.phich_resource*frame_parms->N_RB_DL)%48) > 0)
+    Ngroup_PHICH++;
+
+  if (frame_parms->Ncp == 1) {
+    Ngroup_PHICH<<=1;
+  }
+
+  Ngroup_PHICH*=mi;
+
+  if ((num_pdcch_symbols>0) && (num_pdcch_symbols<4))
+    switch (frame_parms->N_RB_DL) {
+    case 6:
+      Nreg=12+(num_pdcch_symbols-1)*18;
+      break;
+
+    case 25:
+      Nreg=50+(num_pdcch_symbols-1)*75;
+      break;
+
+    case 50:
+      Nreg=100+(num_pdcch_symbols-1)*150;
+      break;
+
+    case 100:
+      Nreg=200+(num_pdcch_symbols-1)*300;
+      break;
+
+    default:
+      return(0);
+    }
+
+  //   printf("Nreg %d (%d)\n",Nreg,Nreg - 4 - (3*Ngroup_PHICH));
+  return(Nreg - 4 - (3*Ngroup_PHICH));
+}
+
+uint16_t get_nCCE(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uint8_t mi)
+{
+  return(get_nquad(num_pdcch_symbols,frame_parms,mi)/9);
+}
+
+
+
+uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe)
+{
+
+  // check for eNB only !
+  return(get_nCCE(num_pdcch_symbols,
+		  &RC.eNB[Mod_id][CC_id]->frame_parms,
+		  get_mi(&RC.eNB[Mod_id][CC_id]->frame_parms,subframe)));
+}
+
+
+void conv_eMTC_rballoc(uint16_t resource_block_coding,
+		       uint32_t N_RB_DL,
+		       uint32_t *rb_alloc) {
+
+   
+  int narrowband = resource_block_coding>>5;
+  int RIV        = resource_block_coding&31;
+  int N_NB_DL    = N_RB_DL/6;
+  int i0         = (N_RB_DL>>1) - (3*N_NB_DL);
+  int first_rb   = (6*narrowband)+i0;
+  int alloc      = localRIV2alloc_LUT6[RIV];
+  int ind        = first_rb>>5;
+  int ind_mod    = first_rb&31;
+
+  if (((N_RB_DL&1) > 0) && (narrowband>=(N_NB_DL>>1))) first_rb++;
+  rb_alloc[0]                        = 0;
+  rb_alloc[1]                        = 0;
+  rb_alloc[2]                        = 0;
+  rb_alloc[3]                        = 0;
+  rb_alloc[ind]                      = alloc<<ind_mod;
+  if (ind_mod > 26)  rb_alloc[ind+1] = alloc>>(6-(ind_mod-26)); 
+}
+
+void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t *rb_alloc2)
+{
+
+  uint32_t i,shift,subset;
+  rb_alloc2[0] = 0;
+  rb_alloc2[1] = 0;
+  rb_alloc2[2] = 0;
+  rb_alloc2[3] = 0;
+
+  //  printf("N_RB_DL %d, ra_header %d, rb_alloc %x\n",N_RB_DL,ra_header,rb_alloc);
+
+  switch (N_RB_DL) {
+
+  case 6:
+    rb_alloc2[0] = rb_alloc&0x3f;
+    break;
+
+  case 25:
+    if (ra_header == 0) {// Type 0 Allocation
+
+      for (i=12; i>0; i--) {
+        if ((rb_alloc&(1<<i)) != 0)
+          rb_alloc2[0] |= (3<<((2*(12-i))));
+
+        //      printf("rb_alloc2 (type 0) %x\n",rb_alloc2);
+      }
+
+      if ((rb_alloc&1) != 0)
+        rb_alloc2[0] |= (1<<24);
+    } else {
+      subset = rb_alloc&1;
+      shift  = (rb_alloc>>1)&1;
+
+      for (i=0; i<11; i++) {
+        if ((rb_alloc&(1<<(i+2))) != 0)
+          rb_alloc2[0] |= (1<<(2*i));
+
+        //printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
+      }
+
+      if ((shift == 0) && (subset == 1))
+        rb_alloc2[0]<<=1;
+      else if ((shift == 1) && (subset == 0))
+        rb_alloc2[0]<<=4;
+      else if ((shift == 1) && (subset == 1))
+        rb_alloc2[0]<<=3;
+    }
+
+    break;
+
+  case 50:
+    AssertFatal(ra_header==0,"resource type 1 not supported for  N_RB_DL=50\n");
+
+    for (i=16; i>0; i--) {
+      if ((rb_alloc&(1<<i)) != 0)
+	rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32));
+    }
+
+    // bit mask across
+    if ((rb_alloc2[0]>>31)==1)
+      rb_alloc2[1] |= 1;
+    
+    if ((rb_alloc&1) != 0)
+      rb_alloc2[1] |= (3<<16);
+    break;
+
+  case 100:
+    AssertFatal(ra_header==0,"resource type 1 not supported for  N_RB_DL=100\n");
+    for (i=0; i<25; i++) {
+      if ((rb_alloc&(1<<(24-i))) != 0)
+	rb_alloc2[(4*i)>>5] |= (0xf<<((4*i)%32));
+      
+      //  printf("rb_alloc2[%d] (type 0) %x (%d)\n",(4*i)>>5,rb_alloc2[(4*i)>>5],rb_alloc&(1<<i));
+    }
+
+    break;
+
+  default:
+    LOG_E(PHY,"Invalid N_RB_DL %d\n", N_RB_DL);
+    DevParam (N_RB_DL, 0, 0);
+    break;
+  }
+
+}
+
+
+
+uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL)
+{
+
+  uint32_t nprb=0,i;
+
+  switch (N_RB_DL) {
+  case 6:
+    for (i=0; i<6; i++) {
+      if ((rb_alloc&(1<<i)) != 0)
+        nprb += 1;
+    }
+
+    break;
+
+  case 25:
+    if (ra_header == 0) {// Type 0 Allocation
+
+      for (i=12; i>0; i--) {
+        if ((rb_alloc&(1<<i)) != 0)
+          nprb += 2;
+      }
+
+      if ((rb_alloc&1) != 0)
+        nprb += 1;
+    } else {
+      for (i=0; i<11; i++) {
+        if ((rb_alloc&(1<<(i+2))) != 0)
+          nprb += 1;
+      }
+    }
+
+    break;
+
+  case 50:
+    if (ra_header == 0) {// Type 0 Allocation
+
+      for (i=0; i<16; i++) {
+        if ((rb_alloc&(1<<(16-i))) != 0)
+          nprb += 3;
+      }
+
+      if ((rb_alloc&1) != 0)
+        nprb += 2;
+
+    } else {
+      for (i=0; i<17; i++) {
+        if ((rb_alloc&(1<<(i+2))) != 0)
+          nprb += 1;
+      }
+    }
+
+    break;
+
+  case 100:
+    if (ra_header == 0) {// Type 0 Allocation
+
+      for (i=0; i<25; i++) {
+        if ((rb_alloc&(1<<(24-i))) != 0)
+          nprb += 4;
+      }
+    } else {
+      for (i=0; i<25; i++) {
+        if ((rb_alloc&(1<<(i+2))) != 0)
+          nprb += 1;
+      }
+    }
+
+    break;
+
+  default:
+    LOG_E(PHY,"Invalide N_RB_DL %d\n", N_RB_DL);
+    DevParam (N_RB_DL, 0, 0);
+    break;
+  }
+
+  return(nprb);
+}
+
+uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs)
+{
+
+  uint16_t RIV;
+
+  if (Lcrbs<=(1+(N_RB_DL>>1)))
+    RIV = (N_RB_DL*(Lcrbs-1)) + RBstart;
+  else
+    RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart);
+
+  return(RIV);
+}
+
+// Convert a DCI Format 1C RIV to a Format 1A RIV
+// This extracts the start and length in PRBs from the 1C rballoc and
+// recomputes the RIV as if it were the 1A rballoc
+
+uint32_t conv_1C_RIV(int32_t rballoc,uint32_t N_RB_DL) {
+
+  int NpDLVRB,N_RB_step,LpCRBsm1,RBpstart;
+
+  switch (N_RB_DL) {
+
+  case 6: // N_RB_step = 2, NDLVRB = 6, NpDLVRB = 3
+    NpDLVRB   = 3;
+    N_RB_step = 2;
+    break;
+  case 25: // N_RB_step = 2, NDLVRB = 24, NpDLVRB = 12
+    NpDLVRB   = 12;
+    N_RB_step = 2;
+    break;
+  case 50: // N_RB_step = 4, NDLVRB = 46, NpDLVRB = 11
+    NpDLVRB   = 11;
+    N_RB_step = 4;
+    break;
+  case 100: // N_RB_step = 4, NDLVRB = 96, NpDLVRB = 24
+    NpDLVRB   = 24;
+    N_RB_step = 4;
+    break;
+  default:
+    NpDLVRB   = 24;
+    N_RB_step = 4;
+    break;
+  }
+
+  // This is the 1C part from 7.1.6.3 in 36.213
+  LpCRBsm1 = rballoc/NpDLVRB;
+  //  printf("LpCRBs = %d\n",LpCRBsm1+1);
+
+  if (LpCRBsm1 <= (NpDLVRB/2)) {
+    RBpstart = rballoc % NpDLVRB;
+  }
+  else {
+    LpCRBsm1 = NpDLVRB-LpCRBsm1;
+    RBpstart = NpDLVRB-(rballoc%NpDLVRB);
+  }
+  //  printf("RBpstart %d\n",RBpstart);
+  return(computeRIV(N_RB_DL,N_RB_step*RBpstart,N_RB_step*(LpCRBsm1+1)));
+
+}
+
+uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap) {
+
+  int offset;
+
+  switch (N_RB_DL) {
+
+  case 6:
+  // N_RB_DL = tildeN_RB_DL = 6
+  // Ngap = 4 , P=1, Nrow = 2, Nnull = 2
+
+    switch (vrb) {
+    case 0:  // even: 0->0, 1->2, odd: 0->3, 1->5
+    case 1:
+      return ((3*odd_slot) + 2*(vrb&3))%6;
+      break;
+    case 2:  // even: 2->3, 3->5, odd: 2->0, 3->2
+    case 3:
+      return ((3*odd_slot) + 2*(vrb&3) + 5)%6;
+      break;
+    case 4:  // even: 4->1, odd: 4->4
+      return ((3*odd_slot) + 1)%6;
+    case 5:  // even: 5->4, odd: 5->1
+      return ((3*odd_slot) + 4)%6;
+      break;
+    }
+    break;
+
+  case 15:
+    if (vrb<12) {
+      if ((vrb&3) < 2)     // even: 0->0, 1->4, 4->1, 5->5, 8->2, 9->6 odd: 0->7, 1->11
+  return(((7*odd_slot) + 4*(vrb&3) + (vrb>>2))%14) + 14*(vrb/14);
+      else if (vrb < 12) // even: 2->7, 3->11, 6->8, 7->12, 10->9, 11->13
+  return (((7*odd_slot) + 4*(vrb&3) + (vrb>>2) +13 )%14) + 14*(vrb/14);
+    }
+    if (vrb==12)
+      return (3+(7*odd_slot)) % 14;
+    if (vrb==13)
+      return (10+(7*odd_slot)) % 14;
+    return 14;
+    break;
+
+  case 25:
+    return (((12*odd_slot) + 6*(vrb&3) + (vrb>>2))%24) + 24*(vrb/24);
+    break;
+
+  case 50: // P=3
+    if (Ngap==0) {
+      // Nrow=12,Nnull=2,NVRBDL=46,Ngap1= 27
+      if (vrb>=23)
+  offset=4;
+      else
+  offset=0;
+      if (vrb<44) {
+  if ((vrb&3)>=2)
+    return offset+((23*odd_slot) + 12*(vrb&3) + (vrb>>2) + 45)%46;
+  else
+    return offset+((23*odd_slot) + 12*(vrb&3) + (vrb>>2))%46;
+      }
+      if (vrb==44)  // even: 44->11, odd: 45->34
+  return offset+((23*odd_slot) + 22-12+1);
+      if (vrb==45)  // even: 45->10, odd: 45->33
+  return offset+((23*odd_slot) + 22+12);
+      if (vrb==46)
+  return offset+46+((23*odd_slot) + 23-12+1) % 46;
+      if (vrb==47)
+  return offset+46+((23*odd_slot) + 23+12) % 46;
+      if (vrb==48)
+  return offset+46+((23*odd_slot) + 23-12+1) % 46;
+      if (vrb==49)
+  return offset+46+((23*odd_slot) + 23+12) % 46;
+    }
+    else {
+      // Nrow=6,Nnull=6,NVRBDL=18,Ngap1= 27
+      if (vrb>=9)
+  offset=18;
+      else
+  offset=0;
+
+      if (vrb<12) {
+  if ((vrb&3)>=2)
+    return offset+((9*odd_slot) + 6*(vrb&3) + (vrb>>2) + 17)%18;
+  else
+    return offset+((9*odd_slot) + 6*(vrb&3) + (vrb>>2))%18;
+      }
+      else {
+  return offset+((9*odd_slot) + 12*(vrb&1)+(vrb>>1) )%18 + 18*(vrb/18);
+      }
+    }
+    break;
+  case 75:
+    // Ngap1 = 32, NVRBRL=64, P=4, Nrow= 16, Nnull=0
+    if (Ngap ==0) {
+      return ((32*odd_slot) + 16*(vrb&3) + (vrb>>2))%64 + (vrb/64);
+    } else {
+      // Ngap2 = 16, NVRBDL=32, Nrow=8, Nnull=0
+      return ((16*odd_slot) + 8*(vrb&3) + (vrb>>2))%32 + (vrb/32);
+    }
+    break;
+  case 100:
+    // Ngap1 = 48, NVRBDL=96, Nrow=24, Nnull=0
+    if (Ngap ==0) {
+      return ((48*odd_slot) + 24*(vrb&3) + (vrb>>2))%96 + (vrb/96);
+    } else {
+      // Ngap2 = 16, NVRBDL=32, Nrow=8, Nnull=0
+      return ((16*odd_slot) + 8*(vrb&3) + (vrb>>2))%32 + (vrb/32);
+    }
+    break;
+  default:
+    LOG_E(PHY,"Unknown N_RB_DL %d\n",N_RB_DL);
+    return 0;
+  }
+  return 0;
+
+}
+
+
+void generate_RIV_tables(void)
+{
+
+  // 6RBs localized RIV
+  uint8_t Lcrbs,RBstart;
+  uint16_t RIV;
+  uint32_t alloc0,allocdist0_0_even,allocdist0_0_odd,allocdist0_1_even,allocdist0_1_odd;
+  uint32_t alloc1,allocdist1_0_even,allocdist1_0_odd,allocdist1_1_even,allocdist1_1_odd;
+  uint32_t alloc2,allocdist2_0_even,allocdist2_0_odd,allocdist2_1_even,allocdist2_1_odd;
+  uint32_t alloc3,allocdist3_0_even,allocdist3_0_odd,allocdist3_1_even,allocdist3_1_odd;
+  uint32_t nVRB,nVRB_even_dist,nVRB_odd_dist;
+
+  for (RBstart=0; RBstart<6; RBstart++) {
+    alloc0 = 0;
+    allocdist0_0_even = 0;
+    allocdist0_0_odd  = 0;
+    for (Lcrbs=1; Lcrbs<=(6-RBstart); Lcrbs++) {
+      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
+      nVRB             = Lcrbs-1+RBstart;
+      alloc0          |= (1<<nVRB);
+      allocdist0_0_even |= (1<<get_prb(6,0,nVRB,0));
+      allocdist0_0_odd  |= (1<<get_prb(6,1,nVRB,0));
+      RIV=computeRIV(6,RBstart,Lcrbs);
+
+      if (RIV>RIV_max6)
+        RIV_max6 = RIV;
+
+      //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
+      localRIV2alloc_LUT6[RIV] = alloc0;
+      distRIV2alloc_even_LUT6[RIV]  = allocdist0_0_even;
+      distRIV2alloc_odd_LUT6[RIV]  = allocdist0_0_odd;
+      RIV2nb_rb_LUT6[RIV]      = Lcrbs;
+      RIV2first_rb_LUT6[RIV]   = RBstart;
+    }
+  }
+
+
+  for (RBstart=0; RBstart<25; RBstart++) {
+    alloc0 = 0;
+    allocdist0_0_even = 0;
+    allocdist0_0_odd  = 0;
+    for (Lcrbs=1; Lcrbs<=(25-RBstart); Lcrbs++) {
+      nVRB = Lcrbs-1+RBstart;
+      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
+      alloc0     |= (1<<nVRB);
+      allocdist0_0_even |= (1<<get_prb(25,0,nVRB,0));
+      allocdist0_0_odd  |= (1<<get_prb(25,1,nVRB,0));
+
+      //printf("alloc 0 %x, allocdist0_even %x, allocdist0_odd %x\n",alloc0,allocdist0_0_even,allocdist0_0_odd);
+      RIV=computeRIV(25,RBstart,Lcrbs);
+
+      if (RIV>RIV_max25)
+        RIV_max25 = RIV;;
+
+
+      localRIV2alloc_LUT25[RIV]      = alloc0;
+      distRIV2alloc_even_LUT25[RIV]  = allocdist0_0_even;
+      distRIV2alloc_odd_LUT25[RIV]   = allocdist0_0_odd;
+      RIV2nb_rb_LUT25[RIV]           = Lcrbs;
+      RIV2first_rb_LUT25[RIV]        = RBstart;
+    }
+  }
+
+
+  for (RBstart=0; RBstart<50; RBstart++) {
+    alloc0 = 0;
+    alloc1 = 0;
+    allocdist0_0_even=0;
+    allocdist1_0_even=0;
+    allocdist0_0_odd=0;
+    allocdist1_0_odd=0;
+    allocdist0_1_even=0;
+    allocdist1_1_even=0;
+    allocdist0_1_odd=0;
+    allocdist1_1_odd=0;
+
+    for (Lcrbs=1; Lcrbs<=(50-RBstart); Lcrbs++) {
+
+      nVRB = Lcrbs-1+RBstart;
+
+
+      if (nVRB<32)
+        alloc0 |= (1<<nVRB);
+      else
+        alloc1 |= (1<<(nVRB-32));
+
+      // Distributed Gap1, even slot
+      nVRB_even_dist = get_prb(50,0,nVRB,0);
+      if (nVRB_even_dist<32)
+        allocdist0_0_even |= (1<<nVRB_even_dist);
+      else
+        allocdist1_0_even |= (1<<(nVRB_even_dist-32));
+
+      // Distributed Gap1, odd slot
+      nVRB_odd_dist = get_prb(50,1,nVRB,0);
+      if (nVRB_odd_dist<32)
+        allocdist0_0_odd |= (1<<nVRB_odd_dist);
+      else
+        allocdist1_0_odd |= (1<<(nVRB_odd_dist-32));
+
+      // Distributed Gap2, even slot
+      nVRB_even_dist = get_prb(50,0,nVRB,1);
+      if (nVRB_even_dist<32)
+        allocdist0_1_even |= (1<<nVRB_even_dist);
+      else
+        allocdist1_1_even |= (1<<(nVRB_even_dist-32));
+
+      // Distributed Gap2, odd slot
+      nVRB_odd_dist = get_prb(50,1,nVRB,1);
+      if (nVRB_odd_dist<32)
+        allocdist0_1_odd |= (1<<nVRB_odd_dist);
+      else
+        allocdist1_1_odd |= (1<<(nVRB_odd_dist-32));
+
+      RIV=computeRIV(50,RBstart,Lcrbs);
+
+      if (RIV>RIV_max50)
+        RIV_max50 = RIV;
+
+      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
+      localRIV2alloc_LUT50_0[RIV]      = alloc0;
+      localRIV2alloc_LUT50_1[RIV]      = alloc1;
+      distRIV2alloc_gap0_even_LUT50_0[RIV]  = allocdist0_0_even;
+      distRIV2alloc_gap0_even_LUT50_1[RIV]  = allocdist1_0_even;
+      distRIV2alloc_gap0_odd_LUT50_0[RIV]   = allocdist0_0_odd;
+      distRIV2alloc_gap0_odd_LUT50_1[RIV]   = allocdist1_0_odd;
+      distRIV2alloc_gap1_even_LUT50_0[RIV]  = allocdist0_1_even;
+      distRIV2alloc_gap1_even_LUT50_1[RIV]  = allocdist1_1_even;
+      distRIV2alloc_gap1_odd_LUT50_0[RIV]   = allocdist0_1_odd;
+      distRIV2alloc_gap1_odd_LUT50_1[RIV]   = allocdist1_1_odd;
+      RIV2nb_rb_LUT50[RIV]        = Lcrbs;
+      RIV2first_rb_LUT50[RIV]     = RBstart;
+    }
+  }
+
+
+  for (RBstart=0; RBstart<100; RBstart++) {
+    alloc0 = 0;
+    alloc1 = 0;
+    alloc2 = 0;
+    alloc3 = 0;
+    allocdist0_0_even=0;
+    allocdist1_0_even=0;
+    allocdist2_0_even=0;
+    allocdist3_0_even=0;
+    allocdist0_0_odd=0;
+    allocdist1_0_odd=0;
+    allocdist2_0_odd=0;
+    allocdist3_0_odd=0;
+    allocdist0_1_even=0;
+    allocdist1_1_even=0;
+    allocdist2_1_even=0;
+    allocdist3_1_even=0;
+    allocdist0_1_odd=0;
+    allocdist1_1_odd=0;
+    allocdist2_1_odd=0;
+    allocdist3_1_odd=0;
+
+    for (Lcrbs=1; Lcrbs<=(100-RBstart); Lcrbs++) {
+
+      nVRB = Lcrbs-1+RBstart;
+
+      if (nVRB<32)
+        alloc0 |= (1<<nVRB);
+      else if (nVRB<64)
+        alloc1 |= (1<<(nVRB-32));
+      else if (nVRB<96)
+        alloc2 |= (1<<(nVRB-64));
+      else
+        alloc3 |= (1<<(nVRB-96));
+
+      // Distributed Gap1, even slot
+      nVRB_even_dist = get_prb(100,0,nVRB,0);
+
+//      if ((RBstart==0) && (Lcrbs<=8))
+//  printf("nVRB %d => nVRB_even_dist %d\n",nVRB,nVRB_even_dist);
+
+
+      if (nVRB_even_dist<32)
+        allocdist0_0_even |= (1<<nVRB_even_dist);
+      else if (nVRB_even_dist<64)
+        allocdist1_0_even |= (1<<(nVRB_even_dist-32));
+      else if (nVRB_even_dist<96)
+  allocdist2_0_even |= (1<<(nVRB_even_dist-64));
+      else
+  allocdist3_0_even |= (1<<(nVRB_even_dist-96));
+/*      if ((RBstart==0) && (Lcrbs<=8))
+  printf("rballoc =>(%08x.%08x.%08x.%08x)\n",
+         allocdist0_0_even,
+         allocdist1_0_even,
+         allocdist2_0_even,
+         allocdist3_0_even
+         );
+*/
+      // Distributed Gap1, odd slot
+      nVRB_odd_dist = get_prb(100,1,nVRB,0);
+      if (nVRB_odd_dist<32)
+        allocdist0_0_odd |= (1<<nVRB_odd_dist);
+      else if (nVRB_odd_dist<64)
+        allocdist1_0_odd |= (1<<(nVRB_odd_dist-32));
+      else if (nVRB_odd_dist<96)
+  allocdist2_0_odd |= (1<<(nVRB_odd_dist-64));
+      else
+  allocdist3_0_odd |= (1<<(nVRB_odd_dist-96));
+
+
+      // Distributed Gap2, even slot
+      nVRB_even_dist = get_prb(100,0,nVRB,1);
+      if (nVRB_even_dist<32)
+        allocdist0_1_even |= (1<<nVRB_even_dist);
+      else if (nVRB_even_dist<64)
+        allocdist1_1_even |= (1<<(nVRB_even_dist-32));
+      else if (nVRB_even_dist<96)
+  allocdist2_1_even |= (1<<(nVRB_even_dist-64));
+      else
+  allocdist3_1_even |= (1<<(nVRB_even_dist-96));
+
+
+      // Distributed Gap2, odd slot
+      nVRB_odd_dist = get_prb(100,1,nVRB,1);
+      if (nVRB_odd_dist<32)
+        allocdist0_1_odd |= (1<<nVRB_odd_dist);
+      else if (nVRB_odd_dist<64)
+        allocdist1_1_odd |= (1<<(nVRB_odd_dist-32));
+      else if (nVRB_odd_dist<96)
+  allocdist2_1_odd |= (1<<(nVRB_odd_dist-64));
+      else
+  allocdist3_1_odd |= (1<<(nVRB_odd_dist-96));
+
+
+      RIV=computeRIV(100,RBstart,Lcrbs);
+
+      if (RIV>RIV_max100)
+        RIV_max100 = RIV;
+
+      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
+      localRIV2alloc_LUT100_0[RIV] = alloc0;
+      localRIV2alloc_LUT100_1[RIV] = alloc1;
+      localRIV2alloc_LUT100_2[RIV] = alloc2;
+      localRIV2alloc_LUT100_3[RIV] = alloc3;
+      distRIV2alloc_gap0_even_LUT100_0[RIV]  = allocdist0_0_even;
+      distRIV2alloc_gap0_even_LUT100_1[RIV]  = allocdist1_0_even;
+      distRIV2alloc_gap0_even_LUT100_2[RIV]  = allocdist2_0_even;
+      distRIV2alloc_gap0_even_LUT100_3[RIV]  = allocdist3_0_even;
+      distRIV2alloc_gap0_odd_LUT100_0[RIV]   = allocdist0_0_odd;
+      distRIV2alloc_gap0_odd_LUT100_1[RIV]   = allocdist1_0_odd;
+      distRIV2alloc_gap0_odd_LUT100_2[RIV]   = allocdist2_0_odd;
+      distRIV2alloc_gap0_odd_LUT100_3[RIV]   = allocdist3_0_odd;
+      distRIV2alloc_gap1_even_LUT100_0[RIV]  = allocdist0_1_even;
+      distRIV2alloc_gap1_even_LUT100_1[RIV]  = allocdist1_1_even;
+      distRIV2alloc_gap1_even_LUT100_2[RIV]  = allocdist2_1_even;
+      distRIV2alloc_gap1_even_LUT100_3[RIV]  = allocdist3_1_even;
+      distRIV2alloc_gap1_odd_LUT100_0[RIV]   = allocdist0_1_odd;
+      distRIV2alloc_gap1_odd_LUT100_1[RIV]   = allocdist1_1_odd;
+      distRIV2alloc_gap1_odd_LUT100_2[RIV]   = allocdist2_1_odd;
+      distRIV2alloc_gap1_odd_LUT100_3[RIV]   = allocdist3_1_odd;
+
+      RIV2nb_rb_LUT100[RIV]      = Lcrbs;
+      RIV2first_rb_LUT100[RIV]   = RBstart;
+    }
+  }
+}
+
+// Ngap = 3, N_VRB_DL=6, P=1, N_row=2, N_null=4*2-6=2
+// permutation for even slots :
+//    n_PRB'(0,2,4) = (0,1,2), n_PRB'(1,3,5) = (4,5,6)
+//    n_PRB''(0,1,2,3) = (0,2,4,6)
+//    => n_tilde_PRB(5) = (4)
+//       n_tilde_PRB(4) = (1)
+//       n_tilde_PRB(2,3) = (3,5)
+//       n_tilde_PRB(0,1) = (0,2)
+
+uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci)
+{
+
+  return(localRIV2alloc_LUT25[rb_alloc_dci]);
+
+}
+
+int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci)
+{
+  switch (dci->format) {
+
+  case format0:   // This is an UL SCH allocation so nothing here, inform MAC
+    if ((frame_parms->frame_type == TDD) &&
+        (frame_parms->tdd_config>0))
+      switch(frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format0 (TDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
+              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format0 (TDD1-6, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
+              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format0 (TDD1-6, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
+              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format0 (TDD1-6, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
+              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+    else if (frame_parms->frame_type == FDD)
+      switch(frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format0 (FDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format0 (FDD, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format0 (FDD, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format0 (FDD, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu[0])[0],
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
+              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+    else
+      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
+
+    break;
+
+  case format1:
+    if ((frame_parms->frame_type == TDD) &&
+        (frame_parms->tdd_config>0))
+
+      switch(frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format1 (TDD 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format1 (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format1 (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format1 (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
+              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+    else if (frame_parms->frame_type == FDD) {
+      switch(frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format1 (FDD, 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format1 (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format1 (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format1 (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
+              dci->rnti,
+              ((uint32_t*)&dci->dci_pdu)[0],
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rah,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rv,
+              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+    }
+
+    else
+      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
+
+    break;
+
+  case format1A:  // This is DLSCH allocation for control traffic
+    if ((frame_parms->frame_type == TDD) &&
+        (frame_parms->tdd_config>0)) {
+      switch (frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format1A (TDD1-6, 1_5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
+        LOG_D(PHY,"DAI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format1A (TDD1-6, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %d (NB_RB %d)\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
+        LOG_D(PHY,"DAI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format1A (TDD1-6, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
+        LOG_D(PHY,"DAI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format1A (TDD1-6, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT100[((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
+        LOG_D(PHY,"DAI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+
+    } else if (frame_parms->frame_type == FDD) {
+      switch (frame_parms->N_RB_DL) {
+      case 6:
+        LOG_D(PHY,"DCI format1A(FDD, 1.5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 25:
+        LOG_D(PHY,"DCI format1A(FDD, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 50:
+        LOG_D(PHY,"DCI format1A(FDD, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      case 100:
+        LOG_D(PHY,"DCI format1A(FDD, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
+        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT100[((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
+        LOG_D(PHY,"MCS %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
+        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
+        LOG_D(PHY,"NDI %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
+        LOG_D(PHY,"RV %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rv);
+        LOG_D(PHY,"TPC %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
+        break;
+
+      default:
+        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+      }
+    }
+
+    break;
+
+  case format1C:  // This is DLSCH allocation for control traffic
+    switch (frame_parms->N_RB_DL) {
+    case 6:
+      LOG_D(PHY,"DCI format1C (1.5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",
+      ((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT6[conv_1C_RIV(((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->rballoc,6)]);
+      LOG_D(PHY,"MCS %d\n",((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->mcs);
+      break;
+
+    case 25:
+      LOG_D(PHY,"DCI format1C (5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_5MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[conv_1C_RIV(((DCI1C_5MHz_t *)&dci->dci_pdu[0])->rballoc,25)]);
+      LOG_D(PHY,"MCS %d\n",((DCI1C_5MHz_t *)&dci->dci_pdu[0])->mcs);
+      break;
+
+    case 50:
+      LOG_D(PHY,"DCI format1C (10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+      LOG_D(PHY,"Ngap %d\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->Ngap);
+      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[conv_1C_RIV(((DCI1C_10MHz_t *)&dci->dci_pdu[0])->rballoc,50)]);
+      LOG_D(PHY,"MCS %d\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->mcs);
+      break;
+
+    case 100:
+      LOG_D(PHY,"DCI format1C (20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
+      LOG_D(PHY,"Ngap %d\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->Ngap);
+      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[conv_1C_RIV(((DCI1C_20MHz_t *)&dci->dci_pdu[0])->rballoc,100)]);
+      LOG_D(PHY,"MCS %d\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->mcs);
+      break;
+
+
+    default:
+      LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+        DevParam (frame_parms->N_RB_DL, 0, 0);
+        break;
+    }
+
+
+    break;
+
+  case format2:
+
+    if ((frame_parms->frame_type == TDD) &&
+        (frame_parms->tdd_config>0)) {
+      if (frame_parms->nb_antenna_ports_eNB == 2) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi
+               );
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi
+               );
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2 2 antennas (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      }
+    } else if (frame_parms->frame_type == FDD) {
+      if (frame_parms->nb_antenna_ports_eNB == 2) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2 2 antennas (FDD, 1.5 MHz), rnti %x (%x):  rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 25:
+
+          LOG_D(PHY,"DCI format2 2 antennas (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, swap %d, TPMI %d, TPC %d\n",
+
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2 2 antennas (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2 2 antennas (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
+        switch(frame_parms->N_RB_DL) {
+
+        case 6:
+          LOG_D(PHY,"DCI format2 4 antennas (FDD, 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2 4 antennas (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2 4 antennas (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2 4 antennas (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      }
+    }
+
+    else
+      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
+
+    break;
+
+  case format2A:
+
+    if ((frame_parms->frame_type == TDD) &&
+        (frame_parms->tdd_config>0)) {
+      if (frame_parms->nb_antenna_ports_eNB == 2) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap
+               );
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2A 4 antennas (TDD 1.5 MHz), rnti %x (%"PRIu64"): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi
+               );
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2A 4 antennas (TDD 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2A 4 antennas (TDD 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2A 4 antennas (TDD 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      }
+    } else if (frame_parms->frame_type == FDD) {
+      if (frame_parms->nb_antenna_ports_eNB == 2) {
+        switch(frame_parms->N_RB_DL) {
+        case 6:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 1.5 MHz), rnti %x (%x):  rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
+                dci->rnti,
+                ((uint32_t*)&dci->dci_pdu)[0],
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
+        switch(frame_parms->N_RB_DL) {
+
+        case 6:
+          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 1.5 MHz), rnti %x (%"PRIu64"): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 25:
+          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 50:
+          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        case 100:
+          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
+                dci->rnti,
+                ((uint64_t*)&dci->dci_pdu)[0],
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
+                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
+          break;
+
+        default:
+          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
+          DevParam (frame_parms->N_RB_DL, 0, 0);
+          break;
+        }
+      }
+    }
+
+    else
+      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
+
+    break;
+
+  case format1E_2A_M10PRB:
+
+    LOG_D(PHY,"DCI format1E_2A_M10PRB, rnti %x (%8x): harq_pid %d, rah %d, rb_alloc %x, mcs %d, rv %d, tpmi %d, ndi %d, dl_power_offset %d\n",
+          dci->rnti,
+          ((uint32_t *)&dci->dci_pdu)[0],
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->harq_pid,
+          //((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tb_swap,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rah,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rballoc,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->mcs,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rv,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tpmi,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->ndi,
+          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->dl_power_off
+         );
+
+    break;
+
+  default:
+    LOG_E(PHY,"dci_tools.c: dump_dci, unknown format %d\n",dci->format);
+    return(-1);
+  }
+
+  return(0);
+}

openair1/PHY/LTE_TRANSPORT/pbch.c

@@ -417,3 +417,6 @@ int generate_pbch(LTE_eNB_PBCH *eNB_pbch,
 
   return(0);
 }
+
+
+

openair1/PHY/LTE_TRANSPORT/pcfich_common.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/LTE_TRANSPORT/pcfich.c
+* \brief Top-level routines for generating and decoding  the PCFICH/CFI physical/transport channel V8.6 2009-03
+* \author R. Knopp
+* \date 2011
+* \version 0.1
+* \company Eurecom
+* \email: knopp@eurecom.fr
+* \note
+* \warning
+*/
+#include "PHY/impl_defs_top.h"
+#include "PHY/defs_eNB.h"
+
+void generate_pcfich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms)
+{
+
+  uint16_t kbar = 6 * (frame_parms->Nid_cell %(2*frame_parms->N_RB_DL));
+  uint16_t first_reg;
+  uint16_t *pcfich_reg = frame_parms->pcfich_reg;
+
+  pcfich_reg[0] = kbar/6;
+  first_reg = pcfich_reg[0];
+
+  frame_parms->pcfich_first_reg_idx=0;
+
+  pcfich_reg[1] = ((kbar + (frame_parms->N_RB_DL>>1)*6)%(frame_parms->N_RB_DL*12))/6;
+
+  if (pcfich_reg[1] < pcfich_reg[0]) {
+    frame_parms->pcfich_first_reg_idx = 1;
+    first_reg = pcfich_reg[1];
+  }
+
+  pcfich_reg[2] = ((kbar + (frame_parms->N_RB_DL)*6)%(frame_parms->N_RB_DL*12))/6;
+
+  if (pcfich_reg[2] < first_reg) {
+    frame_parms->pcfich_first_reg_idx = 2;
+    first_reg = pcfich_reg[2];
+  }
+
+  pcfich_reg[3] = ((kbar + ((3*frame_parms->N_RB_DL)>>1)*6)%(frame_parms->N_RB_DL*12))/6;
+
+  if (pcfich_reg[3] < first_reg) {
+    frame_parms->pcfich_first_reg_idx = 3;
+    first_reg = pcfich_reg[3];
+  }
+
+
+  //#ifdef DEBUG_PCFICH
+  printf("pcfich_reg : %d,%d,%d,%d\n",pcfich_reg[0],pcfich_reg[1],pcfich_reg[2],pcfich_reg[3]);
+  //#endif
+}

openair1/PHY/LTE_TRANSPORT/pmch_common.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#include "PHY/defs_eNB.h"
+#include "PHY/phy_extern.h"
+
+int is_pmch_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms)
+{
+
+  uint32_t period;
+  uint8_t i;
+
+  //  LOG_D(PHY,"is_pmch_subframe: frame %d, subframe %d, num_MBSFN_config %d\n",
+  //  frame,subframe,frame_parms->num_MBSFN_config);
+
+  for (i=0; i<frame_parms->num_MBSFN_config; i++) {  // we have at least one MBSFN configuration
+    period = 1<<frame_parms->MBSFN_config[i].radioframeAllocationPeriod;
+
+    if ((frame % period) == frame_parms->MBSFN_config[i].radioframeAllocationOffset) {
+      if (frame_parms->MBSFN_config[i].fourFrames_flag == 0) {
+        if (frame_parms->frame_type == FDD) {
+          switch (subframe) {
+
+          case 1:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF1) > 0)
+              return(1);
+
+            break;
+
+          case 2:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF2) > 0)
+              return(1);
+
+            break;
+
+          case 3:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF3) > 0)
+              return(1);
+
+            break;
+
+          case 6:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF6) > 0)
+              return(1);
+
+            break;
+
+          case 7:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF7) > 0)
+              return(1);
+
+            break;
+
+          case 8:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_FDD_SF8) > 0)
+              return(1);
+
+            break;
+          }
+        } else  {
+          switch (subframe) {
+          case 3:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_TDD_SF3) > 0)
+              return(1);
+
+            break;
+
+          case 4:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_TDD_SF4) > 0)
+              return(1);
+
+            break;
+
+          case 7:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_TDD_SF7) > 0)
+              return(1);
+
+            break;
+
+          case 8:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_TDD_SF8) > 0)
+              return(1);
+
+            break;
+
+          case 9:
+            if ((frame_parms->MBSFN_config[i].mbsfn_SubframeConfig & MBSFN_TDD_SF9) > 0)
+              return(1);
+
+            break;
+          }
+        }
+
+      } else { // handle 4 frames case
+
+      }
+    }
+  }
+
+  return(0);
+}

openair1/PHY/LTE_TRANSPORT/prach_extern.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/LTE_TRANSPORT/prach_common.c
+ * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03
+ * \author R. Knopp
+ * \date 2011
+ * \version 0.1
+ * \company Eurecom
+ * \email: knopp@eurecom.fr
+ * \note
+ * \warning
+ */
+#include "PHY/sse_intrin.h"
+#include "PHY/defs_eNB.h"
+#include "PHY/phy_extern.h"
+
+//#define PRACH_DEBUG 1
+//#define PRACH_WRITE_OUTPUT_DEBUG 1
+
+extern uint16_t NCS_unrestricted[16];
+extern uint16_t NCS_restricted[15];
+extern uint16_t NCS_4[7];
+
+extern int16_t ru[2*839]; // quantized roots of unity
+extern uint32_t ZC_inv[839]; // multiplicative inverse for roots u
+extern uint16_t du[838];
+
+
+
+// This is table 5.7.1-4 from 36.211
+extern PRACH_TDD_PREAMBLE_MAP tdd_preamble_map[64][7];
+
+
+
+
+extern uint16_t prach_root_sequence_map0_3[838];
+ 
+
+extern uint16_t prach_root_sequence_map4[138];
+
+void dump_prach_config(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+
+// This function computes the du
+void fill_du(uint8_t prach_fmt);
+
+
+uint8_t get_num_prach_tdd(module_id_t Mod_id);
+
+
+uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index);
+
+
+uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type);
+
+
+uint8_t get_prach_prb_offset(LTE_DL_FRAME_PARMS *frame_parms, 
+			     uint8_t prach_ConfigIndex, 
+			     uint8_t n_ra_prboffset,
+			     uint8_t tdd_mapindex, uint16_t Nf); 
+
+
+int is_prach_subframe0(LTE_DL_FRAME_PARMS *frame_parms,uint8_t prach_ConfigIndex,uint32_t frame, uint8_t subframe);
+
+int is_prach_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe);
+
+
+void compute_prach_seq(uint16_t rootSequenceIndex,
+		       uint8_t prach_ConfigIndex,
+		       uint8_t zeroCorrelationZoneConfig,
+		       uint8_t highSpeedFlag,
+		       lte_frame_type_t frame_type,
+		       uint32_t X_u[64][839]);
+

openair1/PHY/LTE_TRANSPORT/pucch_extern.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/LTE_TRANSPORT/pucch.c
+* \brief Top-level routines for generating and decoding the PUCCH physical channel V8.6 2009-03
+* \author R. Knopp
+* \date 2011
+* \version 0.1
+* \company Eurecom
+* \email: knopp@eurecom.fr
+* \note
+* \warning
+*/
+
+#include <stdint.h>
+
+/* PUCCH format3 >> */
+#define D_I             0
+#define D_Q             1
+#define D_IQDATA        2
+#define D_NSLT1SF       2
+#define D_NSYM1SLT      7
+#define D_NSYM1SF       2*7
+#define D_NSC1RB        12
+#define D_NRB1PUCCH     2
+#define D_NPUCCH_SF5    5
+#define D_NPUCCH_SF4    4
+
+extern int16_t W4[3][4];
+
+extern int16_t W3_re[3][6];
+
+
+extern int16_t W3_im[3][6];
+
+extern int16_t alpha_re[12];
+extern int16_t alpha_im[12];
+
+extern char *pucch_format_string[];
+
+extern uint8_t chcod_tbl[128][48];
+
+extern int16_t W5_fmt3_re[5][5];
+
+extern int16_t W5_fmt3_im[5][5];
+
+extern int16_t W4_fmt3[4][4];
+
+extern int16_t W2[2];
+
+extern int16_t RotTBL_re[4];
+extern int16_t RotTBL_im[4];
+
+//np4_tbl, np5_tbl
+extern uint8_t Np5_TBL[5];
+extern uint8_t Np4_TBL[4];
+
+// alpha_TBL
+extern int16_t alphaTBL_re[12];
+extern int16_t alphaTBL_im[12];

openair1/PHY/LTE_TRANSPORT/transport_common_proto.h

+/** \brief Compute Q (modulation order) based on I_MCS PDSCH.  Implements table 7.1.7.1-1 from 36.213.
+    @param I_MCS */
+uint8_t get_Qm(uint8_t I_MCS);
+
+/** \brief Compute Q (modulation order) based on I_MCS for PUSCH.  Implements table 8.6.1-1 from 36.213.
+    @param I_MCS */
+uint8_t get_Qm_ul(uint8_t I_MCS);
+
+/** \brief Compute I_TBS (transport-block size) based on I_MCS for PDSCH.  Implements table 7.1.7.1-1 from 36.213.
+    @param I_MCS */
+uint8_t get_I_TBS(uint8_t I_MCS);
+
+/** \brief Compute I_TBS (transport-block size) based on I_MCS for PUSCH.  Implements table 8.6.1-1 from 36.213.
+    @param I_MCS */
+unsigned char get_I_TBS_UL(unsigned char I_MCS);
+
+/** \brief Compute Q (modulation order) based on downlink I_MCS. Implements table 7.1.7.1-1 from 36.213.
+    @param I_MCS
+    @param nb_rb
+    @return Transport block size */
+uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb);
+
+/** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213.
+    @param I_MCS
+    @param nb_rb
+    @return Transport block size */
+uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb);
+
+/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type
+   @param N_RB_DL number of PRB on DL
+   @param indicator for even/odd slot
+   @param vrb vrb index
+   @param Ngap Gap indicator
+*/
+uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap);
+
+/* \brief Return prb for a given vrb index
+   @param vrb_type VRB type (0=localized,1=distributed)
+   @param rb_alloc_dci rballoc field from DCI
+*/
+uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci);
+
+
+/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type
+   @returns Transmission mode (1-7)
+*/
+uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti);
+
+
+/* \brief
+   @param ra_header Header of resource allocation (0,1) (See sections 7.1.6.1/7.1.6.2 of 36.213 Rel8.6)
+   @param rb_alloc Bitmap allocation from DCI (format 1,2)
+   @returns number of physical resource blocks
+*/
+uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL);
+
+int get_G(LTE_DL_FRAME_PARMS *frame_parms,uint16_t nb_rb,uint32_t *rb_alloc,uint8_t mod_order,uint8_t Nl,uint8_t num_pdcch_symbols,int frame,uint8_t subframe, uint8_t beamforming_mode);
+
+int adjust_G(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe);
+int adjust_G2(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe,uint8_t symbol);
+
+
+#ifndef modOrder
+#define modOrder(I_MCS,I_TBS) ((I_MCS-I_TBS)*2+2) // Find modulation order from I_TBS and I_MCS
+#endif
+
+/** \fn uint8_t I_TBS2I_MCS(uint8_t I_TBS);
+    \brief This function maps I_tbs to I_mcs according to Table 7.1.7.1-1 in 3GPP TS 36.213 V8.6.0. Where there is two supported modulation orders for the same I_TBS then either high or low modulation is chosen by changing the equality of the two first comparisons in the if-else statement.
+    \param I_TBS Index of Transport Block Size
+    \return I_MCS given I_TBS
+*/
+uint8_t I_TBS2I_MCS(uint8_t I_TBS);
+
+/** \fn uint8_t SE2I_TBS(float SE,
+    uint8_t N_PRB,
+    uint8_t symbPerRB);
+    \brief This function maps a requested throughput in number of bits to I_tbs. The throughput is calculated as a function of modulation order, RB allocation and number of symbols per RB. The mapping orginates in the "Transport block size table" (Table 7.1.7.2.1-1 in 3GPP TS 36.213 V8.6.0)
+    \param SE Spectral Efficiency (before casting to integer, multiply by 1024, remember to divide result by 1024!)
+    \param N_PRB Number of PhysicalResourceBlocks allocated \sa lte_frame_parms->N_RB_DL
+    \param symbPerRB Number of symbols per resource block allocated to this channel
+    \return I_TBS given an SE and an N_PRB
+*/
+uint8_t SE2I_TBS(float SE,
+                 uint8_t N_PRB,
+                 uint8_t symbPerRB);
+/** \brief This function generates the sounding reference symbol (SRS) for the uplink according to 36.211 v8.6.0. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence.
+    @param frame_parms LTE DL Frame Parameters
+    @param soundingrs_ul_config_dedicated Dynamic configuration from RRC during Connection Establishment
+    @param txdataF pointer to the frequency domain TX signal
+    @returns 0 on success*/
+
+int generate_srs(LTE_DL_FRAME_PARMS *frame_parms,
+		 SOUNDINGRS_UL_CONFIG_DEDICATED *soundingrs_ul_config_dedicated,
+		 int *txdataF,
+		 int16_t amp,
+		 uint32_t subframe);
+
+
+/*!
+  \brief This function generates the downlink reference signal for the PUSCH according to 36.211 v8.6.0. The DRS occuies the RS defined by rb_alloc and the symbols 2 and 8 for extended CP and 3 and 10 for normal CP.
+*/
+
+
+/*!
+  \brief This function initializes the Group Hopping, Sequence Hopping and nPRS sequences for PUCCH/PUSCH according to 36.211 v8.6.0. It should be called after configuration of UE (reception of SIB2/3) and initial configuration of eNB (or after reconfiguration of cell-specific parameters).
+  @param frame_parms Pointer to a LTE_DL_FRAME_PARMS structure (eNB or UE)*/
+void init_ul_hopping(LTE_DL_FRAME_PARMS *frame_parms);
+
+
+int32_t compareints (const void * a, const void * b);
+
+uint8_t subframe2harq_pid(LTE_DL_FRAME_PARMS *frame_parms,frame_t frame,uint8_t subframe);
+
+int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci);
+
+void generate_pcfich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms);
+
+void generate_phich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms);
+
+void generate_RIV_tables(void);
+
+/** \brief  This routine provides the relationship between a PHICH TXOp and its corresponding PUSCH subframe (Table 8.3.-1 from 36.213).
+    @param frame_parms Pointer to DL frame configuration parameters
+    @param subframe Subframe of received/transmitted PHICH
+    @returns subframe of PUSCH transmission
+*/
+uint8_t phich_subframe2_pusch_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+/** \brief  This routine provides the relationship between a PHICH TXOp and its corresponding PUSCH frame (Table 8.3.-1 from 36.213).
+    @param frame_parms Pointer to DL frame configuration parameters
+    @param frame Frame of received/transmitted PHICH
+    @param subframe Subframe of received/transmitted PHICH
+    @returns frame of PUSCH transmission
+*/
+int phich_frame2_pusch_frame(LTE_DL_FRAME_PARMS *frame_parms, int frame, int subframe);
+
+uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs);
+
+int get_nCCE_offset_l1(int *CCE_table,
+                       const unsigned char L,
+                       const int nCCE,
+                       const int common_dci,
+                       const unsigned short rnti,
+                       const unsigned char subframe);
+
+uint16_t get_nCCE(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uint8_t mi);
+
+uint16_t get_nquad(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uint8_t mi);
+
+uint8_t get_mi(LTE_DL_FRAME_PARMS *frame,uint8_t subframe);
+
+uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe);
+
+uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+void init_ncs_cell(LTE_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7]);
+
+/*!
+  \brief Check for PRACH TXop in subframe
+  @param frame_parms Pointer to LTE_DL_FRAME_PARMS
+  @param frame frame index to check
+  @param subframe subframe index to check
+  @returns 0 on success
+*/
+int is_prach_subframe(LTE_DL_FRAME_PARMS *frame_parms,frame_t frame, uint8_t subframe);
+
+/*!
+  \brief Helper for MAC, returns number of available PRACH in TDD for a particular configuration index
+  @param frame_parms Pointer to LTE_DL_FRAME_PARMS structure
+  @returns 0-5 depending on number of available prach
+*/
+uint8_t get_num_prach_tdd(module_id_t Mod_id);
+
+/*!
+  \brief Return the PRACH format as a function of the Configuration Index and Frame type.
+  @param prach_ConfigIndex PRACH Configuration Index
+  @param frame_type 0-FDD, 1-TDD
+  @returns 0-1 accordingly
+*/
+uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type);
+
+/*!
+  \brief Helper for MAC, returns frequency index of PRACH resource in TDD for a particular configuration index
+  @param frame_parms Pointer to LTE_DL_FRAME_PARMS structure
+  @returns 0-5 depending on number of available prach
+*/
+uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index);
+
+/*!
+  \brief Comp ute DFT of PRACH ZC sequences.  Used for generation of prach in UE and reception of PRACH in eNB.
+  @param rootSequenceIndex PRACH root sequence
+  #param prach_ConfigIndex PRACH Configuration Index
+  @param zeroCorrelationZoneConfig PRACH ncs_config
+  @param highSpeedFlat PRACH High-Speed Flag
+  @param frame_type TDD/FDD flag
+  @param Xu DFT output
+*/
+void compute_prach_seq(uint16_t rootSequenceIndex,
+		       uint8_t prach_ConfigIndex,
+		       uint8_t zeroCorrelationZoneConfig,
+		       uint8_t highSpeedFlag,
+		       lte_frame_type_t frame_type,
+		       uint32_t X_u[64][839]);
+
+
+void init_prach_tables(int N_ZC);
+
+/*!
+  \brief Return the status of MBSFN in this frame/subframe
+  @param frame Frame index
+  @param subframe Subframe index
+  @param frame_parms Pointer to frame parameters
+  @returns 1 if subframe is for MBSFN
+*/
+int is_pmch_subframe(frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms);
+
+
+// DL power control functions
+double get_pa_dB(uint8_t pa);
+
+uint8_t get_prach_prb_offset(LTE_DL_FRAME_PARMS *frame_parms, 
+			     uint8_t prach_ConfigIndex, 
+			     uint8_t n_ra_prboffset,
+			     uint8_t tdd_mapindex, uint16_t Nf);
+
+uint8_t ul_subframe2pdcch_alloc_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n);
+
+uint32_t conv_1C_RIV(int32_t rballoc,uint32_t N_RB_DL);
+
+void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t *rb_alloc2);

openair1/PHY/LTE_UE_TRANSPORT/dci_ue.c

@@ -52,7 +52,6 @@
 //#undef ALL_AGGREGATION
 
 
-
 uint16_t extract_crc(uint8_t *dci,uint8_t dci_len)
 {
 

openair1/PHY/MODULATION/modulation_common.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#ifndef __MODULATION_DEFS__H__
+#define __MODULATION_DEFS__H__
+#include "PHY/defs_common.h"
+/** @addtogroup _PHY_MODULATION_
+ * @{
+*/
+
+/**
+\fn void PHY_ofdm_mod(int *input,int *output,int fftsize,unsigned char nb_symbols,unsigned short nb_prefix_samples,Extension_t etype)
+This function performs OFDM modulation with cyclic extension or zero-padding.
+
+@param input The sequence input samples in the frequency-domain.  This is a concatenation of the input symbols in SIMD redundant format
+@param output The time-domain output signal
+@param fftsize size of OFDM symbol size (\f$N_d\f$)
+@param nb_symbols The number of OFDM symbols in the block
+@param nb_prefix_samples The number of prefix/suffix/zero samples
+@param etype Type of extension (CYCLIC_PREFIX,CYCLIC_SUFFIX,ZEROS)
+
+*/
+void PHY_ofdm_mod(int *input,
+                  int *output,
+                  int fftsize,
+                  unsigned char nb_symbols,
+                  unsigned short nb_prefix_samples,
+                  Extension_t etype
+                 );
+
+
+void normal_prefix_mod(int32_t *txdataF,int32_t *txdata,uint8_t nsymb,LTE_DL_FRAME_PARMS *frame_parms);
+
+void do_OFDM_mod(int32_t **txdataF, int32_t **txdata, uint32_t frame,uint16_t next_slot, LTE_DL_FRAME_PARMS *frame_parms);
+
+
+/** @}*/
+#endif

openair1/PHY/MODULATION/ul_7_5_kHz_ue.c

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#include "PHY/defs_UE.h"
+#include "PHY/phy_extern_ue.h"
+#include "modulation_extern.h"
+#include <math.h>
+#include "PHY/sse_intrin.h"
+
+extern short conjugate75[8];
+extern short conjugate75_2[8];
+extern short negate[8];
+
+void apply_7_5_kHz(PHY_VARS_UE *ue,int32_t*txdata,uint8_t slot)
+{
+
+
+  uint16_t len;
+  uint32_t *kHz7_5ptr;
+#if defined(__x86_64__) || defined(__i386__)
+  __m128i *txptr128,*kHz7_5ptr128,mmtmp_re,mmtmp_im,mmtmp_re2,mmtmp_im2;
+#elif defined(__arm__)
+  int16x8_t *txptr128,*kHz7_5ptr128;
+  int32x4_t mmtmp_re,mmtmp_im;
+  int32x4_t mmtmp0,mmtmp1;
+#endif
+  uint32_t slot_offset;
+  //   uint8_t aa;
+  uint32_t i;
+  LTE_DL_FRAME_PARMS *frame_parms=&ue->frame_parms;
+
+  switch (frame_parms->N_RB_UL) {
+
+  case 6:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s6n_kHz_7_5 : (uint32_t*)s6e_kHz_7_5;
+    break;
+
+  case 15:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s15n_kHz_7_5 : (uint32_t*)s15e_kHz_7_5;
+    break;
+
+  case 25:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s25n_kHz_7_5 : (uint32_t*)s25e_kHz_7_5;
+    break;
+
+  case 50:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s50n_kHz_7_5 : (uint32_t*)s50e_kHz_7_5;
+    break;
+
+  case 75:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s75n_kHz_7_5 : (uint32_t*)s75e_kHz_7_5;
+    break;
+
+  case 100:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s100n_kHz_7_5 : (uint32_t*)s100e_kHz_7_5;
+    break;
+
+  default:
+    kHz7_5ptr = (frame_parms->Ncp==0) ? (uint32_t*)s25n_kHz_7_5 : (uint32_t*)s25e_kHz_7_5;
+    break;
+  }
+
+  slot_offset = (uint32_t)slot * frame_parms->samples_per_tti/2;
+  len = frame_parms->samples_per_tti/2;
+
+#if defined(__x86_64__) || defined(__i386__)
+  txptr128 = (__m128i *)&txdata[slot_offset];
+  kHz7_5ptr128 = (__m128i *)kHz7_5ptr;
+#elif defined(__arm__)
+  txptr128 = (int16x8_t*)&txdata[slot_offset];
+  kHz7_5ptr128 = (int16x8_t*)kHz7_5ptr;
+#endif
+  // apply 7.5 kHz
+
+  for (i=0; i<(len>>2); i++) {
+#if defined(__x86_64__) || defined(__i386__)
+    mmtmp_re = _mm_madd_epi16(*txptr128,*kHz7_5ptr128);
+    // Real part of complex multiplication (note: 7_5kHz signal is conjugated for this to work)
+    mmtmp_im = _mm_shufflelo_epi16(*kHz7_5ptr128,_MM_SHUFFLE(2,3,0,1));
+    mmtmp_im = _mm_shufflehi_epi16(mmtmp_im,_MM_SHUFFLE(2,3,0,1));
+    mmtmp_im = _mm_sign_epi16(mmtmp_im,*(__m128i*)&conjugate75[0]);
+    mmtmp_im = _mm_madd_epi16(mmtmp_im,txptr128[0]);
+    mmtmp_re = _mm_srai_epi32(mmtmp_re,15);
+    mmtmp_im = _mm_srai_epi32(mmtmp_im,15);
+    mmtmp_re2 = _mm_unpacklo_epi32(mmtmp_re,mmtmp_im);
+    mmtmp_im2 = _mm_unpackhi_epi32(mmtmp_re,mmtmp_im);
+
+    txptr128[0] = _mm_packs_epi32(mmtmp_re2,mmtmp_im2);
+    txptr128++;
+    kHz7_5ptr128++;  
+#elif defined(__arm__)
+
+    mmtmp0 = vmull_s16(((int16x4_t*)txptr128)[0],((int16x4_t*)kHz7_5ptr128)[0]);
+        //mmtmp0 = [Re(ch[0])Re(rx[0]) Im(ch[0])Im(ch[0]) Re(ch[1])Re(rx[1]) Im(ch[1])Im(ch[1])] 
+    mmtmp1 = vmull_s16(((int16x4_t*)txptr128)[1],((int16x4_t*)kHz7_5ptr128)[1]);
+        //mmtmp1 = [Re(ch[2])Re(rx[2]) Im(ch[2])Im(ch[2]) Re(ch[3])Re(rx[3]) Im(ch[3])Im(ch[3])] 
+    mmtmp_re = vcombine_s32(vpadd_s32(vget_low_s32(mmtmp0),vget_high_s32(mmtmp0)),
+                            vpadd_s32(vget_low_s32(mmtmp1),vget_high_s32(mmtmp1)));
+        //mmtmp_re = [Re(ch[0])Re(rx[0])+Im(ch[0])Im(ch[0]) Re(ch[1])Re(rx[1])+Im(ch[1])Im(ch[1]) Re(ch[2])Re(rx[2])+Im(ch[2])Im(ch[2]) Re(ch[3])Re(rx[3])+Im(ch[3])Im(ch[3])] 
+
+    mmtmp0 = vmull_s16(vrev32_s16(vmul_s16(((int16x4_t*)txptr128)[0],*(int16x4_t*)conjugate75_2)),((int16x4_t*)kHz7_5ptr128)[0]);
+        //mmtmp0 = [-Im(ch[0])Re(rx[0]) Re(ch[0])Im(rx[0]) -Im(ch[1])Re(rx[1]) Re(ch[1])Im(rx[1])]
+    mmtmp1 = vmull_s16(vrev32_s16(vmul_s16(((int16x4_t*)txptr128)[1],*(int16x4_t*)conjugate75_2)), ((int16x4_t*)kHz7_5ptr128)[1]);
+        //mmtmp0 = [-Im(ch[2])Re(rx[2]) Re(ch[2])Im(rx[2]) -Im(ch[3])Re(rx[3]) Re(ch[3])Im(rx[3])]
+    mmtmp_im = vcombine_s32(vpadd_s32(vget_low_s32(mmtmp0),vget_high_s32(mmtmp0)),
+                            vpadd_s32(vget_low_s32(mmtmp1),vget_high_s32(mmtmp1)));
+        //mmtmp_im = [-Im(ch[0])Re(rx[0])+Re(ch[0])Im(rx[0]) -Im(ch[1])Re(rx[1])+Re(ch[1])Im(rx[1]) -Im(ch[2])Re(rx[2])+Re(ch[2])Im(rx[2]) -Im(ch[3])Re(rx[3])+Re(ch[3])Im(rx[3])]
+
+    txptr128[0] = vcombine_s16(vmovn_s32(mmtmp_re),vmovn_s32(mmtmp_im));
+    txptr128++;
+    kHz7_5ptr128++;
+#endif
+  }
+
+  //}
+}
+
+

openair1/PHY/defs_UE.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/defs.h
+ \brief Top-level defines and structure definitions
+ \author R. Knopp, F. Kaltenberger
+ \date 2011
+ \version 0.1
+ \company Eurecom
+ \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr
+ \note
+ \warning
+*/
+#ifndef __PHY_DEFS_UE_H__
+#define __PHY_DEFS_UE_H__
+
+
+#define _GNU_SOURCE
+#include <sched.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <linux/sched.h>
+#include <signal.h>
+#include <execinfo.h>
+#include <getopt.h>
+#include <sys/sysinfo.h>
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <malloc.h>
+#include <string.h>
+#include <math.h>
+#include "common_lib.h"
+#include "msc.h"
+
+#include "defs_common.h"
+
+
+#include "PHY/TOOLS/time_meas.h"
+#include "PHY/CODING/coding_defs.h"
+#include "PHY/TOOLS/tools_defs.h"
+#include "platform_types.h"
+#include "PHY/LTE_UE_TRANSPORT/transport_ue.h"
+#include "PHY/LTE_TRANSPORT/transport_eNB.h" // for SIC
+#include <pthread.h>
+
+
+
+/// Context data structure for RX/TX portion of subframe processing
+typedef struct {
+  /// index of the current UE RX/TX proc
+  int                  proc_id;
+  /// Component Carrier index
+  uint8_t              CC_id;
+  /// timestamp transmitted to HW
+  openair0_timestamp timestamp_tx;
+  /// subframe to act upon for transmission
+  int subframe_tx;
+  /// subframe to act upon for reception
+  int subframe_rx;
+  /// frame to act upon for transmission
+  int frame_tx;
+  /// frame to act upon for reception
+  int frame_rx;
+  /// \brief Instance count for RXn-TXnp4 processing thread.
+  /// \internal This variable is protected by \ref mutex_rxtx.
+  int instance_cnt_rxtx;
+  /// pthread structure for RXn-TXnp4 processing thread
+  pthread_t pthread_rxtx;
+  /// pthread attributes for RXn-TXnp4 processing thread
+  pthread_attr_t attr_rxtx;
+  /// condition variable for tx processing thread
+  pthread_cond_t cond_rxtx;
+  /// mutex for RXn-TXnp4 processing thread
+  pthread_mutex_t mutex_rxtx;
+  /// scheduling parameters for RXn-TXnp4 thread
+  struct sched_param sched_param_rxtx;
+
+  /// internal This variable is protected by ref mutex_fep_slot1.
+  //int instance_cnt_slot0_dl_processing;
+  int instance_cnt_slot1_dl_processing;
+  /// pthread descriptor fep_slot1 thread
+  //pthread_t pthread_slot0_dl_processing;
+  pthread_t pthread_slot1_dl_processing;
+  /// pthread attributes for fep_slot1 processing thread
+ // pthread_attr_t attr_slot0_dl_processing;
+  pthread_attr_t attr_slot1_dl_processing;
+  /// condition variable for UE fep_slot1 thread;
+  //pthread_cond_t cond_slot0_dl_processing;
+  pthread_cond_t cond_slot1_dl_processing;
+  /// mutex for UE synch thread
+  //pthread_mutex_t mutex_slot0_dl_processing;
+  pthread_mutex_t mutex_slot1_dl_processing;
+  //
+  uint8_t chan_est_pilot0_slot1_available;
+  uint8_t chan_est_slot1_available;
+  uint8_t llr_slot1_available;
+  uint8_t dci_slot0_available;
+  uint8_t first_symbol_available;
+  //uint8_t channel_level;
+  /// scheduling parameters for fep_slot1 thread
+  struct sched_param sched_param_fep_slot1;
+
+  int sub_frame_start;
+  int sub_frame_step;
+  unsigned long long gotIQs;
+} UE_rxtx_proc_t;
+
+/// Context data structure for eNB subframe processing
+typedef struct {
+  /// Component Carrier index
+  uint8_t              CC_id;
+  /// Last RX timestamp
+  openair0_timestamp timestamp_rx;
+  /// pthread attributes for main UE thread
+  pthread_attr_t attr_ue;
+  /// scheduling parameters for main UE thread
+  struct sched_param sched_param_ue;
+  /// pthread descriptor main UE thread
+  pthread_t pthread_ue;
+  /// \brief Instance count for synch thread.
+  /// \internal This variable is protected by \ref mutex_synch.
+  int instance_cnt_synch;
+  /// pthread attributes for synch processing thread
+  pthread_attr_t attr_synch;
+  /// scheduling parameters for synch thread
+  struct sched_param sched_param_synch;
+  /// pthread descriptor synch thread
+  pthread_t pthread_synch;
+  /// condition variable for UE synch thread;
+  pthread_cond_t cond_synch;
+  /// mutex for UE synch thread
+  pthread_mutex_t mutex_synch;
+  /// instance count for eNBs
+  int instance_cnt_eNBs;
+  /// set of scheduling variables RXn-TXnp4 threads
+  UE_rxtx_proc_t proc_rxtx[RX_NB_TH];
+} UE_proc_t;
+
+
+
+
+typedef struct {
+  //unsigned int   rx_power[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];     //! estimated received signal power (linear)
+  //unsigned short rx_power_dB[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];  //! estimated received signal power (dB)
+  //unsigned short rx_avg_power_dB[NUMBER_OF_CONNECTED_eNB_MAX];              //! estimated avg received signal power (dB)
+
+  // RRC measurements
+  uint32_t rssi;
+  int n_adj_cells;
+  unsigned int adj_cell_id[6];
+  uint32_t rsrq[7];
+  uint32_t rsrp[7];
+  float rsrp_filtered[7]; // after layer 3 filtering
+  float rsrq_filtered[7];
+  // common measurements
+  //! estimated noise power (linear)
+  unsigned int   n0_power[NB_ANTENNAS_RX];
+  //! estimated noise power (dB)
+  unsigned short n0_power_dB[NB_ANTENNAS_RX];
+  //! total estimated noise power (linear)
+  unsigned int   n0_power_tot;
+  //! total estimated noise power (dB)
+  unsigned short n0_power_tot_dB;
+  //! average estimated noise power (linear)
+  unsigned int   n0_power_avg;
+  //! average estimated noise power (dB)
+  unsigned short n0_power_avg_dB;
+  //! total estimated noise power (dBm)
+  short n0_power_tot_dBm;
+
+  // UE measurements
+  //! estimated received spatial signal power (linear)
+  int            rx_spatial_power[NUMBER_OF_CONNECTED_eNB_MAX][2][2];
+  //! estimated received spatial signal power (dB)
+  unsigned short rx_spatial_power_dB[NUMBER_OF_CONNECTED_eNB_MAX][2][2];
+
+  /// estimated received signal power (sum over all TX antennas)
+  //int            wideband_cqi[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+  int            rx_power[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+  /// estimated received signal power (sum over all TX antennas)
+  //int            wideband_cqi_dB[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+  unsigned short rx_power_dB[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+
+  /// estimated received signal power (sum over all TX/RX antennas)
+  int            rx_power_tot[NUMBER_OF_CONNECTED_eNB_MAX]; //NEW
+  /// estimated received signal power (sum over all TX/RX antennas)
+  unsigned short rx_power_tot_dB[NUMBER_OF_CONNECTED_eNB_MAX]; //NEW
+
+  //! estimated received signal power (sum of all TX/RX antennas, time average)
+  int            rx_power_avg[NUMBER_OF_CONNECTED_eNB_MAX];
+  //! estimated received signal power (sum of all TX/RX antennas, time average, in dB)
+  unsigned short rx_power_avg_dB[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// SINR (sum of all TX/RX antennas, in dB)
+  int            wideband_cqi_tot[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// SINR (sum of all TX/RX antennas, time average, in dB)
+  int            wideband_cqi_avg[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  //! estimated rssi (dBm)
+  short          rx_rssi_dBm[NUMBER_OF_CONNECTED_eNB_MAX];
+  //! estimated correlation (wideband linear) between spatial channels (computed in dlsch_demodulation)
+  int            rx_correlation[NUMBER_OF_CONNECTED_eNB_MAX][2];
+  //! estimated correlation (wideband dB) between spatial channels (computed in dlsch_demodulation)
+  int            rx_correlation_dB[NUMBER_OF_CONNECTED_eNB_MAX][2];
+
+  /// Wideband CQI (sum of all RX antennas, in dB, for precoded transmission modes (3,4,5,6), up to 4 spatial streams)
+  int            precoded_cqi_dB[NUMBER_OF_CONNECTED_eNB_MAX+1][4];
+  /// Subband CQI per RX antenna (= SINR)
+  int            subband_cqi[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX][NUMBER_OF_SUBBANDS_MAX];
+  /// Total Subband CQI  (= SINR)
+  int            subband_cqi_tot[NUMBER_OF_CONNECTED_eNB_MAX][NUMBER_OF_SUBBANDS_MAX];
+  /// Subband CQI in dB (= SINR dB)
+  int            subband_cqi_dB[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX][NUMBER_OF_SUBBANDS_MAX];
+  /// Total Subband CQI
+  int            subband_cqi_tot_dB[NUMBER_OF_CONNECTED_eNB_MAX][NUMBER_OF_SUBBANDS_MAX];
+  /// Wideband PMI for each RX antenna
+  int            wideband_pmi_re[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+  /// Wideband PMI for each RX antenna
+  int            wideband_pmi_im[NUMBER_OF_CONNECTED_eNB_MAX][NB_ANTENNAS_RX];
+  ///Subband PMI for each RX antenna
+  int            subband_pmi_re[NUMBER_OF_CONNECTED_eNB_MAX][NUMBER_OF_SUBBANDS_MAX][NB_ANTENNAS_RX];
+  ///Subband PMI for each RX antenna
+  int            subband_pmi_im[NUMBER_OF_CONNECTED_eNB_MAX][NUMBER_OF_SUBBANDS_MAX][NB_ANTENNAS_RX];
+  /// chosen RX antennas (1=Rx antenna 1, 2=Rx antenna 2, 3=both Rx antennas)
+  unsigned char           selected_rx_antennas[NUMBER_OF_CONNECTED_eNB_MAX][NUMBER_OF_SUBBANDS_MAX];
+  /// Wideband Rank indication
+  unsigned char  rank[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// Number of RX Antennas
+  unsigned char  nb_antennas_rx;
+  /// DLSCH error counter
+  // short          dlsch_errors;
+
+} PHY_MEASUREMENTS;
+
+typedef struct {
+
+  /// \brief Holds the received data in the frequency domain.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: symbol [0..28*ofdm_symbol_size[
+  int32_t **rxdataF;
+  
+  /// \brief Hold the channel estimates in frequency domain.
+  /// - first index: eNB id [0..6] (hard coded)
+  /// - second index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - third index: samples? [0..symbols_per_tti*(ofdm_symbol_size+LTE_CE_FILTER_LENGTH)[
+  int32_t **dl_ch_estimates[7];
+  
+  /// \brief Hold the channel estimates in time domain (used for tracking).
+  /// - first index: eNB id [0..6] (hard coded)
+  /// - second index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - third index: samples? [0..2*ofdm_symbol_size[
+  int32_t **dl_ch_estimates_time[7];
+}LTE_UE_COMMON_PER_THREAD;
+
+typedef struct {
+  /// \brief Holds the transmit data in time domain.
+  /// For IFFT_FPGA this points to the same memory as PHY_vars->tx_vars[a].TX_DMA_BUFFER.
+  /// - first index: tx antenna [0..nb_antennas_tx[
+  /// - second index: sample [0..FRAME_LENGTH_COMPLEX_SAMPLES[
+  int32_t **txdata;
+  /// \brief Holds the transmit data in the frequency domain.
+  /// For IFFT_FPGA this points to the same memory as PHY_vars->rx_vars[a].RX_DMA_BUFFER.
+  /// - first index: tx antenna [0..nb_antennas_tx[
+  /// - second index: sample [0..FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX[
+  int32_t **txdataF;
+
+  /// \brief Holds the received data in time domain.
+  /// Should point to the same memory as PHY_vars->rx_vars[a].RX_DMA_BUFFER.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: sample [0..FRAME_LENGTH_COMPLEX_SAMPLES+2048[
+  int32_t **rxdata;
+
+  LTE_UE_COMMON_PER_THREAD common_vars_rx_data_per_thread[RX_NB_TH_MAX];
+
+  /// holds output of the sync correlator
+  int32_t *sync_corr;
+  /// estimated frequency offset (in radians) for all subcarriers
+  int32_t freq_offset;
+  /// eNb_id user is synched to
+  int32_t eNb_id;
+} LTE_UE_COMMON;
+
+typedef struct {
+  /// \brief Received frequency-domain signal after extraction.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **rxdataF_ext;
+  /// \brief Received frequency-domain ue specific pilots.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..12*N_RB_DL[
+  int32_t **rxdataF_uespec_pilots;
+  /// \brief Received frequency-domain signal after extraction and channel compensation.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **rxdataF_comp0;
+  /// \brief Received frequency-domain signal after extraction and channel compensation for the second stream. For the SIC receiver we need to store the history of this for each harq process and round
+  /// - first index: ? [0..7] (hard coded) accessed via \c harq_pid
+  /// - second index: ? [0..7] (hard coded) accessed via \c round
+  /// - third index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - fourth index: ? [0..168*N_RB_DL[
+  int32_t **rxdataF_comp1[8][8];
+  /// \brief Downlink channel estimates extracted in PRBS.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_estimates_ext;
+  /// \brief Downlink cross-correlation of MIMO channel estimates (unquantized PMI) extracted in PRBS. For the SIC receiver we need to store the history of this for each harq process and round
+  /// - first index: ? [0..7] (hard coded) accessed via \c harq_pid
+  /// - second index: ? [0..7] (hard coded) accessed via \c round
+  /// - third index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - fourth index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_rho_ext[8][8];
+  /// \brief Downlink beamforming channel estimates in frequency domain.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: samples? [0..symbols_per_tti*(ofdm_symbol_size+LTE_CE_FILTER_LENGTH)[
+  int32_t **dl_bf_ch_estimates;
+  /// \brief Downlink beamforming channel estimates.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_bf_ch_estimates_ext;
+  /// \brief Downlink cross-correlation of MIMO channel estimates (unquantized PMI) extracted in PRBS.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_rho2_ext;
+  /// \brief Downlink PMIs extracted in PRBS and grouped in subbands.
+  /// - first index: ressource block [0..N_RB_DL[
+  uint8_t *pmi_ext;
+  /// \brief Magnitude of Downlink Channel first layer (16QAM level/First 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_mag0;
+  /// \brief Magnitude of Downlink Channel second layer (16QAM level/First 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_mag1[8][8];
+  /// \brief Magnitude of Downlink Channel, first layer (2nd 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_magb0;
+  /// \brief Magnitude of Downlink Channel second layer (2nd 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_magb1[8][8];
+  /// \brief Cross-correlation of two eNB signals.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: symbol [0..]
+  int32_t **rho;
+  /// never used... always send dl_ch_rho_ext instead...
+  int32_t **rho_i;
+  /// \brief Pointers to llr vectors (2 TBs).
+  /// - first index: ? [0..1] (hard coded)
+  /// - second index: ? [0..1179743] (hard coded)
+  int16_t *llr[2];
+  /// \f$\log_2(\max|H_i|^2)\f$
+  int16_t log2_maxh;
+    /// \f$\log_2(\max|H_i|^2)\f$ //this is for TM3-4 layer1 channel compensation
+  int16_t log2_maxh0;
+    /// \f$\log_2(\max|H_i|^2)\f$ //this is for TM3-4 layer2 channel commpensation
+  int16_t log2_maxh1;
+  /// \brief LLR shifts for subband scaling.
+  /// - first index: ? [0..168*N_RB_DL[
+  uint8_t *llr_shifts;
+  /// \brief Pointer to LLR shifts.
+  /// - first index: ? [0..168*N_RB_DL[
+  uint8_t *llr_shifts_p;
+  /// \brief Pointers to llr vectors (128-bit alignment).
+  /// - first index: ? [0..0] (hard coded)
+  /// - second index: ? [0..]
+  int16_t **llr128;
+  /// \brief Pointers to llr vectors (128-bit alignment).
+  /// - first index: ? [0..0] (hard coded)
+  /// - second index: ? [0..]
+  int16_t **llr128_2ndstream;
+  //uint32_t *rb_alloc;
+  //uint8_t Qm[2];
+  //MIMO_mode_t mimo_mode;
+  // llr offset per ofdm symbol
+  uint32_t llr_offset[14];
+  // llr length per ofdm symbol
+  uint32_t llr_length[14];
+} LTE_UE_PDSCH;
+
+typedef struct {
+  /// \brief Received frequency-domain signal after extraction.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  int32_t **rxdataF_ext;
+  /// \brief Received frequency-domain signal after extraction and channel compensation.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  double **rxdataF_comp;
+  /// \brief Downlink channel estimates extracted in PRBS.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  int32_t **dl_ch_estimates_ext;
+  ///  \brief Downlink cross-correlation of MIMO channel estimates (unquantized PMI) extracted in PRBS.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  double **dl_ch_rho_ext;
+  /// \brief Downlink PMIs extracted in PRBS and grouped in subbands.
+  /// - first index: ressource block [0..N_RB_DL[
+  uint8_t *pmi_ext;
+  /// \brief Magnitude of Downlink Channel (16QAM level/First 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  double **dl_ch_mag;
+  /// \brief Magnitude of Downlink Channel (2nd 64QAM level).
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..]
+  double **dl_ch_magb;
+  /// \brief Cross-correlation of two eNB signals.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: ? [0..]
+  double **rho;
+  /// never used... always send dl_ch_rho_ext instead...
+  double **rho_i;
+  /// \brief Pointers to llr vectors (2 TBs).
+  /// - first index: ? [0..1] (hard coded)
+  /// - second index: ? [0..1179743] (hard coded)
+  int16_t *llr[2];
+  /// \f$\log_2(\max|H_i|^2)\f$
+  uint8_t log2_maxh;
+  /// \brief Pointers to llr vectors (128-bit alignment).
+  /// - first index: ? [0..0] (hard coded)
+  /// - second index: ? [0..]
+  int16_t **llr128;
+  //uint32_t *rb_alloc;
+  //uint8_t Qm[2];
+  //MIMO_mode_t mimo_mode;
+} LTE_UE_PDSCH_FLP;
+
+typedef struct {
+  /// \brief Pointers to extracted PDCCH symbols in frequency-domain.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **rxdataF_ext;
+  /// \brief Pointers to extracted and compensated PDCCH symbols in frequency-domain.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **rxdataF_comp;
+  /// \brief Pointers to extracted channel estimates of PDCCH symbols.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_estimates_ext;
+  /// \brief Pointers to channel cross-correlation vectors for multi-eNB detection.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..168*N_RB_DL[
+  int32_t **dl_ch_rho_ext;
+  /// \brief Pointers to channel cross-correlation vectors for multi-eNB detection.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: ? [0..]
+  int32_t **rho;
+  /// \brief Pointer to llrs, 4-bit resolution.
+  /// - first index: ? [0..48*N_RB_DL[
+  uint16_t *llr;
+  /// \brief Pointer to llrs, 16-bit resolution.
+  /// - first index: ? [0..96*N_RB_DL[
+  uint16_t *llr16;
+  /// \brief \f$\overline{w}\f$ from 36-211.
+  /// - first index: ? [0..48*N_RB_DL[
+  uint16_t *wbar;
+  /// \brief PDCCH/DCI e-sequence (input to rate matching).
+  /// - first index: ? [0..96*N_RB_DL[
+  int8_t *e_rx;
+  /// number of PDCCH symbols in current subframe
+  uint8_t num_pdcch_symbols;
+  /// Allocated CRNTI for UE
+  uint16_t crnti;
+  /// 1: the allocated crnti is Temporary C-RNTI / 0: otherwise
+  uint8_t crnti_is_temporary;
+  /// Total number of PDU errors (diagnostic mode)
+  uint32_t dci_errors;
+  /// Total number of PDU received
+  uint32_t dci_received;
+  /// Total number of DCI False detection (diagnostic mode)
+  uint32_t dci_false;
+  /// Total number of DCI missed (diagnostic mode)
+  uint32_t dci_missed;
+  /// nCCE for PUCCH per subframe
+  uint8_t nCCE[10];
+  //Check for specific DCIFormat and AgregationLevel
+  uint8_t dciFormat;
+  uint8_t agregationLevel;
+} LTE_UE_PDCCH;
+
+
+typedef struct {
+  /// \brief Pointers to extracted PBCH symbols in frequency-domain.
+  /// - first index: rx antenna [0..nb_antennas_rx[
+  /// - second index: ? [0..287] (hard coded)
+  int32_t **rxdataF_ext;
+  /// \brief Pointers to extracted and compensated PBCH symbols in frequency-domain.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..287] (hard coded)
+  int32_t **rxdataF_comp;
+  /// \brief Pointers to downlink channel estimates in frequency-domain extracted in PRBS.
+  /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
+  /// - second index: ? [0..287] (hard coded)
+  int32_t **dl_ch_estimates_ext;
+  /// \brief Pointer to PBCH llrs.
+  /// - first index: ? [0..1919] (hard coded)
+  int8_t *llr;
+  /// \brief Pointer to PBCH decoded output.
+  /// - first index: ? [0..63] (hard coded)
+  uint8_t *decoded_output;
+  /// \brief Total number of PDU errors.
+  uint32_t pdu_errors;
+  /// \brief Total number of PDU errors 128 frames ago.
+  uint32_t pdu_errors_last;
+  /// \brief Total number of consecutive PDU errors.
+  uint32_t pdu_errors_conseq;
+  /// \brief FER (in percent) .
+  uint32_t pdu_fer;
+} LTE_UE_PBCH;
+
+typedef struct {
+  int16_t amp;
+  int16_t *prachF;
+  int16_t *prach;
+} LTE_UE_PRACH;
+
+
+
+typedef enum {
+  /// do not detect any DCIs in the current subframe
+  NO_DCI = 0x0,
+  /// detect only downlink DCIs in the current subframe
+  UL_DCI = 0x1,
+  /// detect only uplink DCIs in the current subframe
+  DL_DCI = 0x2,
+  /// detect both uplink and downlink DCIs in the current subframe
+  UL_DL_DCI = 0x3} dci_detect_mode_t;
+
+typedef struct UE_SCAN_INFO_s {
+  /// 10 best amplitudes (linear) for each pss signals
+  int32_t amp[3][10];
+  /// 10 frequency offsets (kHz) corresponding to best amplitudes, with respect do minimum DL frequency in the band
+  int32_t freq_offset_Hz[3][10];
+} UE_SCAN_INFO_t;
+
+/// Top-level PHY Data Structure for UE
+typedef struct {
+  /// \brief Module ID indicator for this instance
+  uint8_t Mod_id;
+  /// \brief Component carrier ID for this PHY instance
+  uint8_t CC_id;
+  /// \brief Mapping of CC_id antennas to cards
+  openair0_rf_map      rf_map;
+  //uint8_t local_flag;
+  /// \brief Indicator of current run mode of UE (normal_txrx, rx_calib_ue, no_L2_connect, debug_prach)
+  runmode_t mode;
+  /// \brief Indicator that UE should perform band scanning
+  int UE_scan;
+  /// \brief Indicator that UE should perform coarse scanning around carrier
+  int UE_scan_carrier;
+  /// \brief Indicator that UE is synchronized to an eNB
+  int is_synchronized;
+  /// Data structure for UE process scheduling
+  UE_proc_t proc;
+  /// Flag to indicate the UE shouldn't do timing correction at all
+  int no_timing_correction;
+  /// \brief Total gain of the TX chain (16-bit baseband I/Q to antenna)
+  uint32_t tx_total_gain_dB;
+  /// \brief Total gain of the RX chain (antenna to baseband I/Q) This is a function of rx_gain_mode (and the corresponding gain) and the rx_gain of the card.
+  uint32_t rx_total_gain_dB;
+  /// \brief Total gains with maximum RF gain stage (ExpressMIMO2/Lime)
+  uint32_t rx_gain_max[4];
+  /// \brief Total gains with medium RF gain stage (ExpressMIMO2/Lime)
+  uint32_t rx_gain_med[4];
+  /// \brief Total gains with bypassed RF gain stage (ExpressMIMO2/Lime)
+  uint32_t rx_gain_byp[4];
+  /// \brief Current transmit power
+  int16_t tx_power_dBm[10];
+  /// \brief Total number of REs in current transmission
+  int tx_total_RE[10];
+  /// \brief Maximum transmit power
+  int8_t tx_power_max_dBm;
+  /// \brief Number of eNB seen by UE
+  uint8_t n_connected_eNB;
+  /// \brief indicator that Handover procedure has been initiated
+  uint8_t ho_initiated;
+  /// \brief indicator that Handover procedure has been triggered
+  uint8_t ho_triggered;
+  /// \brief Measurement variables.
+  PHY_MEASUREMENTS measurements;
+  LTE_DL_FRAME_PARMS  frame_parms;
+  /// \brief Frame parame before ho used to recover if ho fails.
+  LTE_DL_FRAME_PARMS  frame_parms_before_ho;
+  LTE_UE_COMMON    common_vars;
+
+  // point to the current rxTx thread index
+  uint8_t current_thread_id[10];
+
+  LTE_UE_PDSCH     *pdsch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX+1]; // two RxTx Threads
+  LTE_UE_PDSCH_FLP *pdsch_vars_flp[NUMBER_OF_CONNECTED_eNB_MAX+1];
+  LTE_UE_PDSCH     *pdsch_vars_SI[NUMBER_OF_CONNECTED_eNB_MAX+1];
+  LTE_UE_PDSCH     *pdsch_vars_ra[NUMBER_OF_CONNECTED_eNB_MAX+1];
+  LTE_UE_PDSCH     *pdsch_vars_p[NUMBER_OF_CONNECTED_eNB_MAX+1];
+  LTE_UE_PDSCH     *pdsch_vars_MCH[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_PBCH      *pbch_vars[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_PDCCH     *pdcch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_PRACH     *prach_vars[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_DLSCH_t   *dlsch[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX][2]; // two RxTx Threads
+  LTE_UE_ULSCH_t   *ulsch[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_DLSCH_t   *dlsch_SI[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_DLSCH_t   *dlsch_ra[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_DLSCH_t   *dlsch_p[NUMBER_OF_CONNECTED_eNB_MAX];
+  LTE_UE_DLSCH_t   *dlsch_MCH[NUMBER_OF_CONNECTED_eNB_MAX];
+  // This is for SIC in the UE, to store the reencoded data
+  LTE_eNB_DLSCH_t  *dlsch_eNB[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  //Paging parameters
+  uint32_t              IMSImod1024;
+  uint32_t              PF;
+  uint32_t              PO;
+
+  // For abstraction-purposes only
+  uint8_t               sr[10];
+  uint8_t               pucch_sel[10];
+  uint8_t               pucch_payload[22];
+
+  UE_MODE_t        UE_mode[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// cell-specific reference symbols
+  uint32_t lte_gold_table[7][20][2][14];
+
+  /// UE-specific reference symbols (p=5), TM 7
+  uint32_t lte_gold_uespec_port5_table[20][38];
+
+  /// ue-specific reference symbols
+  uint32_t lte_gold_uespec_table[2][20][2][21];
+
+  /// mbsfn reference symbols
+  uint32_t lte_gold_mbsfn_table[10][3][42];
+
+  uint32_t X_u[64][839];
+
+  uint32_t high_speed_flag;
+  uint32_t perfect_ce;
+  int16_t ch_est_alpha;
+  int generate_ul_signal[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  UE_SCAN_INFO_t scan_info[NB_BANDS_MAX];
+
+  char ulsch_no_allocation_counter[NUMBER_OF_CONNECTED_eNB_MAX];
+
+
+
+  unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_eNB_MAX];
+  uint32_t  ulsch_Msg3_frame[NUMBER_OF_CONNECTED_eNB_MAX];
+  unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_eNB_MAX];
+  PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_eNB_MAX];
+  int turbo_iterations, turbo_cntl_iterations;
+  /// \brief ?.
+  /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded)
+  uint32_t total_TBS[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// \brief ?.
+  /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded)
+  uint32_t total_TBS_last[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// \brief ?.
+  /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded)
+  uint32_t bitrate[NUMBER_OF_CONNECTED_eNB_MAX];
+  /// \brief ?.
+  /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded)
+  uint32_t total_received_bits[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_errors[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_errors_last[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_received[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_received_last[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_fer[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_SI_received[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_SI_errors[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_ra_received[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_ra_errors[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_p_received[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_p_errors[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mch_received_sf[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mch_received[NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mcch_received[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mtch_received[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mcch_errors[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mtch_errors[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mcch_trials[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int dlsch_mtch_trials[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
+  int current_dlsch_cqi[NUMBER_OF_CONNECTED_eNB_MAX];
+  unsigned char first_run_timing_advance[NUMBER_OF_CONNECTED_eNB_MAX];
+  uint8_t               generate_prach;
+  uint8_t               prach_cnt;
+  uint8_t               prach_PreambleIndex;
+  //  uint8_t               prach_timer;
+  uint8_t               decode_SIB;
+  uint8_t               decode_MIB;
+  int              rx_offset; /// Timing offset
+  int              rx_offset_diff; /// Timing adjustment for ofdm symbol0 on HW USRP
+  int              time_sync_cell;
+  int              timing_advance; ///timing advance signalled from eNB
+  int              hw_timing_advance;
+  int              N_TA_offset; ///timing offset used in TDD
+  /// Flag to tell if UE is secondary user (cognitive mode)
+  unsigned char    is_secondary_ue;
+  /// Flag to tell if secondary eNB has channel estimates to create NULL-beams from.
+  unsigned char    has_valid_precoder;
+  /// hold the precoder for NULL beam to the primary eNB
+  int              **ul_precoder_S_UE;
+  /// holds the maximum channel/precoder coefficient
+  char             log2_maxp;
+
+  /// if ==0 enables phy only test mode
+  int mac_enabled;
+
+  /// Flag to initialize averaging of PHY measurements
+  int init_averaging;
+
+  /// \brief sinr for all subcarriers of the current link (used only for abstraction).
+  /// - first index: ? [0..12*N_RB_DL[
+  double *sinr_dB;
+
+  /// \brief sinr for all subcarriers of first symbol for the CQI Calculation.
+  /// - first index: ? [0..12*N_RB_DL[
+  double *sinr_CQI_dB;
+
+  /// sinr_effective used for CQI calulcation
+  double sinr_eff;
+
+  /// N0 (used for abstraction)
+  double N0;
+
+  /// PDSCH Varaibles
+  PDSCH_CONFIG_DEDICATED pdsch_config_dedicated[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// PUSCH Varaibles
+  PUSCH_CONFIG_DEDICATED pusch_config_dedicated[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// PUSCH contention-based access vars
+  PUSCH_CA_CONFIG_DEDICATED  pusch_ca_config_dedicated[NUMBER_OF_eNB_MAX]; // lola
+
+  /// PUCCH variables
+
+  PUCCH_CONFIG_DEDICATED pucch_config_dedicated[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  uint8_t ncs_cell[20][7];
+
+  /// UL-POWER-Control
+  UL_POWER_CONTROL_DEDICATED ul_power_control_dedicated[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// TPC
+  TPC_PDCCH_CONFIG tpc_pdcch_config_pucch[NUMBER_OF_CONNECTED_eNB_MAX];
+  TPC_PDCCH_CONFIG tpc_pdcch_config_pusch[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// CQI reporting
+  CQI_REPORT_CONFIG cqi_report_config[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// SRS Variables
+  SOUNDINGRS_UL_CONFIG_DEDICATED soundingrs_ul_config_dedicated[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// Scheduling Request Config
+  SCHEDULING_REQUEST_CONFIG scheduling_request_config[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  /// Transmission mode per eNB
+  uint8_t transmission_mode[NUMBER_OF_CONNECTED_eNB_MAX];
+
+  time_stats_t phy_proc[RX_NB_TH];
+  time_stats_t phy_proc_tx;
+  time_stats_t phy_proc_rx[RX_NB_TH];
+
+  uint32_t use_ia_receiver;
+
+  time_stats_t ofdm_mod_stats;
+  time_stats_t ulsch_encoding_stats;
+  time_stats_t ulsch_modulation_stats;
+  time_stats_t ulsch_segmentation_stats;
+  time_stats_t ulsch_rate_matching_stats;
+  time_stats_t ulsch_turbo_encoding_stats;
+  time_stats_t ulsch_interleaving_stats;
+  time_stats_t ulsch_multiplexing_stats;
+
+  time_stats_t generic_stat;
+  time_stats_t generic_stat_bis[RX_NB_TH][LTE_SLOTS_PER_SUBFRAME];
+  time_stats_t ue_front_end_stat[RX_NB_TH];
+  time_stats_t ue_front_end_per_slot_stat[RX_NB_TH][LTE_SLOTS_PER_SUBFRAME];
+  time_stats_t pdcch_procedures_stat[RX_NB_TH];
+  time_stats_t pdsch_procedures_stat[RX_NB_TH];
+  time_stats_t pdsch_procedures_per_slot_stat[RX_NB_TH][LTE_SLOTS_PER_SUBFRAME];
+  time_stats_t dlsch_procedures_stat[RX_NB_TH];
+
+  time_stats_t ofdm_demod_stats;
+  time_stats_t dlsch_rx_pdcch_stats;
+  time_stats_t rx_dft_stats;
+  time_stats_t dlsch_channel_estimation_stats;
+  time_stats_t dlsch_freq_offset_estimation_stats;
+  time_stats_t dlsch_decoding_stats[2];
+  time_stats_t dlsch_demodulation_stats;
+  time_stats_t dlsch_rate_unmatching_stats;
+  time_stats_t dlsch_turbo_decoding_stats;
+  time_stats_t dlsch_deinterleaving_stats;
+  time_stats_t dlsch_llr_stats;
+  time_stats_t dlsch_llr_stats_parallelization[RX_NB_TH][LTE_SLOTS_PER_SUBFRAME];
+  time_stats_t dlsch_unscrambling_stats;
+  time_stats_t dlsch_rate_matching_stats;
+  time_stats_t dlsch_turbo_encoding_stats;
+  time_stats_t dlsch_interleaving_stats;
+  time_stats_t dlsch_tc_init_stats;
+  time_stats_t dlsch_tc_alpha_stats;
+  time_stats_t dlsch_tc_beta_stats;
+  time_stats_t dlsch_tc_gamma_stats;
+  time_stats_t dlsch_tc_ext_stats;
+  time_stats_t dlsch_tc_intl1_stats;
+  time_stats_t dlsch_tc_intl2_stats;
+  time_stats_t tx_prach;
+
+  /// RF and Interface devices per CC
+
+  openair0_device rfdevice; 
+} PHY_VARS_UE;
+
+/* this structure is used to pass both UE phy vars and
+ * proc to the function UE_thread_rxn_txnp4
+ */
+struct rx_tx_thread_data {
+  PHY_VARS_UE    *UE;
+  UE_rxtx_proc_t *proc;
+};
+
+
+#endif //  __PHY_DEFS__H__

openair1/PHY/defs_common.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*! \file PHY/defs.h
+ \brief Top-level defines and structure definitions
+ \author R. Knopp, F. Kaltenberger
+ \date 2011
+ \version 0.1
+ \company Eurecom
+ \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr
+ \note
+ \warning
+*/
+#ifndef __PHY_DEFS_COMMON_H__
+#define __PHY_DEFS_COMMON_H__
+
+
+#define _GNU_SOURCE
+#include <sched.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <linux/sched.h>
+#include <signal.h>
+#include <execinfo.h>
+#include <getopt.h>
+#include <sys/sysinfo.h>
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <malloc.h>
+#include <string.h>
+#include <math.h>
+#include "common_lib.h"
+#include "msc.h"
+
+
+//#include <complex.h>
+#include "assertions.h"
+
+#include "sse_intrin.h"
+#ifdef MEX
+# define msg mexPrintf
+#endif
+//use msg in the real-time thread context
+#define msg_nrt printf
+//use msg_nrt in the non real-time context (for initialization, ...)
+#ifndef malloc16
+#  ifdef __AVX2__
+#    define malloc16(x) memalign(32,x)
+#  else
+#    define malloc16(x) memalign(16,x)
+#  endif
+#endif
+#define free16(y,x) free(y)
+#define bigmalloc malloc
+#define bigmalloc16 malloc16
+#define openair_free(y,x) free((y))
+#define PAGE_SIZE 4096
+#define free_and_zero(PtR) do { \
+      if (PtR) {           \
+        free(PtR);         \
+        PtR = NULL;        \
+      }                    \
+    } while (0)
+
+#define RX_NB_TH_MAX 2
+#define RX_NB_TH 2
+
+
+//! \brief Allocate \c size bytes of memory on the heap with alignment 16 and zero it afterwards.
+//! If no more memory is available, this function will terminate the program with an assertion error.
+static inline void* malloc16_clear( size_t size )
+{
+#ifdef __AVX2__
+  void* ptr = memalign(32, size);
+#else
+  void* ptr = memalign(16, size);
+#endif
+  DevAssert(ptr);
+  memset( ptr, 0, size );
+  return ptr;
+}
+
+
+
+#define PAGE_MASK 0xfffff000
+#define virt_to_phys(x) (x)
+
+#define openair_sched_exit() exit(-1)
+
+
+#define max(a,b)  ((a)>(b) ? (a) : (b))
+#define min(a,b)  ((a)<(b) ? (a) : (b))
+
+
+#define bzero(s,n) (memset((s),0,(n)))
+
+#define cmax(a,b)  ((a>b) ? (a) : (b))
+#define cmin(a,b)  ((a<b) ? (a) : (b))
+
+#define cmax3(a,b,c) ((cmax(a,b)>c) ? (cmax(a,b)) : (c))
+
+/// suppress compiler warning for unused arguments
+#define UNUSED(x) (void)x;
+
+
+#include "PHY/TOOLS/time_meas.h"
+#include "platform_types.h"
+#define MAX_NUM_RU_PER_eNB 64 
+
+#include <pthread.h>
+
+#include "targets/ARCH/COMMON/common_lib.h"
+#include "targets/COMMON/openairinterface5g_limits.h"
+
+#include "types.h"
+#include "nfapi_interface.h"
+//#include "defs.h"
+#include "openair2/COMMON/platform_types.h"
+
+#define RX_NB_TH_MAX 2
+#define RX_NB_TH 2
+
+#define LTE_SLOTS_PER_SUBFRAME 2
+
+#define LTE_NUMBER_OF_SUBFRAMES_PER_FRAME 10
+#define LTE_SLOTS_PER_FRAME  20
+#define LTE_CE_FILTER_LENGTH 5
+#define LTE_CE_OFFSET LTE_CE_FILTER_LENGTH
+#define TX_RX_SWITCH_SYMBOL (NUMBER_OF_SYMBOLS_PER_FRAME>>1)
+#define PBCH_PDU_SIZE 3 //bytes
+
+#define PRACH_SYMBOL 3 //position of the UL PSS wrt 2nd slot of special subframe
+
+#define NUMBER_OF_FREQUENCY_GROUPS (lte_frame_parms->N_RB_DL)
+
+#define SSS_AMP 1148
+
+#define MAX_NUM_PHICH_GROUPS 56  //110 RBs Ng=2, p.60 36-212, Sec. 6.9
+
+#define MAX_MBSFN_AREA 8
+
+#define NB_RX_ANTENNAS_MAX 64
+
+#ifdef OCP_FRAMEWORK
+#include "enums.h"
+#else
+typedef enum {TDD=1,FDD=0} lte_frame_type_t;
+
+typedef enum {EXTENDED=1,NORMAL=0} lte_prefix_type_t;
+
+typedef enum {LOCALIZED=0,DISTRIBUTED=1} vrb_t;
+
+/// Enumeration for parameter PHICH-Duration \ref PHICH_CONFIG_COMMON::phich_duration.
+typedef enum {
+  normal=0,
+  extended=1
+} PHICH_DURATION_t;
+
+/// Enumeration for parameter Ng \ref PHICH_CONFIG_COMMON::phich_resource.
+typedef enum {
+  oneSixth=1,
+  half=3,
+  one=6,
+  two=12
+} PHICH_RESOURCE_t;
+#endif
+/// PHICH-Config from 36.331 RRC spec
+typedef struct {
+  /// Parameter: PHICH-Duration, see TS 36.211 (Table 6.9.3-1).
+  PHICH_DURATION_t phich_duration;
+  /// Parameter: Ng, see TS 36.211 (6.9). \details Value oneSixth corresponds to 1/6, half corresponds to 1/2 and so on.
+  PHICH_RESOURCE_t phich_resource;
+} PHICH_CONFIG_COMMON;
+
+/// PRACH-ConfigInfo from 36.331 RRC spec
+typedef struct {
+  /// Parameter: prach-ConfigurationIndex, see TS 36.211 (5.7.1). \vr{[0..63]}
+  uint8_t prach_ConfigIndex;
+  /// Parameter: High-speed-flag, see TS 36.211 (5.7.2). \vr{[0..1]} 1 corresponds to Restricted set and 0 to Unrestricted set.
+  uint8_t highSpeedFlag;
+  /// Parameter: \f$N_\text{CS}\f$, see TS 36.211 (5.7.2). \vr{[0..15]}\n Refer to table 5.7.2-2 for preamble format 0..3 and to table 5.7.2-3 for preamble format 4.
+  uint8_t zeroCorrelationZoneConfig;
+  /// Parameter: prach-FrequencyOffset, see TS 36.211 (5.7.1). \vr{[0..94]}\n For TDD the value range is dependent on the value of \ref prach_ConfigIndex.
+  uint8_t prach_FreqOffset;
+} PRACH_CONFIG_INFO;
+
+
+
+/// PRACH-ConfigSIB or PRACH-Config from 36.331 RRC spec
+typedef struct {
+  /// Parameter: RACH_ROOT_SEQUENCE, see TS 36.211 (5.7.1). \vr{[0..837]}
+  uint16_t rootSequenceIndex;
+  /// prach_Config_enabled=1 means enabled. \vr{[0..1]}
+  uint8_t prach_Config_enabled;
+  /// PRACH Configuration Information
+  PRACH_CONFIG_INFO prach_ConfigInfo;
+} PRACH_CONFIG_COMMON;
+
+#ifdef Rel14
+
+/// PRACH-eMTC-Config from 36.331 RRC spec
+typedef struct {
+  /// Parameter: High-speed-flag, see TS 36.211 (5.7.2). \vr{[0..1]} 1 corresponds to Restricted set and 0 to Unrestricted set.
+  uint8_t highSpeedFlag;
+/// Parameter: \f$N_\text{CS}\f$, see TS 36.211 (5.7.2). \vr{[0..15]}\n Refer to table 5.7.2-2 for preamble format 0..3 and to table 5.7.2-3 for preamble format 4.
+  uint8_t zeroCorrelationZoneConfig;
+  /// Parameter: prach-FrequencyOffset, see TS 36.211 (5.7.1). \vr{[0..94]}\n For TDD the value range is dependent on the value of \ref prach_ConfigIndex.
+
+  /// PRACH starting subframe periodicity, expressed in number of subframes available for preamble transmission (PRACH opportunities), see TS 36.211. Value 2 corresponds to 2 subframes, 4 corresponds to 4 subframes and so on. EUTRAN configures the PRACH starting subframe periodicity larger than or equal to the Number of PRACH repetitions per attempt for each CE level (numRepetitionPerPreambleAttempt).
+  uint8_t prach_starting_subframe_periodicity[4];
+  /// number of repetitions per preamble attempt per CE level
+  uint8_t prach_numRepetitionPerPreambleAttempt[4];
+  /// prach configuration index for each CE level
+  uint8_t prach_ConfigIndex[4];
+  /// indicator for CE level activation
+  uint8_t prach_CElevel_enable[4];
+  /// prach frequency offset for each CE level 
+  uint8_t prach_FreqOffset[4];
+  /// indicator for CE level hopping activation
+  uint8_t prach_hopping_enable[4];
+  /// indicator for CE level hopping activation
+  uint8_t prach_hopping_offset[4];
+} PRACH_eMTC_CONFIG_INFO;
+
+/// PRACH-ConfigSIB or PRACH-Config from 36.331 RRC spec
+typedef struct {
+  /// Parameter: RACH_ROOT_SEQUENCE, see TS 36.211 (5.7.1). \vr{[0..837]}
+  uint16_t rootSequenceIndex;
+  /// prach_Config_enabled=1 means enabled. \vr{[0..1]}
+  uint8_t prach_Config_enabled;
+  /// PRACH Configuration Information
+#ifdef Rel14
+  PRACH_eMTC_CONFIG_INFO prach_ConfigInfo;
+#endif  
+} PRACH_eMTC_CONFIG_COMMON;
+
+#endif
+
+/// Enumeration for parameter \f$N_\text{ANRep}\f$ \ref PUCCH_CONFIG_DEDICATED::repetitionFactor.
+typedef enum {
+  n2=0,
+  n4,
+  n6
+} ACKNAKREP_t;
+
+/// Enumeration for \ref PUCCH_CONFIG_DEDICATED::tdd_AckNackFeedbackMode.
+typedef enum {
+  bundling=0,
+  multiplexing
+} ANFBmode_t;
+
+/// PUCCH-ConfigDedicated from 36.331 RRC spec
+typedef struct {
+  /// Flag to indicate ACK NAK repetition activation, see TS 36.213 (10.1). \vr{[0..1]}
+  uint8_t ackNackRepetition;
+  /// Parameter: \f$N_\text{ANRep}\f$, see TS 36.213 (10.1).
+  ACKNAKREP_t repetitionFactor;
+  /// Parameter: \f$n^{(1)}_\text{PUCCH,ANRep}\f$, see TS 36.213 (10.1). \vr{[0..2047]}
+  uint16_t n1PUCCH_AN_Rep;
+  /// Feedback mode, see TS 36.213 (7.3). \details Applied to both PUCCH and PUSCH feedback. For TDD, should always be set to bundling.
+  ANFBmode_t tdd_AckNackFeedbackMode;
+} PUCCH_CONFIG_DEDICATED;
+
+/// PUCCH-ConfigCommon from 36.331 RRC spec
+typedef struct {
+  /// Parameter: \f$\Delta^\text{PUCCH}_\text{shift}\f$, see TS 36.211 (5.4.1). \vr{[1..3]} \note the specification sais it is an enumerated value.
+  uint8_t deltaPUCCH_Shift;
+  /// Parameter: \f$N^{(2)}_\text{RB}\f$, see TS 36.211 (5.4). \vr{[0..98]}
+  uint8_t nRB_CQI;
+  /// Parameter: \f$N^{(1)}_\text{CS}\f$, see TS 36.211 (5.4). \vr{[0..7]}
+  uint8_t nCS_AN;
+  /// Parameter: \f$N^{(1)}_\text{PUCCH}\f$ see TS 36.213 (10.1). \vr{[0..2047]}
+  uint16_t n1PUCCH_AN;
+
+  /// group hopping sequence for DRS \note not part of offical UL-PUCCH_CONFIG_COMMON ASN1 specification.
+  uint8_t grouphop[20];
+  /// sequence hopping sequence for DRS \note not part of offical UL-PUCCH_CONFIG_COMMON ASN1 specification.
+  uint8_t seqhop[20];
+} PUCCH_CONFIG_COMMON;
+
+/// UL-ReferenceSignalsPUSCH from 36.331 RRC spec
+typedef struct {
+  /// Parameter: Group-hopping-enabled, see TS 36.211 (5.5.1.3). \vr{[0..1]}
+  uint8_t groupHoppingEnabled;
+  /// Parameter: \f$\Delta SS\f$, see TS 36.211 (5.5.1.3). \vr{[0..29]}
+  uint8_t groupAssignmentPUSCH;
+  /// Parameter: Sequence-hopping-enabled, see TS 36.211 (5.5.1.4). \vr{[0..1]}
+  uint8_t sequenceHoppingEnabled;
+  /// Parameter: cyclicShift, see TS 36.211 (Table 5.5.2.1.1-2). \vr{[0..7]}
+  uint8_t cyclicShift;
+  /// nPRS for cyclic shift of DRS \note not part of offical UL-ReferenceSignalsPUSCH ASN1 specification.
+  uint8_t nPRS[20];
+  /// group hopping sequence for DRS \note not part of offical UL-ReferenceSignalsPUSCH ASN1 specification.
+  uint8_t grouphop[20];
+  /// sequence hopping sequence for DRS \note not part of offical UL-ReferenceSignalsPUSCH ASN1 specification.
+  uint8_t seqhop[20];
+} UL_REFERENCE_SIGNALS_PUSCH_t;
+
+/// Enumeration for parameter Hopping-mode \ref PUSCH_CONFIG_COMMON::hoppingMode.
+#ifndef OCP_FRAMEWORK
+typedef enum {
+  interSubFrame=0,
+  intraAndInterSubFrame=1
+} PUSCH_HOPPING_t;
+#endif
+
+/// PUSCH-ConfigCommon from 36.331 RRC spec.
+typedef struct {
+  /// Parameter: \f$N_{sb}\f$, see TS 36.211 (5.3.4). \vr{[1..4]}
+  uint8_t n_SB;
+  /// Parameter: Hopping-mode, see TS 36.211 (5.3.4).
+  PUSCH_HOPPING_t hoppingMode;
+  /// Parameter: \f$N^{HO}_{RB}\f$, see TS 36.211 (5.3.4). \vr{[0..98]}
+  uint8_t pusch_HoppingOffset;
+  /// See TS 36.213 (8.6.1). \vr{[0..1]} 1 indicates 64QAM is allowed, 0 not allowed.
+  uint8_t enable64QAM;
+  /// Ref signals configuration
+  UL_REFERENCE_SIGNALS_PUSCH_t ul_ReferenceSignalsPUSCH;
+} PUSCH_CONFIG_COMMON;
+
+/// UE specific PUSCH configuration.
+typedef struct {
+  /// Parameter: \f$I^\text{HARQ-ACK}_\text{offset}\f$, see TS 36.213 (Table 8.6.3-1). \vr{[0..15]}
+  uint16_t betaOffset_ACK_Index;
+  /// Parameter: \f$I^{RI}_\text{offset}\f$, see TS 36.213 (Table 8.6.3-2). \vr{[0..15]}
+  uint16_t betaOffset_RI_Index;
+  /// Parameter: \f$I^{CQI}_\text{offset}\f$, see TS 36.213 (Table 8.6.3-3). \vr{[0..15]}
+  uint16_t betaOffset_CQI_Index;
+} PUSCH_CONFIG_DEDICATED;
+
+/// lola CBA information
+typedef struct {
+  ///
+  uint16_t betaOffset_CA_Index;
+  ///
+  uint16_t cShift;
+} PUSCH_CA_CONFIG_DEDICATED;
+
+/// PDSCH-ConfigCommon from 36.331 RRC spec
+typedef struct {
+  /// Parameter: Reference-signal power, see TS 36.213 (5.2). \vr{[-60..50]}\n Provides the downlink reference-signal EPRE. The actual value in dBm.
+  int8_t referenceSignalPower;
+  /// Parameter: \f$P_B\f$, see TS 36.213 (Table 5.2-1). \vr{[0..3]}
+  uint8_t p_b;
+} PDSCH_CONFIG_COMMON;
+
+/// Enumeration for Parameter \f$P_A\f$ \ref PDSCH_CONFIG_DEDICATED::p_a.
+typedef enum {
+  dBm6=0, ///< (dB-6) corresponds to -6 dB
+  dBm477, ///< (dB-4dot77) corresponds to -4.77 dB
+  dBm3,   ///< (dB-3) corresponds to -3 dB
+  dBm177, ///< (dB-1dot77) corresponds to -1.77 dB
+  dB0,    ///< corresponds to 0 dB
+  dB1,    ///< corresponds to 1 dB
+  dB2,    ///< corresponds to 2 dB
+  dB3     ///< corresponds to 3 dB
+} PA_t;
+
+/// PDSCH-ConfigDedicated from 36.331 RRC spec
+typedef struct {
+  /// Parameter: \f$P_A\f$, see TS 36.213 (5.2).
+  PA_t p_a;
+} PDSCH_CONFIG_DEDICATED;
+
+/// SoundingRS-UL-ConfigCommon Information Element from 36.331 RRC spec
+typedef struct {
+  /// enabled flag=1 means SRS is enabled. \vr{[0..1]}
+  uint8_t enabled_flag;
+  /// Parameter: SRS Bandwidth Configuration, see TS 36.211 (table 5.5.3.2-1, 5.5.3.2-2, 5.5.3.2-3 and 5.5.3.2-4). \vr{[0..7]}\n Actual configuration depends on UL bandwidth. \note the specification sais it is an enumerated value.
+  uint8_t srs_BandwidthConfig;
+  /// Parameter: SRS SubframeConfiguration, see TS 36.211 (table 5.5.3.3-1 for FDD, table 5.5.3.3-2 for TDD). \vr{[0..15]} \note the specification sais it is an enumerated value.
+  uint8_t srs_SubframeConfig;
+  /// Parameter: Simultaneous-AN-and-SRS, see TS 36.213 (8.2). \vr{[0..1]}
+  uint8_t ackNackSRS_SimultaneousTransmission;
+  /// Parameter: srsMaxUpPts, see TS 36.211 (5.5.3.2). \details If this field is present, reconfiguration of \f$m^\text{max}_\text{SRS,0}\f$ applies for UpPts, otherwise reconfiguration does not apply.
+  uint8_t srs_MaxUpPts;
+} SOUNDINGRS_UL_CONFIG_COMMON;
+
+/// \note UNUSED
+typedef enum {
+  ulpc_al0=0,
+  ulpc_al04=1,
+  ulpc_al05=2,
+  ulpc_al06=3,
+  ulpc_al07=4,
+  ulpc_al08=5,
+  ulpc_al09=6,
+  ulpc_al11=7
+} UL_POWER_CONTROL_COMMON_alpha_t;
+
+/// Enumeration for \ref deltaFList_PUCCH_t::deltaF_PUCCH_Format1.
+typedef enum {
+  deltaF_PUCCH_Format1_deltaF_2  = 0,
+  deltaF_PUCCH_Format1_deltaF0   = 1,
+  deltaF_PUCCH_Format1_deltaF2   = 2
+} deltaF_PUCCH_Format1_t;
+
+/// Enumeration for \ref deltaFList_PUCCH_t::deltaF_PUCCH_Format1b.
+typedef enum {
+  deltaF_PUCCH_Format1b_deltaF1  = 0,
+  deltaF_PUCCH_Format1b_deltaF3  = 1,
+  deltaF_PUCCH_Format1b_deltaF5  = 2
+} deltaF_PUCCH_Format1b_t;
+
+/// Enumeration for \ref deltaFList_PUCCH_t::deltaF_PUCCH_Format2.
+typedef enum {
+  deltaF_PUCCH_Format2_deltaF_2  = 0,
+  deltaF_PUCCH_Format2_deltaF0   = 1,
+  deltaF_PUCCH_Format2_deltaF1   = 2,
+  deltaF_PUCCH_Format2_deltaF2   = 3
+} deltaF_PUCCH_Format2_t;
+
+/// Enumeration for \ref deltaFList_PUCCH_t::deltaF_PUCCH_Format2a.
+typedef enum {
+  deltaF_PUCCH_Format2a_deltaF_2 = 0,
+  deltaF_PUCCH_Format2a_deltaF0  = 1,
+  deltaF_PUCCH_Format2a_deltaF2  = 2
+} deltaF_PUCCH_Format2a_t;
+
+/// Enumeration for \ref deltaFList_PUCCH_t::deltaF_PUCCH_Format2b.
+typedef enum {
+  deltaF_PUCCH_Format2b_deltaF_2 = 0,
+  deltaF_PUCCH_Format2b_deltaF0  = 1,
+  deltaF_PUCCH_Format2b_deltaF2  = 2
+} deltaF_PUCCH_Format2b_t;
+
+/// DeltaFList-PUCCH from 36.331 RRC spec
+typedef struct {
+  deltaF_PUCCH_Format1_t   deltaF_PUCCH_Format1;
+  deltaF_PUCCH_Format1b_t  deltaF_PUCCH_Format1b;
+  deltaF_PUCCH_Format2_t   deltaF_PUCCH_Format2;
+  deltaF_PUCCH_Format2a_t  deltaF_PUCCH_Format2a;
+  deltaF_PUCCH_Format2b_t  deltaF_PUCCH_Format2b;
+} deltaFList_PUCCH_t;
+
+/// SoundingRS-UL-ConfigDedicated Information Element from 36.331 RRC spec
+typedef struct {
+  /// This descriptor is active
+  uint8_t active;
+  /// This descriptor's frame
+  uint16_t frame;
+  /// This descriptor's subframe
+  uint8_t  subframe;
+  /// rnti
+  uint16_t rnti;
+  /// Parameter: \f$B_\text{SRS}\f$, see TS 36.211 (table 5.5.3.2-1, 5.5.3.2-2, 5.5.3.2-3 and 5.5.3.2-4). \vr{[0..3]} \note the specification sais it is an enumerated value.
+  uint8_t srs_Bandwidth;
+  /// Parameter: SRS hopping bandwidth \f$b_\text{hop}\in\{0,1,2,3\}\f$, see TS 36.211 (5.5.3.2) \vr{[0..3]} \note the specification sais it is an enumerated value.
+  uint8_t srs_HoppingBandwidth;
+  /// Parameter: \f$n_\text{RRC}\f$, see TS 36.211 (5.5.3.2). \vr{[0..23]}
+  uint8_t freqDomainPosition;
+  /// Parameter: Duration, see TS 36.213 (8.2). \vr{[0..1]} 0 corresponds to "single" and 1 to "indefinite".
+  uint8_t duration;
+  /// Parameter: \f$k_\text{TC}\in\{0,1\}\f$, see TS 36.211 (5.5.3.2). \vr{[0..1]}
+  uint8_t transmissionComb;
+  /// Parameter: \f$I_\text{SRS}\f$, see TS 36.213 (table 8.2-1). \vr{[0..1023]}
+  uint16_t srs_ConfigIndex;
+  /// Parameter: \f$n^\text{CS}_\text{SRS}\f$. See TS 36.211 (5.5.3.1). \vr{[0..7]} \note the specification sais it is an enumerated value.
+  uint8_t cyclicShift;
+  // Parameter: internal implementation: UE SRS configured
+  uint8_t srsConfigDedicatedSetup;
+  // Parameter: cell srs subframe for internal implementation
+  uint8_t srsCellSubframe;
+  // Parameter: ue srs subframe for internal implementation
+  uint8_t srsUeSubframe;
+} SOUNDINGRS_UL_CONFIG_DEDICATED;
+
+/// UplinkPowerControlDedicated Information Element from 36.331 RRC spec
+typedef struct {
+  /// Parameter: \f$P_\text{0\_UE\_PUSCH}(1)\f$, see TS 36.213 (5.1.1.1), unit dB. \vr{[-8..7]}\n This field is applicable for non-persistent scheduling, only.
+  int8_t p0_UE_PUSCH;
+  /// Parameter: Ks, see TS 36.213 (5.1.1.1). \vr{[0..1]}\n en0 corresponds to value 0 corresponding to state “disabled”. en1 corresponds to value 1.25 corresponding to “enabled”. \note the specification sais it is an enumerated value. \warning the enumeration values do not correspond to the given values in the specification (en1 should be 1.25).
+  uint8_t deltaMCS_Enabled;
+  /// Parameter: Accumulation-enabled, see TS 36.213 (5.1.1.1). \vr{[0..1]} 1 corresponds to "enabled" whereas 0 corresponds to "disabled".
+  uint8_t accumulationEnabled;
+  /// Parameter: \f$P_\text{0\_UE\_PUCCH}(1)\f$, see TS 36.213 (5.1.2.1), unit dB. \vr{[-8..7]}
+  int8_t p0_UE_PUCCH;
+  /// Parameter: \f$P_\text{SRS\_OFFSET}\f$, see TS 36.213 (5.1.3.1). \vr{[0..15]}\n For Ks=1.25 (\ref deltaMCS_Enabled), the actual parameter value is pSRS_Offset value - 3. For Ks=0, the actual parameter value is -10.5 + 1.5*pSRS_Offset value.
+  int8_t pSRS_Offset;
+  /// Specifies the filtering coefficient for RSRP measurements used to calculate path loss, as specified in TS 36.213 (5.1.1.1).\details The same filtering mechanism applies as for quantityConfig described in 5.5.3.2. \note the specification sais it is an enumerated value.
+  uint8_t filterCoefficient;
+} UL_POWER_CONTROL_DEDICATED;
+
+#ifndef OCP_FRAMEWORK
+/// Enumeration for parameter \f$\alpha\f$ \ref UL_POWER_CONTROL_CONFIG_COMMON::alpha.
+typedef enum {
+  al0=0,
+  al04=1,
+  al05=2,
+  al06=3,
+  al07=4,
+  al08=5,
+  al09=6,
+  al1=7
+} PUSCH_alpha_t;
+#endif
+
+/// \note UNUSED
+typedef enum {
+  deltaFm2=0,
+  deltaF0,
+  deltaF1,
+  deltaF2,
+  deltaF3,
+  deltaF5
+} deltaF_PUCCH_t;
+
+/// UplinkPowerControlCommon Information Element from 36.331 RRC spec \note this structure does not currently make use of \ref deltaFList_PUCCH_t.
+typedef struct {
+  /// Parameter: \f$P_\text{0\_NOMINAL\_PUSCH}(1)\f$, see TS 36.213 (5.1.1.1), unit dBm. \vr{[-126..24]}\n This field is applicable for non-persistent scheduling, only.
+  int8_t p0_NominalPUSCH;
+  /// Parameter: \f$\alpha\f$, see TS 36.213 (5.1.1.1) \warning the enumeration values do not correspond to the given values in the specification (al04 should be 0.4, ...)!
+  PUSCH_alpha_t alpha;
+  /// Parameter: \f$P_\text{0\_NOMINAL\_PUCCH}\f$ See TS 36.213 (5.1.2.1), unit dBm. \vr{[-127..-96]}
+  int8_t p0_NominalPUCCH;
+  /// Parameter: \f$\Delta_\text{PREAMBLE\_Msg3}\f$ see TS 36.213 (5.1.1.1). \vr{[-1..6]}\n Actual value = IE value * 2 [dB].
+  int8_t deltaPreambleMsg3;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 1, see TS 36.213 (5.1.2). \vr{[0..2]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format1;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 1a, see TS 36.213 (5.1.2). \vr{[0..2]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format1a;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 1b, see TS 36.213 (5.1.2). \vr{[0..2]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format1b;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 2, see TS 36.213 (5.1.2). \vr{[0..3]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format2;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 2a, see TS 36.213 (5.1.2). \vr{[0..2]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format2a;
+  /// Parameter: \f$\Delta_\text{F\_PUCCH}(F)\f$ for the PUCCH format 2b, see TS 36.213 (5.1.2). \vr{[0..2]} \warning check value range, why is this a long? \note the specification sais it is an enumerated value.
+  long deltaF_PUCCH_Format2b;
+} UL_POWER_CONTROL_CONFIG_COMMON;
+
+/// Union for \ref TPC_PDCCH_CONFIG::tpc_Index.
+typedef union {
+  /// Index of N when DCI format 3 is used. See TS 36.212 (5.3.3.1.6). \vr{[1..15]}
+  uint8_t indexOfFormat3;
+  /// Index of M when DCI format 3A is used. See TS 36.212 (5.3.3.1.7). \vr{[1..31]}
+  uint8_t indexOfFormat3A;
+} TPC_INDEX_t;
+
+/// TPC-PDCCH-Config Information Element from 36.331 RRC spec
+typedef struct {
+  /// RNTI for power control using DCI format 3/3A, see TS 36.212. \vr{[0..65535]}
+  uint16_t rnti;
+  /// Index of N or M, see TS 36.212 (5.3.3.1.6 and 5.3.3.1.7), where N or M is dependent on the used DCI format (i.e. format 3 or 3a).
+  TPC_INDEX_t tpc_Index;
+} TPC_PDCCH_CONFIG;
+
+/// Enumeration for parameter SR transmission \ref SCHEDULING_REQUEST_CONFIG::dsr_TransMax.
+typedef enum {
+  sr_n4=0,
+  sr_n8=1,
+  sr_n16=2,
+  sr_n32=3,
+  sr_n64=4
+} DSR_TRANSMAX_t;
+
+/// SchedulingRequestConfig Information Element from 36.331 RRC spec
+typedef struct {
+  /// Parameter: \f$n^{(1)}_\text{PUCCH,SRI}\f$, see TS 36.213 (10.1). \vr{[0..2047]}
+  uint16_t sr_PUCCH_ResourceIndex;
+  /// Parameter: \f$I_\text{SR}\f$, see TS 36.213 (10.1). \vr{[0..155]}
+  uint8_t sr_ConfigIndex;
+  /// Parameter for SR transmission in TS 36.321 (5.4.4). \details The value n4 corresponds to 4 transmissions, n8 corresponds to 8 transmissions and so on.
+  DSR_TRANSMAX_t dsr_TransMax;
+} SCHEDULING_REQUEST_CONFIG;
+
+/// CQI-ReportPeriodic
+typedef struct {
+  /// Parameter: \f$n^{(2)}_\text{PUCCH}\f$, see TS 36.213 (7.2). \vr{[0..1185]}, -1 indicates inactivity
+  int16_t cqi_PUCCH_ResourceIndex;
+  /// Parameter: CQI/PMI Periodicity and Offset Configuration Index \f$I_\text{CQI/PMI}\f$, see TS 36.213 (tables 7.2.2-1A and 7.2.2-1C). \vr{[0..1023]}
+  int16_t cqi_PMI_ConfigIndex;
+  /// Parameter: K, see 36.213 (4.2.2). \vr{[1..4]}
+  uint8_t K;
+  /// Parameter: RI Config Index \f$I_\text{RI}\f$, see TS 36.213 (7.2.2-1B). \vr{[0..1023]}, -1 indicates inactivity
+  int16_t ri_ConfigIndex;
+  /// Parameter: Simultaneous-AN-and-CQI, see TS 36.213 (10.1). \vr{[0..1]} 1 indicates that simultaneous transmission of ACK/NACK and CQI is allowed.
+  uint8_t simultaneousAckNackAndCQI;
+  /// parameter computed from Tables 7.2.2-1A and 7.2.2-1C
+  uint16_t Npd;
+  /// parameter computed from Tables 7.2.2-1A and 7.2.2-1C
+  uint16_t N_OFFSET_CQI;
+} CQI_REPORTPERIODIC;
+
+/// Enumeration for parameter reporting mode \ref CQI_REPORT_CONFIG::cqi_ReportModeAperiodic.
+typedef enum {
+  rm12=0,
+  rm20=1,
+  rm22=2,
+  rm30=3,
+  rm31=4
+} CQI_REPORTMODEAPERIODIC;
+
+/// CQI-ReportConfig Information Element from 36.331 RRC spec
+typedef struct {
+  /// Parameter: reporting mode. Value rm12 corresponds to Mode 1-2, rm20 corresponds to Mode 2-0, rm22 corresponds to Mode 2-2 etc. PUSCH reporting modes are described in TS 36.213 [23, 7.2.1].
+  CQI_REPORTMODEAPERIODIC cqi_ReportModeAperiodic;
+  /// Parameter: \f$\Delta_\text{offset}\f$, see TS 36.213 (7.2.3). \vr{[-1..6]}\n Actual value = IE value * 2 [dB].
+  int8_t nomPDSCH_RS_EPRE_Offset;
+  CQI_REPORTPERIODIC CQI_ReportPeriodic;
+} CQI_REPORT_CONFIG;
+
+/// MBSFN-SubframeConfig Information Element from 36.331 RRC spec \note deviates from specification.
+typedef struct {
+  /// MBSFN subframe occurance. \details Radio-frames that contain MBSFN subframes occur when equation SFN mod radioFrameAllocationPeriod = radioFrameAllocationOffset is satisfied. When fourFrames is used for subframeAllocation, the equation defines the first radio frame referred to in the description below. Values n1 and n2 are not applicable when fourFrames is used. \note the specification sais it is an enumerated value {n1, n2, n4, n8, n16, n32}.
+  int radioframeAllocationPeriod;
+  /// MBSFN subframe occurance. \vr{[0..7]}\n Radio-frames that contain MBSFN subframes occur when equation SFN mod radioFrameAllocationPeriod = radioFrameAllocationOffset is satisfied. When fourFrames is used for subframeAllocation, the equation defines the first radio frame referred to in the description below. Values n1 and n2 are not applicable when fourFrames is used.
+  int radioframeAllocationOffset;
+  /// oneFrame or fourFrames. \vr{[0..1]}
+  int fourFrames_flag;
+  /// Subframe configuration. \vr{[0..63]} (\ref fourFrames_flag == 0) or \vr{[0..16777215]} (\ref fourFrames_flag == 1)
+  /// \par fourFrames_flag == 0
+  /// "1" denotes that the corresponding subframe is allocated for MBSFN. The following mapping applies:\n FDD: The first/leftmost bit defines the MBSFN allocation for subframe #1, the second bit for #2, third bit for #3 , fourth bit for #6, fifth bit for #7, sixth bit for #8.\n TDD: The first/leftmost bit defines the allocation for subframe #3, the second bit for #4, third bit for #7, fourth bit for #8, fifth bit for #9. Uplink subframes are not allocated. The last bit is not used.
+  /// \par fourFrames_flag == 1
+  /// A bit-map indicating MBSFN subframe allocation in four consecutive radio frames, "1" denotes that the corresponding subframe is allocated for MBSFN. The bitmap is interpreted as follows:\n FDD: Starting from the first radioframe and from the first/leftmost bit in the bitmap, the allocation applies to subframes #1, #2, #3 , #6, #7, and #8 in the sequence of the four radio-frames.\n TDD: Starting from the first radioframe and from the first/leftmost bit in the bitmap, the allocation applies to subframes #3, #4, #7, #8, and #9 in the sequence of the four radio-frames. The last four bits are not used. Uplink subframes are not allocated.
+  int mbsfn_SubframeConfig;
+} MBSFN_config_t;
+
+typedef struct {
+  /// Number of resource blocks (RB) in DL
+  uint8_t N_RB_DL;
+  /// Number of resource blocks (RB) in UL
+  uint8_t N_RB_UL;
+  /// EUTRA Band
+  uint8_t eutra_band;
+  /// DL carrier frequency
+  uint32_t dl_CarrierFreq;
+  /// UL carrier frequency
+  uint32_t ul_CarrierFreq;
+  /// TX attenuation
+  uint32_t att_tx;
+  /// RX attenuation
+  uint32_t att_rx;
+  ///  total Number of Resource Block Groups: this is ceil(N_PRB/P)
+  uint8_t N_RBG;
+  /// Total Number of Resource Block Groups SubSets: this is P
+  uint8_t N_RBGS;
+  /// Cell ID
+  uint16_t Nid_cell;
+  /// MBSFN Area ID
+  uint16_t Nid_cell_mbsfn;
+  /// Cyclic Prefix for DL (0=Normal CP, 1=Extended CP)
+  lte_prefix_type_t Ncp;
+  /// Cyclic Prefix for UL (0=Normal CP, 1=Extended CP)
+  lte_prefix_type_t Ncp_UL;
+  /// shift of pilot position in one RB
+  uint8_t nushift;
+  /// Frame type (0 FDD, 1 TDD)
+  lte_frame_type_t frame_type;
+  /// TDD subframe assignment (0-7) (default = 3) (254=RX only, 255=TX only)
+  uint8_t tdd_config;
+  /// TDD S-subframe configuration (0-9)
+  uint8_t tdd_config_S;
+  /// srs extra symbol flag for TDD
+  uint8_t srsX;
+  /// indicates if node is a UE (NODE=2) or eNB (PRIMARY_CH=0).
+  uint8_t node_id;
+  /// Indicator that 20 MHz channel uses 3/4 sampling frequency
+  uint8_t threequarter_fs;
+  /// Size of FFT
+  uint16_t ofdm_symbol_size;
+  /// Number of prefix samples in all but first symbol of slot
+  uint16_t nb_prefix_samples;
+  /// Number of prefix samples in first symbol of slot
+  uint16_t nb_prefix_samples0;
+  /// Carrier offset in FFT buffer for first RE in PRB0
+  uint16_t first_carrier_offset;
+  /// Number of samples in a subframe
+  uint32_t samples_per_tti;
+  /// Number of OFDM/SC-FDMA symbols in one subframe (to be modified to account for potential different in UL/DL)
+  uint16_t symbols_per_tti;
+  /// Number of OFDM symbols in DL portion of S-subframe
+  uint16_t dl_symbols_in_S_subframe;
+  /// Number of SC-FDMA symbols in UL portion of S-subframe
+  uint16_t ul_symbols_in_S_subframe;
+  /// Number of Physical transmit antennas in node
+  uint8_t nb_antennas_tx;
+  /// Number of Receive antennas in node
+  uint8_t nb_antennas_rx;
+  /// Number of common transmit antenna ports in eNodeB (1 or 2)
+  uint8_t nb_antenna_ports_eNB;
+  /// PRACH_CONFIG
+  PRACH_CONFIG_COMMON prach_config_common;
+#ifdef Rel14
+  /// PRACH_eMTC_CONFIG
+  PRACH_eMTC_CONFIG_COMMON prach_emtc_config_common;
+#endif
+  /// PUCCH Config Common (from 36-331 RRC spec)
+  PUCCH_CONFIG_COMMON pucch_config_common;
+  /// PDSCH Config Common (from 36-331 RRC spec)
+  PDSCH_CONFIG_COMMON pdsch_config_common;
+  /// PUSCH Config Common (from 36-331 RRC spec)
+  PUSCH_CONFIG_COMMON pusch_config_common;
+  /// PHICH Config (from 36-331 RRC spec)
+  PHICH_CONFIG_COMMON phich_config_common;
+  /// SRS Config (from 36-331 RRC spec)
+  SOUNDINGRS_UL_CONFIG_COMMON soundingrs_ul_config_common;
+  /// UL Power Control (from 36-331 RRC spec)
+  UL_POWER_CONTROL_CONFIG_COMMON ul_power_control_config_common;
+  /// Number of MBSFN Configurations
+  int num_MBSFN_config;
+  /// Array of MBSFN Configurations (max 8 (maxMBSFN-Allocations) elements as per 36.331)
+  MBSFN_config_t MBSFN_config[8];
+  /// Maximum Number of Retransmissions of RRCConnectionRequest (from 36-331 RRC Spec)
+  uint8_t maxHARQ_Msg3Tx;
+  /// Size of SI windows used for repetition of one SI message (in frames)
+  uint8_t SIwindowsize;
+  /// Period of SI windows used for repetition of one SI message (in frames)
+  uint16_t SIPeriod;
+  /// REGs assigned to PCFICH
+  uint16_t pcfich_reg[4];
+  /// Index of first REG assigned to PCFICH
+  uint8_t pcfich_first_reg_idx;
+  /// REGs assigned to PHICH
+  uint16_t phich_reg[MAX_NUM_PHICH_GROUPS][3];
+
+  struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[MAX_MBSFN_AREA];
+
+} LTE_DL_FRAME_PARMS;
+
+typedef enum {
+  /// TM1
+  SISO=0,
+  /// TM2
+  ALAMOUTI=1,
+  /// TM3
+  LARGE_CDD=2,
+  /// the next 6 entries are for TM5
+  UNIFORM_PRECODING11=3,
+  UNIFORM_PRECODING1m1=4,
+  UNIFORM_PRECODING1j=5,
+  UNIFORM_PRECODING1mj=6,
+  PUSCH_PRECODING0=7,
+  PUSCH_PRECODING1=8,
+  /// the next 3 entries are for TM4
+  DUALSTREAM_UNIFORM_PRECODING1=9,
+  DUALSTREAM_UNIFORM_PRECODINGj=10,
+  DUALSTREAM_PUSCH_PRECODING=11,
+  TM7=12,
+  TM8=13,
+  TM9_10=14
+} MIMO_mode_t;
+
+
+typedef enum {
+  /// MRT
+  MRT=0,
+  /// ZF
+  ZF=1,
+  /// MMSE
+  MMSE=2
+} PRECODE_TYPE_t;
+
+typedef enum {format0,
+              format1,
+              format1A,
+              format1B,
+              format1C,
+              format1D,
+              format1E_2A_M10PRB,
+              format2,
+              format2A,
+              format2B,
+              format2C,
+              format2D,
+              format3,
+	      format3A,
+	      format4,
+              format5,
+              format6_0A,
+              format6_0B,
+              format6_1A,
+              format6_1B,
+              format6_2
+             } DCI_format_t;
+
+typedef struct {
+  /// Length of DCI in bits
+  uint8_t dci_length;
+  /// Aggregation level
+  uint8_t L;
+  /// Position of first CCE of the dci
+  int firstCCE;
+  /// flag to indicate that this is a RA response
+  boolean_t ra_flag;
+  /// rnti
+  rnti_t rnti;
+  /// harq_pid
+  rnti_t harq_pid;
+  /// Format
+  DCI_format_t format;
+  /// DCI pdu
+  uint8_t dci_pdu[8];
+} DCI_ALLOC_t;
+
+#define MAX_EPDCCH_PRB 8
+
+typedef struct {
+  /// Length of DCI in bits
+  uint8_t dci_length;
+  /// Aggregation level
+  uint8_t L;
+  /// Position of first CCE of the dci
+  int firstCCE;
+  /// flag to indicate that this is a RA response
+  boolean_t ra_flag;
+  /// rnti
+  rnti_t rnti;
+  /// Format
+  DCI_format_t format;
+  /// epdcch resource assignment (0=localized,1=distributed) 
+  uint8_t epdcch_resource_assignment_flag;
+  /// epdcch index
+  uint16_t epdcch_id;
+  /// epdcch start symbol
+  uint8_t epdcch_start_symbol;
+  /// epdcch number of PRBs in set
+  uint8_t epdcch_num_prb;
+  /// vector of prb ids for set
+  uint8_t epdcch_prb_index[MAX_EPDCCH_PRB];  
+  /// LBT parameter for frame configuration
+  uint8_t dwpts_symbols;
+  /// LBT parameter for frame configuration
+  uint8_t initial_lbt_sf;
+  /// DCI pdu
+  uint8_t dci_pdu[8];
+} eDCI_ALLOC_t;
+ 
+typedef struct {
+  /// Length of DCI in bits
+  uint8_t dci_length;
+  /// Aggregation level
+  uint8_t L;
+  /// Position of first CCE of the dci
+  int firstCCE;
+  /// flag to indicate that this is a RA response
+  boolean_t ra_flag;
+  /// rnti
+  rnti_t rnti;
+  /// Format
+  DCI_format_t format;
+  /// harq process index
+  uint8_t harq_pid;
+  /// Narrowband index
+  uint8_t narrowband;
+  /// number of PRB pairs for MPDCCH
+  uint8_t number_of_prb_pairs;
+  /// mpdcch resource assignment (combinatorial index r)
+  uint8_t resource_block_assignment;
+  /// transmission type (0=localized,1=distributed) 
+  uint8_t transmission_type;
+  /// mpdcch start symbol
+  uint8_t start_symbol;
+  /// CE mode (1=ModeA,2=ModeB)
+  uint8_t ce_mode;
+  /// 0-503 n_EPDCCHid_i
+  uint16_t dmrs_scrambling_init;
+  /// Absolute subframe of the initial transmission (0-10239)
+  uint16_t i0;
+  /// number of mdpcch repetitions
+  uint16_t reps;
+  /// current absolute subframe number
+  uint16_t absSF;
+  /// DCI pdu
+  uint8_t dci_pdu[8];
+} mDCI_ALLOC_t;
+
+typedef struct {
+  /// Preamble index for PRACH (0-63)
+  uint8_t ra_PreambleIndex;
+  /// RACH MaskIndex
+  uint8_t ra_RACH_MaskIndex;
+  /// Target received power at eNB (-120 ... -82 dBm)
+  int8_t ra_PREAMBLE_RECEIVED_TARGET_POWER;
+  /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex
+  uint8_t ra_TDD_map_index;
+  /// Corresponding RA-RNTI for UL-grant
+  uint16_t ra_RNTI;
+  /// Pointer to Msg3 payload for UL-grant
+  uint8_t *Msg3;
+} PRACH_RESOURCES_t;
+
+
+typedef struct {
+  /// Downlink Power offset field
+  uint8_t dl_pow_off;
+  ///Subband resource allocation field
+  uint8_t rballoc_sub[50];
+  ///Total number of PRBs indicator
+  uint8_t pre_nb_available_rbs;
+} MU_MIMO_mode;
+
+typedef enum {
+  NOT_SYNCHED=0,
+  PRACH=1,
+  RA_RESPONSE=2,
+  PUSCH=3,
+  RESYNCH=4
+} UE_MODE_t;
+
+
+
+typedef enum {SF_DL, SF_UL, SF_S} lte_subframe_t;
+
+#define NUMBER_OF_SUBBANDS_MAX 13
+#define NUMBER_OF_HARQ_PID_MAX 8
+
+#define MAX_FRAME_NUMBER 0x400
+
+
+
+#define NUMBER_OF_RN_MAX 3
+typedef enum {no_relay=1,unicast_relay_type1,unicast_relay_type2, multicast_relay} relaying_type_t;
+
+
+
+#define MCS_COUNT 28
+#define MCS_TABLE_LENGTH_MAX 64
+
+
+#define NUM_DCI_MAX 32
+
+#define NUMBER_OF_eNB_SECTORS_MAX 3
+
+#define NB_BANDS_MAX 8
+
+#define MAX_BANDS_PER_RRU 4
+
+
+#ifdef OCP_FRAMEWORK
+#include <enums.h>
+#else
+typedef enum {normal_txrx=0,rx_calib_ue=1,rx_calib_ue_med=2,rx_calib_ue_byp=3,debug_prach=4,no_L2_connect=5,calib_prach_tx=6,rx_dump_frame=7,loop_through_memory=8} runmode_t;
+
+/*! \brief Extension Type */
+typedef enum {
+  CYCLIC_PREFIX,
+  CYCLIC_SUFFIX,
+  ZEROS,
+  NONE
+} Extension_t;
+	
+enum transmission_access_mode {
+  NO_ACCESS=0,
+  POSTPONED_ACCESS,
+  CANCELED_ACCESS,
+  UNKNOWN_ACCESS,
+  SCHEDULED_ACCESS,
+  CBA_ACCESS};
+
+typedef enum  {
+  eNodeB_3GPP=0,   // classical eNodeB function
+  NGFI_RAU_IF5,    // RAU with NGFI IF5
+  NGFI_RAU_IF4p5,  // RAU with NFGI IF4p5
+  NGFI_RRU_IF5,    // NGFI_RRU (NGFI remote radio-unit,IF5)
+  NGFI_RRU_IF4p5,  // NGFI_RRU (NGFI remote radio-unit,IF4p5)
+  MBP_RRU_IF5      // Mobipass RRU
+} node_function_t;
+
+typedef enum {
+
+  synch_to_ext_device=0,  // synch to RF or Ethernet device
+  synch_to_other,          // synch to another source_(timer, other RU)
+  synch_to_mobipass_standalone  // special case for mobipass in standalone mode
+} node_timing_t;
+#endif
+
+
+void exit_fun(const char* s);
+
+#include "UTIL/LOG/log_extern.h"
+extern pthread_cond_t sync_cond;
+extern pthread_mutex_t sync_mutex;
+extern int sync_var;
+
+
+#define MODE_DECODE_NONE         0
+#define MODE_DECODE_SSE          1
+#define MODE_DECODE_C            2
+#define MODE_DECODE_AVX2         3
+
+#define DECODE_INITTD8_SSE_FPTRIDX   0
+#define DECODE_INITTD16_SSE_FPTRIDX  1
+#define DECODE_INITTD_AVX2_FPTRIDX   2
+#define DECODE_TD8_SSE_FPTRIDX       3
+#define DECODE_TD16_SSE_FPTRIDX      4
+#define DECODE_TD_C_FPTRIDX          5
+#define DECODE_TD16_AVX2_FPTRIDX     6
+#define DECODE_FREETD8_FPTRIDX       7
+#define DECODE_FREETD16_FPTRIDX      8
+#define DECODE_FREETD_AVX2_FPTRIDX   9
+#define ENCODE_SSE_FPTRIDX           10
+#define ENCODE_C_FPTRIDX             11
+#define ENCODE_INIT_SSE_FPTRIDX      12
+#define DECODE_NUM_FPTR              13
+
+
+typedef uint8_t(*decoder_if_t)(int16_t *y,
+                               int16_t *y2,
+    		               uint8_t *decoded_bytes,
+    		               uint8_t *decoded_bytes2,
+	   		       uint16_t n,
+	   		       uint16_t f1,
+	   		       uint16_t f2,
+	   		       uint8_t max_iterations,
+	   		       uint8_t crc_type,
+	   		       uint8_t F,
+	   		       time_stats_t *init_stats,
+	   		       time_stats_t *alpha_stats,
+	   		       time_stats_t *beta_stats,
+	   		       time_stats_t *gamma_stats,
+	   		       time_stats_t *ext_stats,
+	   		       time_stats_t *intl1_stats,
+                               time_stats_t *intl2_stats);
+
+typedef uint8_t(*encoder_if_t)(uint8_t *input,
+                               uint16_t input_length_bytes,
+                               uint8_t *output,
+                               uint8_t F,
+                               uint16_t interleaver_f1,
+                               uint16_t interleaver_f2);
+
+
+static inline void wait_sync(char *thread_name) {
+
+  printf( "waiting for sync (%s)\n",thread_name);
+  pthread_mutex_lock( &sync_mutex );
+  
+  while (sync_var<0)
+    pthread_cond_wait( &sync_cond, &sync_mutex );
+  
+  pthread_mutex_unlock(&sync_mutex);
+  
+  printf( "got sync (%s)\n", thread_name);
+
+}
+
+static inline int wait_on_condition(pthread_mutex_t *mutex,pthread_cond_t *cond,int *instance_cnt,char *name) {
+  if (pthread_mutex_lock(mutex) != 0) {
+    LOG_E( PHY, "[SCHED][eNB] error locking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+
+  while (*instance_cnt < 0) {
+    // most of the time the thread is waiting here
+    // proc->instance_cnt_rxtx is -1
+    pthread_cond_wait(cond,mutex); // this unlocks mutex_rxtx while waiting and then locks it again
+  }
+
+  if (pthread_mutex_unlock(mutex) != 0) {
+    LOG_E(PHY,"[SCHED][eNB] error unlocking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+  return(0);
+}
+
+static inline int wait_on_busy_condition(pthread_mutex_t *mutex,pthread_cond_t *cond,int *instance_cnt,char *name) {
+
+  if (pthread_mutex_lock(mutex) != 0) {
+    LOG_E( PHY, "[SCHED][eNB] error locking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+
+  while (*instance_cnt == 0) {
+    // most of the time the thread will skip this
+    // waits only if proc->instance_cnt_rxtx is 0
+    pthread_cond_wait(cond,mutex); // this unlocks mutex_rxtx while waiting and then locks it again
+  }
+
+  if (pthread_mutex_unlock(mutex) != 0) {
+    LOG_E(PHY,"[SCHED][eNB] error unlocking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+  return(0);
+}
+
+static inline int release_thread(pthread_mutex_t *mutex,int *instance_cnt,char *name) {
+
+  if (pthread_mutex_lock(mutex) != 0) {
+    LOG_E( PHY, "[SCHED][eNB] error locking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+
+  *instance_cnt=*instance_cnt-1;
+
+  if (pthread_mutex_unlock(mutex) != 0) {
+    LOG_E( PHY, "[SCHED][eNB] error unlocking mutex for %s\n",name);
+    exit_fun("nothing to add");
+    return(-1);
+  }
+  return(0);
+}
+
+
+#endif //  __PHY_DEFS__H__

openair1/PHY/phy_extern_ue.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#ifndef __PHY_EXTERN_UE__H__
+#define __PHY_EXTERN_UE__H__
+
+#include "PHY/defs_UE.h"
+#include "common/ran_context.h"
+
+extern  char* namepointer_chMag ;
+extern char* namepointer_log2;
+extern  char fmageren_name2[512];
+
+extern unsigned int RX_DMA_BUFFER[4][NB_ANTENNAS_RX];
+extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX];
+
+#include "PHY/LTE_TRANSPORT/transport_extern.h"
+
+extern int number_of_cards;
+
+
+#ifndef OCP_FRAMEWORK
+extern PHY_VARS_UE ***PHY_vars_UE_g;
+extern LTE_DL_FRAME_PARMS *lte_frame_parms_g;
+#else
+#define MAX_UE 10
+#define MAX_eNB 20
+
+extern PHY_VARS_UE * PHY_vars_UE_g[MAX_UE][MAX_NUM_CCs];
+#endif
+
+extern short primary_synch0[144];
+extern short primary_synch1[144];
+extern short primary_synch2[144];
+extern unsigned char primary_synch0_tab[72];
+extern unsigned char primary_synch1_tab[72];
+extern unsigned char primary_synch2_tab[72];
+extern int16_t *primary_synch0_time; //!< index: [0..ofdm_symbol_size*2[
+extern int16_t *primary_synch1_time; //!< index: [0..ofdm_symbol_size*2[
+extern int16_t *primary_synch2_time; //!< index: [0..ofdm_symbol_size*2[
+extern int *sync_corr_ue0; //!< index [0..10*samples_per_tti[
+extern int *sync_corr_ue1; //!< index [0..10*samples_per_tti[
+extern int *sync_corr_ue2; //!< index [0..10*samples_per_tti[
+
+extern int flagMag;
+//extern short **txdataF_rep_tmp;
+
+extern char mode_string[4][20];
+
+extern unsigned char NB_RU;
+
+#ifndef OPENAIR2
+extern unsigned char NB_eNB_INST;
+extern unsigned char NB_UE_INST;
+extern unsigned char NB_RN_INST;
+#endif
+
+extern unsigned int ULSCH_max_consecutive_errors;
+extern int flag_LA;
+extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX];
+extern double sinr_bler_map_up[MCS_COUNT][2][16];
+extern int table_length[MCS_COUNT];
+extern double sinr_to_cqi[4][16];
+extern int cqi_to_mcs[16];
+
+//for MU-MIMO abstraction using MIESM
+//this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively
+extern double MI_map_4qam[3][162];
+extern double MI_map_16qam[3][197];
+extern double MI_map_64qam[3][227];
+
+extern double beta1_dlsch_MI[6][MCS_COUNT];
+extern double beta2_dlsch_MI[6][MCS_COUNT];
+
+extern double q_qpsk[8];
+extern double q_qam16[8];
+extern double q_qam64[8];
+
+extern double p_qpsk[8];
+extern double p_qam16[8];
+extern double p_qam64[8];
+
+extern double beta1_dlsch[6][MCS_COUNT];
+extern double beta2_dlsch[6][MCS_COUNT];
+
+extern char eNB_functions[6][20];
+extern char eNB_timing[2][20];
+extern char ru_if_types[MAX_RU_IF_TYPES][20];
+
+extern int16_t unscrambling_lut[65536*16];
+extern uint8_t scrambling_lut[65536*16];
+
+extern unsigned short msrsb_6_40[8][4];
+extern unsigned short msrsb_41_60[8][4];
+extern unsigned short msrsb_61_80[8][4];
+extern unsigned short msrsb_81_110[8][4];
+extern unsigned short Nb_6_40[8][4];
+extern unsigned short Nb_41_60[8][4];
+extern unsigned short Nb_61_80[8][4];
+extern unsigned short Nb_81_110[8][4];
+
+extern uint16_t hundred_times_log10_NPRB[100];
+extern uint8_t alpha_lut[8];
+extern uint8_t max_turbo_iterations;
+#endif /*__PHY_EXTERN_H__ */
+

openair1/PHY/phy_vars_ue.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#ifndef __PHY_VARS_H__
+#define __PHY_VARS_H__
+
+#include "PHY/types.h"
+#include "PHY/defs.h"
+#include "common/ran_context.h"
+
+char* namepointer_chMag ;
+char fmageren_name2[512];
+char* namepointer_log2;
+
+
+#include "PHY/LTE_REFSIG/primary_synch.h"
+int16_t *primary_synch0_time;
+int16_t *primary_synch1_time;
+int16_t *primary_synch2_time;
+
+
+#include "PHY/CODING/vars.h"
+
+//PHY_VARS *PHY_vars;
+#ifndef OCP_FRAMEWORK
+PHY_VARS_UE ***PHY_vars_UE_g;
+LTE_DL_FRAME_PARMS *lte_frame_parms_g;
+#else
+PHY_VARS_UE * PHY_vars_UE_g[MAX_UE][MAX_NUM_CCs]={NULL};
+
+#endif
+
+
+unsigned short rev[2048],rev_times4[8192],rev_half[1024];
+unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192];
+
+
+char mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"};
+#include "PHY/LTE_TRANSPORT/vars.h"
+
+
+
+#include "SIMULATION/ETH_TRANSPORT/vars.h"
+
+unsigned char NB_RU=0;
+
+#ifndef OPENAIR2
+unsigned char NB_eNB_INST=0;
+unsigned char NB_UE_INST=0;
+unsigned char NB_RN_INST=0;
+unsigned char NB_INST=0;
+#endif
+
+unsigned int ULSCH_max_consecutive_errors = 20;
+
+int number_of_cards;
+
+
+int flag_LA=0;
+int flagMag;
+//extern  channel_desc_t *eNB2UE[NUMBER_OF_eNB_MAX][NUMBER_OF_UE_MAX];
+//extern  double ABS_SINR_eff_BLER_table[MCS_COUNT][9][9];
+//extern  double ABS_beta[MCS_COUNT];odi
+double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX];
+int table_length[MCS_COUNT];
+//double sinr_bler_map_up[MCS_COUNT][2][16];
+
+//for MU-MIMO abstraction using MIESM
+//this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively
+double MI_map_4qam[3][162];
+double MI_map_16qam[3][197];
+double MI_map_64qam[3][227];
+
+// here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs
+double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281,  17.2424,  17.2424, 17.2424},
+  {-2.2360, -2.2360, -1.3919, -0.0218, 1.5319,  2.9574,  4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572},
+  {-1, -1.0000, -0.4198, -0.0140, 1.0362,  2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392},
+  { -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545}
+};
+
+//int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27};
+int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
+
+//for SNR to MI conversion 7 th order Polynomial coeff
+double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
+double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
+double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
+
+//for MI to SNR conversion 7 th order Polynomial coeff
+double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
+double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
+double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
+
+// ideal CE MIESM
+
+double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
+double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},  {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
+
+//real CE MIESM
+/*
+double beta1_dlsch_MI[6][MCS_COUNT] = { {1.32955, 0.59522, 0.54024, 0.98698, 0.81305, 0.76976, 0.69258, 0.69713, 0.70546, 0.69111, 0.81904, 0.72664, 0.79491, 0.72562, 0.53980, 0.33134, 0.50550, 0.40602,0.40281,0.47012,0.50510,0.23540,0.32045,1}, {0.59632, 1.08475, 1.02431, 1.07020, 0.90170, 0.97719, 0.95464, 0.92764, 0.86721, 0.85986, 0.64558, 0.80631, 0.82673, 0.82888, 0.87122, 0.77245, 0.29771, 0.43477, 0.55321, 0.61027, 0.56111, 0.57292, 0.39737,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.77532, 1.07544, 1.10571, 1.04099, 0.91638, 0.88644, 0.96405, 0.86709, 0.94066, 0.84430, 1.24478, 1.09665, 1.42604, 0.79541, 0.71847, 0.71604, 0.74561, 0.36431, 0.41536, 0.52175, 0.47096, 0.49977, 0.59728,1}};
+double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.81637, 0.76847, 0.69842, 0.69885, 0.69967, 0.69826, 0.82660, 0.70559, 0.78404, 0.70670, 0.55393, 0.36893, 0.52225, 0.39752, 0.40494, 0.46239, 0.49247,0.26900,0.34504,1}, {0.43775, 0.78208, 0.72875, 0.77458, 0.64485, 0.69174, 0.66097, 0.63289, 0.59652, 0.61175, 0.44551, 0.56047, 0.57314, 0.57553, 0.58849, 0.52159, 0.21241, 0.30139, 0.37373, 0.32029, 0.37067, 0.36706, 0.27118,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},  {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.54448, 0.73731, 0.79165, 0.74407, 0.68042, 0.64906, 0.71349, 0.62109, 0.65815, 0.60940, 0.90549, 0.78708, 1.03176, 0.58431, 0.53379, 0.51224, 0.52767, 0.26848, 0.29642, 0.36879, 0.34148, 0.35279,0.40633,1}};
+*/
+//ideal channel estimation values
+//double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
+//double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
+double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
+double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
+
+//real channel estimation valus
+/*
+double beta1_dlsch[6][MCS_COUNT] = { {2.50200, 0.84047, 0.78195, 1.37929, 1.16871, 1.11906, 1.06303, 1.07447, 1.11403, 1.09223, 2.82502, 2.87556, 3.51254, 3.62920, 3.53638, 2.35980, 3.74126, 8.66532, 7.31772, 9.86882, 10.64939, 6.75208, 9.50664, 13.63057}, {0.92257, 1, 1.80445, 1.43175, 1.42093, 1.37381, 1.45392, 1.47255, 1.47451, 1.41235, 3.9079, 3.38557, 4.13059, 4.93355, 4.97277, 6.04951, 5.88896, 8.68076, 10.23746, 12.37069, 5.50538, 17.29612, 17.95050, 13.27095}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79255, 1.88213, 4.44226, 2.25150, 1.93710, 2.18504, 2.57389, 1.94322, 1.78515, 2.09265, 2.37459, 1.74442, 1.74346, 1.19705, 1.56149, 1.59604, 1.6, 1,1,1,1,1,1,1}, {0.93374, 1.40389, 1.36670, 1.38679, 1.35707, 1.26353, 1.32360, 1.40164, 1.51843, 1.34863, 3.45839, 3.13726, 3.94768, 4.21966, 4.60750, 4.97894, 5.40755, 8.12814, 10.59221, 12.96427, 13.37323, 14.27206, 16.61779, 17.19656}};
+double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.16829, 1.11186, 1.06287, 1.07292, 1.09946, 1.10650, 2.79174, 2.75655, 3.36651, 3.49011, 3.60903, 2.73517, 3.84009, 8.20312, 7.41739, 9.64081, 10.40911, 8.11765, 10.41923, 9.34300}, {0.67252, 0.8600, 1.28633, 1.01624, 1.03066, 0.97590, 1.02560, 1.01840, 1.00547, 0.97093, 2.72573, 2.33283, 2.86181, 3.40452, 3.47957, 4.08916, 3.97628, 6.14541, 7.11017, 8.42369, 4.04812, 11.42082, 11.57171, 9.28462}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.85784, 0.90361, 2.09766, 1.08385, 0.96300, 1.04432, 1.22763, 0.99249, 0.95544, 1.12333, 1.37924, 1.12913, 1.30644, 1.19253, 1.75488, 2.13813, 2.10636, 1,1,1,1,1,1,1}, {0.66288, 0.96402, 0.98545, 0.99386, 0.99981, 0.92678, 0.98978, 0.99600, 1.05538, 0.97777, 2.52504, 2.29338, 2.89631, 3.10812, 3.41916, 3.58671, 3.84166, 6.05254, 7.45821, 9.15812, 9.66330, 10.17852, 11.50519, 11.16299}};
+
+*/
+
+#ifdef OCP_FRAMEWORK
+#include <enums.h>
+#else
+char eNB_functions[6][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5",};
+char eNB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
+char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
+#endif
+
+/// lookup table for unscrambling in RX
+int16_t unscrambling_lut[65536*16] __attribute__((aligned(32)));
+/// lookup table for scrambling in TX
+uint8_t scrambling_lut[65536*16] __attribute__((aligned(32)));
+
+uint8_t max_turbo_iterations=4;
+#endif /*__PHY_VARS_H__ */

openair1/SCHED/sched_common.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*
+  \author R. Knopp, F. Kaltenberger
+  \company EURECOM
+  \email knopp@eurecom.fr
+*/
+
+#ifndef __openair_SCHED_COMMON_H__
+#define __openair_SCHED_COMMON_H__
+
+#include "PHY/defs_eNB.h"
+#include "PHY/defs_UE.h"
+
+/*! \brief Function to compute subframe Number(DL and S) as a function of Frame type and TDD Configuration
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @returns Subframe Number (DL,S)
+*/
+int subframe_num(LTE_DL_FRAME_PARMS *frame_parms);
+
+/*! \brief Function to compute subframe type as a function of Frame type and TDD Configuration (implements Table 4.2.2 from 36.211, p.11 from version 8.6) and subframe index.
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe index
+  @returns Subframe type (DL,UL,S)
+*/
+
+
+lte_subframe_t subframe_select(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+
+/*! \brief Function to compute which type of DCIs to detect in the given subframe
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe index
+  @returns DCI detetion mode type (no DCIs, uplink DCIs, downlink DCIs, both uplink and downlink DCIs)
+ */
+dci_detect_mode_t dci_detect_mode_select(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+
+
+
+/*! \brief Function to indicate PHICH transmission subframes.  Implements Table 9.1.2-1 for TDD.
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe index
+  @returns 1 if PHICH can be transmitted in subframe (always 1 for FDD)
+*/
+uint32_t is_phich_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
+
+/*! \brief Function to compute timing of Msg3 transmission on UL-SCH (first UE transmission in RA procedure). This implements the timing in paragraph a) from Section 6.1.1 in 36.213 (p. 17 in version 8.6).  Used by eNB upon transmission of random-access response (RA_RNTI) to program corresponding ULSCH reception procedure.  Used by UE upon reception of random-access response (RA_RNTI) to program corresponding ULSCH transmission procedure.  This does not support the UL_delay field in RAR (always assumed to be 0).
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param current_subframe Index of subframe where RA_RNTI was received
+  @param current_frame Index of frame where RA_RNTI was received
+  @param frame Frame index where Msg3 is to be transmitted (n+6 mod 10 for FDD, different for TDD)
+  @param subframe subframe index where Msg3 is to be transmitted (n, n+1 or n+2)
+*/
+void get_Msg3_alloc(LTE_DL_FRAME_PARMS *frame_parms,
+                    uint8_t current_subframe,
+                    uint32_t current_frame,
+                    uint32_t *frame,
+                    uint8_t *subframe);
+
+/*! \brief Function to compute timing of Msg3 retransmission on UL-SCH (first UE transmission in RA procedure).
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param current_subframe Index of subframe where RA_RNTI was received
+  @param current_frame Index of frame where RA_RNTI was received
+  @param frame Frame index where Msg3 is to be transmitted (n+6 mod 10 for FDD, different for TDD)
+  @param subframe subframe index where Msg3 is to be transmitted (n, n+1 or n+2)
+*/
+void get_Msg3_alloc_ret(LTE_DL_FRAME_PARMS *frame_parms,
+                        uint8_t current_subframe,
+                        uint32_t current_frame,
+                        uint32_t *frame,
+                        uint8_t *subframe);
+
+/*! \brief Get ULSCH harq_pid for Msg3 from RAR subframe.  This returns n+k mod 10 (k>6) and corresponds to the rule in Section 6.1.1 from 36.213
+   @param frame_parms Pointer to DL Frame Parameters
+   @param frame Frame index
+   @param current_subframe subframe of RAR transmission
+   @returns harq_pid (0 ... 7)
+ */
+uint8_t get_Msg3_harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t current_subframe);
+
+/*! \brief Get ULSCH harq_pid from PHICH subframe
+   @param frame_parms Pointer to DL Frame Parameters
+   @param subframe subframe of PHICH
+   @returns harq_pid (0 ... 7)
+ */
+
+/*! \brief Function to indicate failure of contention resolution or RA procedure.  It places the UE back in PRACH mode.
+    @param Mod_id Instance index of UE
+    @param CC_id Component Carrier Index
+    @param eNB_index Index of eNB
+ */
+void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief Function to indicate success of contention resolution or RA procedure.
+    @param Mod_id Instance index of UE
+    @param CC_id Component Carrier Index
+    @param eNB_index Index of eNB
+ */
+void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+uint8_t phich_subframe_to_harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t subframe);
+
+/*! \brief Get PDSCH subframe (n+k) from PDCCH subframe n using relationship from Table 8-2 from 36.213
+   @param frame_parms Pointer to DL Frame Parameters
+   @param n subframe of PDCCH
+   @returns PDSCH subframe (0 ... 7) (note: this is n+k from Table 8-2)
+ */
+uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n);
+
+
+/*! \brief Compute ACK/NACK information for PUSCH/PUCCH for UE transmission in subframe n. This function implements table 10.1-1 of 36.213, p. 69.
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param o_ACK Pointer to ACK/NAK payload for PUCCH/PUSCH
+  @returns status indicator for PUCCH/PUSCH transmission
+*/
+uint8_t get_ack(LTE_DL_FRAME_PARMS *frame_parms,harq_status_t *harq_ack,uint8_t subframe_tx,uint8_t subframe_rx,uint8_t *o_ACK, uint8_t cw_idx);
+
+/*! \brief Reset ACK/NACK information
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param o_ACK Pointer to ACK/NAK payload for PUCCH/PUSCH
+  @returns status indicator for PUCCH/PUSCH transmission
+*/
+uint8_t reset_ack(LTE_DL_FRAME_PARMS *frame_parms,
+                harq_status_t *harq_ack,
+                unsigned char subframe_tx,
+                unsigned char subframe_rx,
+                unsigned char *o_ACK,
+                uint8_t *pN_bundled,
+                uint8_t cw_idx);
+
+/*! \brief Compute UL ACK subframe from DL subframe. This is used to retrieve corresponding DLSCH HARQ pid at eNB upon reception of ACK/NAK information on PUCCH/PUSCH.  Derived from Table 10.1-1 in 36.213 (p. 69 in version 8.6)
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param ACK_index TTI bundling index (0,1)
+  @returns Subframe index for corresponding DL transmission
+*/
+uint8_t ul_ACK_subframe2_dl_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe,uint8_t ACK_index);
+
+/*! \brief Computes number of DL subframes represented by a particular ACK received on UL (M from Table 10.1-1 in 36.213, p. 69 in version 8.6)
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @returns Number of DL subframes (M)
+*/
+uint8_t ul_ACK_subframe2_M(LTE_DL_FRAME_PARMS *frame_parms,unsigned char subframe);
+
+/*! \brief Indicates the SR TXOp in current subframe.  Implements Table 10.1-5 from 36.213.
+  @param phy_vars_ue Pointer to UE variables
+  @param proc Pointer to RXn_TXnp4 thread context
+  @param eNB_id ID of eNB which is to receive the SR
+  @returns 1 if TXOp is active.
+*/
+uint8_t is_SR_TXOp(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id);
+
+/*! \brief Indicates the SR TXOp in current subframe for eNB and particular UE index.  Implements Table 10.1-5 from 36.213.
+  @param phy_vars_eNB Pointer to eNB variables
+  @param UE_id ID of UE which may be issuing the SR
+  @returns 1 if TXOp is active.
+*/
+uint8_t is_SR_subframe(PHY_VARS_eNB *phy_vars_eNB,eNB_rxtx_proc_t *proc,uint8_t UE_id);
+
+/*! \brief Gives the UL subframe corresponding to a PDDCH order in subframe n
+  @param frame_parms Pointer to DL frame parameters
+  @param proc Pointer to RXn-TXnp4 proc information
+  @param n subframe of PDCCH
+  @returns UL subframe corresponding to pdcch order
+*/
+uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n);
+
+/*! \brief Gives the UL frame corresponding to a PDDCH order in subframe n
+  @param frame_parms Pointer to DL frame parameters
+  @param frame Frame of received PDCCH
+  @param n subframe of PDCCH
+  @returns UL frame corresponding to pdcch order
+*/
+uint32_t pdcch_alloc2ul_frame(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t n);
+
+
+uint16_t get_Np(uint8_t N_RB_DL,uint8_t nCCE,uint8_t plus1);
+
+
+int8_t find_ue_dlsch(uint16_t rnti, PHY_VARS_eNB *phy_vars_eNB);
+int8_t find_ue_ulsch(uint16_t rnti, PHY_VARS_eNB *phy_vars_eNB);
+
+//int32_t add_ue(int16_t rnti, PHY_VARS_eNB *phy_vars_eNB);
+//int mac_phy_remove_ue(module_id_t Mod_idP,rnti_t rnti);
+
+void process_timing_advance(module_id_t Mod_id,uint8_t CC_id,int16_t timing_advance);
+void process_timing_advance_rar(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint16_t timing_advance);
+
+unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb);
+
+void phy_reset_ue(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief This function retrives the resource (n1_pucch) corresponding to a PDSCH transmission in
+subframe n-4 which is acknowledged in subframe n (for FDD) according to n1_pucch = Ncce + N1_pucch.  For
+TDD, this routine computes the complex procedure described in Section 10.1 of 36.213 (through tables 10.1-1,10.1-2)
+@param phy_vars_ue Pointer to UE variables
+@param proc Pointer to RXn-TXnp4 proc information
+@param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+@param eNB_id Index of eNB
+@param b Pointer to PUCCH payload (b[0],b[1])
+@param SR 1 means there's a positive SR in parallel to ACK/NAK
+@returns n1_pucch
+*/
+uint16_t get_n1_pucch(PHY_VARS_UE *phy_vars_ue,
+		      UE_rxtx_proc_t *proc,
+                      harq_status_t *harq_ack,
+                      uint8_t eNB_id,
+                      uint8_t *b,
+                      uint8_t SR);
+
+/*! \brief This function retrives the resource (n1_pucch) corresponding to a PDSCH transmission in
+subframe n-4 which is acknowledged in subframe n (for FDD) according to n1_pucch = Ncce + N1_pucch.  For
+TDD, this routine computes the procedure described in Section 10.1 of 36.213 (through tables 10.1-1,10.1-2)
+@param phy_vars_eNB Pointer to eNB variables
+@param proc Pointer to RXn-TXnp4 proc information
+@param eNB_id Index of eNB
+@param subframe Index of subframe
+@param b Pointer to PUCCH payload (b[0],b[1])
+@param n1_pucch0 Pointer to n1_pucch0
+@param n1_pucch1 Pointer to n1_pucch1
+@param n1_pucch2 Pointer to n1_pucch2
+@param n1_pucch3 Pointer to n1_pucch3
+*/
+void get_n1_pucch_eNB(PHY_VARS_eNB *phy_vars_eNB,
+		      eNB_rxtx_proc_t *proc,
+                      uint8_t UE_id,
+                      int16_t *n1_pucch0,
+                      int16_t *n1_pucch1,
+                      int16_t *n1_pucch2,
+                      int16_t *n1_pucch3);
+
+
+/*! \brief This function retrieves the harq_pid of the corresponding DLSCH process and updates the error statistics of the DLSCH based on the received ACK info from UE along with the round index.  It also performs the fine-grain rate-adaptation based on the error statistics derived from the ACK/NAK process.
+  @param UE_id Local UE index on which to act
+  @param phy_vars_eNB Pointer to eNB variables on which to act
+  @param proc Pointer to RXn-TXnp4 proc information
+  @param pusch_flag Indication that feedback came from PUSCH
+  @param pucch_payload Resulting payload from pucch
+  @param pucch_sel Selection of n1_pucch0 or n1_pucch1 (TDD specific)
+  @param SR_payload Indication of SR presence (TDD specific)
+*/
+void process_HARQ_feedback(uint8_t UE_id,
+                           PHY_VARS_eNB *phy_vars_eNB,
+			   eNB_rxtx_proc_t *proc,
+                           uint8_t pusch_flag,
+                           uint8_t *pucch_payload,
+                           uint8_t pucch_sel,
+                           uint8_t SR_payload);
+
+/*! \brief This function retrieves the PHY UE mode. It is used as a helper function for the UE MAC.
+  @param Mod_id Local UE index on which to act
+  @param CC_id Component Carrier Index
+  @param eNB_index ID of eNB
+  @returns UE mode
+*/
+UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief This function implements the power control mechanism for PUCCH from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param pucch_fmt Format of PUCCH that is being transmitted
+    @returns Transmit power
+ */
+int16_t pucch_power_cntl(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t subframe,uint8_t eNB_id,PUCCH_FMT_t pucch_fmt);
+
+/*! \brief This function implements the power control mechanism for PUCCH from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param j index of type of PUSCH (SPS, Normal, Msg3)
+    @returns Transmit power
+ */
+void pusch_power_cntl(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t j, uint8_t abstraction_flag);
+
+/*! \brief This function implements the power control mechanism for SRS from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param j index of type of PUSCH (SPS, Normal, Msg3)
+    @returns Transmit power
+ */
+void srs_power_cntl(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t *pnb_rb_srs, uint8_t abstraction_flag);
+
+void get_cqipmiri_params(PHY_VARS_UE *ue,uint8_t eNB_id);
+
+int8_t get_PHR(uint8_t Mod_id, uint8_t CC_id, uint8_t eNB_index);
+
+void schedule_response(Sched_Rsp_t *Sched_INFO);
+
+LTE_eNB_UE_stats* get_UE_stats(uint8_t Mod_id, uint8_t CC_id,uint16_t rnti);
+
+
+
+LTE_DL_FRAME_PARMS *get_lte_frame_parms(module_id_t Mod_id, uint8_t CC_id);
+
+MU_MIMO_mode* get_mu_mimo_mode (module_id_t Mod_id, uint8_t CC_id, rnti_t rnti);
+
+int16_t get_hundred_times_delta_IF(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t harq_pid);
+
+int16_t get_hundred_times_delta_IF_eNB(PHY_VARS_eNB *phy_vars_eNB,uint8_t UE_id,uint8_t harq_pid, uint8_t bw_factor);
+
+int16_t get_hundred_times_delta_IF_mac(module_id_t module_idP, uint8_t CC_id, rnti_t rnti, uint8_t harq_pid);
+
+int16_t get_target_pusch_rx_power(module_id_t module_idP, uint8_t CC_id);
+int16_t get_target_pucch_rx_power(module_id_t module_idP, uint8_t CC_id);
+
+int get_ue_active_harq_pid(uint8_t Mod_id,uint8_t CC_id,uint16_t rnti,int frame, uint8_t subframe,uint8_t *harq_pid,uint8_t *round,uint8_t ul_flag);
+
+void dump_dlsch(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe,uint8_t harq_pid);
+void dump_dlsch_SI(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe);
+void dump_dlsch_ra(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe);
+
+void dump_dlsch2(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe, unsigned int *coded_bits_per_codeword,int round, unsigned char harq_pid);
+
+
+int is_srs_occasion_common(LTE_DL_FRAME_PARMS *frame_parms,int frame_tx,int subframe_tx);
+
+void compute_srs_pos(lte_frame_type_t frameType,uint16_t isrs,uint16_t *psrsPeriodicity,uint16_t *psrsOffset);
+
+/*@}*/
+
+
+#endif
+
+

openair1/SCHED_UE/sched_UE.h

+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+/*
+  \author R. Knopp, F. Kaltenberger
+  \company EURECOM
+  \email knopp@eurecom.fr
+*/
+
+#ifndef __openair_SCHED_ENB_H__
+#define __openair_SCHED_ENB_H__
+
+#include "PHY/defs_UE.h"
+
+/*! \brief Scheduling for UE TX procedures in normal subframes.
+  @param phy_vars_ue Pointer to UE variables on which to act
+  @param proc Pointer to RXn-TXnp4 proc information
+  @param eNB_id Local id of eNB on which to act
+  @param abstraction_flag Indicator of PHY abstraction
+  @param mode calib/normal mode
+  @param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
+*/
+void phy_procedures_UE_TX(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode);
+/*! \brief Scheduling for UE RX procedures in normal subframes.
+  @param last_slot Index of last slot (0-19)
+  @param phy_vars_ue Pointer to UE variables on which to act
+  @param proc Pointer to RXn_TXnp4 proc information
+  @param eNB_id Local id of eNB on which to act
+  @param abstraction_flag Indicator of PHY abstraction
+  @param mode calibration/debug mode
+  @param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
+  @param phy_vars_rn pointer to RN variables
+*/
+int phy_procedures_UE_RX(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode);
+int phy_procedures_slot_parallelization_UE_RX(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,
+                                              uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode);
+#ifdef UE_SLOT_PARALLELISATION
+void *UE_thread_slot1_dl_processing(void *arg);
+#endif
+
+/*! \brief Scheduling for UE TX procedures in TDD S-subframes.
+  @param phy_vars_ue Pointer to UE variables on which to act
+  @param eNB_id Local id of eNB on which to act
+  @param abstraction_flag Indicator of PHY abstraction
+  @param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
+*/
+void phy_procedures_UE_S_TX(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t abstraction_flag);
+
+/*! \brief Scheduling for UE RX procedures in TDD S-subframes.
+  @param phy_vars_ue Pointer to UE variables on which to act
+  @param eNB_id Local id of eNB on which to act
+  @param abstraction_flag Indicator of PHY abstraction
+  @param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
+*/
+void phy_procedures_UE_S_RX(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t abstraction_flag);
+
+/*! \brief Get ULSCH harq_pid for Msg3 from RAR subframe.  This returns n+k mod 10 (k>6) and corresponds to the rule in Section 6.1.1 from 36.213
+   @param frame_parms Pointer to DL Frame Parameters
+   @param frame Frame index
+   @param current_subframe subframe of RAR transmission
+   @returns harq_pid (0 ... 7)
+ */
+uint8_t get_Msg3_harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t current_subframe);
+
+/*! \brief Get ULSCH harq_pid from PHICH subframe
+   @param frame_parms Pointer to DL Frame Parameters
+   @param subframe subframe of PHICH
+   @returns harq_pid (0 ... 7)
+ */
+
+/*! \brief Function to indicate failure of contention resolution or RA procedure.  It places the UE back in PRACH mode.
+    @param Mod_id Instance index of UE
+    @param CC_id Component Carrier Index
+    @param eNB_index Index of eNB
+ */
+void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief Function to indicate success of contention resolution or RA procedure.
+    @param Mod_id Instance index of UE
+    @param CC_id Component Carrier Index
+    @param eNB_index Index of eNB
+ */
+void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+uint8_t phich_subframe_to_harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t subframe);
+
+/*! \brief Get PDSCH subframe (n+k) from PDCCH subframe n using relationship from Table 8-2 from 36.213
+   @param frame_parms Pointer to DL Frame Parameters
+   @param n subframe of PDCCH
+   @returns PDSCH subframe (0 ... 7) (note: this is n+k from Table 8-2)
+ */
+uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n);
+
+
+/*! \brief Compute ACK/NACK information for PUSCH/PUCCH for UE transmission in subframe n. This function implements table 10.1-1 of 36.213, p. 69.
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param o_ACK Pointer to ACK/NAK payload for PUCCH/PUSCH
+  @returns status indicator for PUCCH/PUSCH transmission
+*/
+uint8_t get_ack(LTE_DL_FRAME_PARMS *frame_parms,harq_status_t *harq_ack,uint8_t subframe_tx,uint8_t subframe_rx,uint8_t *o_ACK, uint8_t cw_idx);
+
+/*! \brief Reset ACK/NACK information
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param o_ACK Pointer to ACK/NAK payload for PUCCH/PUSCH
+  @returns status indicator for PUCCH/PUSCH transmission
+*/
+uint8_t reset_ack(LTE_DL_FRAME_PARMS *frame_parms,
+                harq_status_t *harq_ack,
+                unsigned char subframe_tx,
+                unsigned char subframe_rx,
+                unsigned char *o_ACK,
+                uint8_t *pN_bundled,
+                uint8_t cw_idx);
+
+/*! \brief Compute UL ACK subframe from DL subframe. This is used to retrieve corresponding DLSCH HARQ pid at eNB upon reception of ACK/NAK information on PUCCH/PUSCH.  Derived from Table 10.1-1 in 36.213 (p. 69 in version 8.6)
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @param ACK_index TTI bundling index (0,1)
+  @returns Subframe index for corresponding DL transmission
+*/
+uint8_t ul_ACK_subframe2_dl_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe,uint8_t ACK_index);
+
+/*! \brief Computes number of DL subframes represented by a particular ACK received on UL (M from Table 10.1-1 in 36.213, p. 69 in version 8.6)
+  @param frame_parms Pointer to DL frame parameter descriptor
+  @param subframe Subframe for UE transmission (n in 36.213)
+  @returns Number of DL subframes (M)
+*/
+uint8_t ul_ACK_subframe2_M(LTE_DL_FRAME_PARMS *frame_parms,unsigned char subframe);
+
+/*! \brief Indicates the SR TXOp in current subframe.  Implements Table 10.1-5 from 36.213.
+  @param phy_vars_ue Pointer to UE variables
+  @param proc Pointer to RXn_TXnp4 thread context
+  @param eNB_id ID of eNB which is to receive the SR
+  @returns 1 if TXOp is active.
+*/
+uint8_t is_SR_TXOp(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id);
+
+uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n);
+
+/*! \brief Gives the UL frame corresponding to a PDDCH order in subframe n
+  @param frame_parms Pointer to DL frame parameters
+  @param frame Frame of received PDCCH
+  @param n subframe of PDCCH
+  @returns UL frame corresponding to pdcch order
+*/
+uint32_t pdcch_alloc2ul_frame(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t n);
+
+
+uint16_t get_Np(uint8_t N_RB_DL,uint8_t nCCE,uint8_t plus1);
+
+
+
+void process_timing_advance(module_id_t Mod_id,uint8_t CC_id,int16_t timing_advance);
+void process_timing_advance_rar(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint16_t timing_advance);
+
+unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb);
+
+void phy_reset_ue(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief This function retrives the resource (n1_pucch) corresponding to a PDSCH transmission in
+subframe n-4 which is acknowledged in subframe n (for FDD) according to n1_pucch = Ncce + N1_pucch.  For
+TDD, this routine computes the complex procedure described in Section 10.1 of 36.213 (through tables 10.1-1,10.1-2)
+@param phy_vars_ue Pointer to UE variables
+@param proc Pointer to RXn-TXnp4 proc information
+@param harq_ack Pointer to dlsch_ue harq_ack status descriptor
+@param eNB_id Index of eNB
+@param b Pointer to PUCCH payload (b[0],b[1])
+@param SR 1 means there's a positive SR in parallel to ACK/NAK
+@returns n1_pucch
+*/
+uint16_t get_n1_pucch(PHY_VARS_UE *phy_vars_ue,
+		      UE_rxtx_proc_t *proc,
+                      harq_status_t *harq_ack,
+                      uint8_t eNB_id,
+                      uint8_t *b,
+                      uint8_t SR);
+
+
+
+
+/*! \brief This function retrieves the PHY UE mode. It is used as a helper function for the UE MAC.
+  @param Mod_id Local UE index on which to act
+  @param CC_id Component Carrier Index
+  @param eNB_index ID of eNB
+  @returns UE mode
+*/
+UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+
+/*! \brief This function implements the power control mechanism for PUCCH from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param pucch_fmt Format of PUCCH that is being transmitted
+    @returns Transmit power
+ */
+int16_t pucch_power_cntl(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t subframe,uint8_t eNB_id,PUCCH_FMT_t pucch_fmt);
+
+/*! \brief This function implements the power control mechanism for PUCCH from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param j index of type of PUSCH (SPS, Normal, Msg3)
+    @returns Transmit power
+ */
+void pusch_power_cntl(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t j, uint8_t abstraction_flag);
+
+/*! \brief This function implements the power control mechanism for SRS from 36.213.
+    @param phy_vars_ue PHY variables
+    @param proc Pointer to proc descriptor
+    @param eNB_id Index of eNB
+    @param j index of type of PUSCH (SPS, Normal, Msg3)
+    @returns Transmit power
+ */
+void srs_power_cntl(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t *pnb_rb_srs, uint8_t abstraction_flag);
+
+void get_cqipmiri_params(PHY_VARS_UE *ue,uint8_t eNB_id);
+
+int8_t get_PHR(uint8_t Mod_id, uint8_t CC_id, uint8_t eNB_index);
+
+
+
+LTE_DL_FRAME_PARMS *get_lte_frame_parms(module_id_t Mod_id, uint8_t CC_id);
+
+MU_MIMO_mode* get_mu_mimo_mode (module_id_t Mod_id, uint8_t CC_id, rnti_t rnti);
+
+int16_t get_hundred_times_delta_IF(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t harq_pid);
+
+
+int16_t get_hundred_times_delta_IF_mac(module_id_t module_idP, uint8_t CC_id, rnti_t rnti, uint8_t harq_pid);
+
+int16_t get_target_pusch_rx_power(module_id_t module_idP, uint8_t CC_id);
+int16_t get_target_pucch_rx_power(module_id_t module_idP, uint8_t CC_id);
+
+int get_ue_active_harq_pid(uint8_t Mod_id,uint8_t CC_id,uint16_t rnti,int frame, uint8_t subframe,uint8_t *harq_pid,uint8_t *round,uint8_t ul_flag);
+
+void dump_dlsch(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe,uint8_t harq_pid);
+void dump_dlsch_SI(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe);
+void dump_dlsch_ra(PHY_VARS_UE *phy_vars_ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t subframe);
+
+void dump_dlsch2(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe, unsigned int *coded_bits_per_codeword,int round, unsigned char harq_pid);
+
+
+int is_srs_occasion_common(LTE_DL_FRAME_PARMS *frame_parms,int frame_tx,int subframe_tx);
+
+void compute_srs_pos(lte_frame_type_t frameType,uint16_t isrs,uint16_t *psrsPeriodicity,uint16_t *psrsOffset);
+
+/*@}*/
+
+
+#endif
+
+

openair2/LAYER2/MAC/l1_helpers.c

@@ -54,6 +54,52 @@ int8_t get_Po_NOMINAL_PUSCH(module_id_t module_idP, uint8_t CC_id)
 	     1) + get_DELTA_PREAMBLE(module_idP, CC_id));
 }
 
+int8_t get_DELTA_PREAMBLE(module_id_t module_idP, int CC_id)
+{
+
+    AssertFatal(CC_id == 0,
+		"Transmission on secondary CCs is not supported yet\n");
+    uint8_t prachConfigIndex =
+	UE_mac_inst[module_idP].radioResourceConfigCommon->
+	prach_Config.prach_ConfigInfo.prach_ConfigIndex;
+    uint8_t preambleformat;
+
+    if (UE_mac_inst[module_idP].tdd_Config) {	// TDD
+	if (prachConfigIndex < 20) {
+	    preambleformat = 0;
+	} else if (prachConfigIndex < 30) {
+	    preambleformat = 1;
+	} else if (prachConfigIndex < 40) {
+	    preambleformat = 2;
+	} else if (prachConfigIndex < 48) {
+	    preambleformat = 3;
+	} else {
+	    preambleformat = 4;
+	}
+    } else {			// FDD
+	preambleformat = prachConfigIndex >> 2;
+    }
+
+    switch (preambleformat) {
+    case 0:
+    case 1:
+	return (0);
+
+    case 2:
+    case 3:
+	return (-3);
+
+    case 4:
+	return (8);
+
+    default:
+	AssertFatal(1 == 0,
+		    "[UE %d] ue_procedures.c: FATAL, Illegal preambleformat %d, prachConfigIndex %d\n",
+		    module_idP, preambleformat, prachConfigIndex);
+    }
+
+}
+
 int8_t get_deltaP_rampup(module_id_t module_idP, uint8_t CC_id)
 {
 

openair2/LAYER2/MAC/ra_procedures.c

@@ -49,53 +49,6 @@
 
 #include "SIMULATION/TOOLS/defs.h"	// for taus
 
-int8_t get_DELTA_PREAMBLE(module_id_t module_idP, int CC_id)
-{
-
-    AssertFatal(CC_id == 0,
-		"Transmission on secondary CCs is not supported yet\n");
-    uint8_t prachConfigIndex =
-	UE_mac_inst[module_idP].radioResourceConfigCommon->
-	prach_Config.prach_ConfigInfo.prach_ConfigIndex;
-    uint8_t preambleformat;
-
-    if (UE_mac_inst[module_idP].tdd_Config) {	// TDD
-	if (prachConfigIndex < 20) {
-	    preambleformat = 0;
-	} else if (prachConfigIndex < 30) {
-	    preambleformat = 1;
-	} else if (prachConfigIndex < 40) {
-	    preambleformat = 2;
-	} else if (prachConfigIndex < 48) {
-	    preambleformat = 3;
-	} else {
-	    preambleformat = 4;
-	}
-    } else {			// FDD
-	preambleformat = prachConfigIndex >> 2;
-    }
-
-    switch (preambleformat) {
-    case 0:
-    case 1:
-	return (0);
-
-    case 2:
-    case 3:
-	return (-3);
-
-    case 4:
-	return (8);
-
-    default:
-	AssertFatal(1 == 0,
-		    "[UE %d] ue_procedures.c: FATAL, Illegal preambleformat %d, prachConfigIndex %d\n",
-		    module_idP, preambleformat, prachConfigIndex);
-    }
-
-}
-
-
 /// This routine implements Section 5.1.2 (UE Random Access Resource Selection) from 36.321
 void
 get_prach_resources(module_id_t module_idP,

targets/RT/USER/lte-softmodem.h

@@ -130,10 +130,11 @@
 {"ue-scan-carrier",  	       CONFIG_HLP_UESCAN,     PARAMFLAG_BOOL,	iptr:&UE_scan_carrier,  	    defintval:0,    TYPE_INT,	   0},     \
 {"ue-max-power",     	       NULL,		      0,		iptr:&(tx_max_power[0]),	    defintval:90,   TYPE_INT,	   0},     \
 {"r"  ,                        CONFIG_HLP_PRB,        0,                u8ptr:&(frame_parms[0]->N_RB_DL),   defintval:25,   TYPE_UINT8,    0},     \
+{"dlsch-demod-shift",     	 CONFIG_HLP_DLSHIFT,	0,		  iptr:(int32_t *)&dlsch_demod_shift,	defintval:0,			   TYPE_INT,	  0},			   \
 }
 
 #define DEFAULT_DLF 2680000000
-extern int16_t dlsch_demod_shift;
+
 /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
 /*                                            command line parameters common to eNodeB and UE                                                                                */
 /*   optname                     helpstr                paramflags                      XXXptr                  defXXXval                            type           numelt   */
@@ -153,7 +154,6 @@ extern int16_t dlsch_demod_shift;
 {"threadThreeSubframe",    	 NULL,  		0,		  iptr:&(threads.three),  		defintval:1,			   TYPE_INT,	  0},			   \
 {"threadSlot1ProcOne",     	 NULL,  		0,		  iptr:&(threads.slot1_proc_one),      	defintval:1,			   TYPE_INT,	  0},			   \
 {"threadSlot1ProcTwo",    	 NULL,  		0,		  iptr:&(threads.slot1_proc_two),      	defintval:1,			   TYPE_INT,	  0},			   \
-{"dlsch-demod-shift",     	 CONFIG_HLP_DLSHIFT,	0,		  iptr:(int32_t *)&dlsch_demod_shift,	defintval:0,			   TYPE_INT,	  0},			   \
 {"A" ,  		  	 CONFIG_HLP_TADV,	0,		  uptr:&timing_advance, 		defintval:0,			   TYPE_UINT,	  0},			   \
 {"C" ,  		  	 CONFIG_HLP_DLF,	0,		  uptr:&(downlink_frequency[0][0]),	defuintval:DEFAULT_DLF,  	   TYPE_UINT,	  0},			   \
 {"a" ,  		  	 CONFIG_HLP_CHOFF,	0,		  iptr:&chain_offset,			defintval:0,			   TYPE_INT,	  0},			   \

targets/RT/USER/lte-uesoftmodem.c

@@ -455,6 +455,7 @@ void *l2l1_task(void *arg) {
 }
 #endif
 
+extern int16_t dlsch_demod_shift;
 
 static void get_options(void) {
   int CC_id;