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Commit d75dc39a authored by Raymond Knopp's avatar Raymond Knopp
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removal of more compilation warnings

parent 293bcf13
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Showing with 45 additions and 2022 deletions
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @ d75dc39a
......@@ -857,7 +857,7 @@ uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti)
}
*/
int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_alloc,nfapi_dl_config_dci_dl_pdu *pdu) {
void fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_alloc,nfapi_dl_config_dci_dl_pdu *pdu) {
LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
......@@ -1170,10 +1170,8 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
break;
}
if (rel8->harq_process>=8) {
LOG_E(PHY,"ERROR: Format 1: harq_pid=%d >= 8\n", rel8->harq_process);
return(-1);
}
AssertFatal(rel8->harq_process<8,"Format 1: harq_pid=%d >= 8\n", rel8->harq_process);
dlsch0_harq = dlsch0->harq_processes[rel8->harq_process];
dlsch0_harq->codeword=0;
......@@ -1193,9 +1191,7 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
NPRB = dlsch0_harq->nb_rb;
if (NPRB==0)
return(-1);
AssertFatal(NPRB>0,"NPRB == 0\n");
dlsch0_harq->rvidx = rel8->redundancy_version_1;
......@@ -1365,10 +1361,8 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
break;
}
if (rel8->harq_process>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
return(-1);
}
AssertFatal(rel8->harq_process<8,"Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
......@@ -1400,8 +1394,7 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
fp->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
if (dlsch0_harq->nb_rb == 0)
return(-1);
AssertFatal(dlsch0_harq->nb_rb > 0,"nb_rb=0\n");
dlsch0_harq->mcs = rel8->mcs_1;
dlsch1_harq->mcs = rel8->mcs_2;
......@@ -1685,10 +1678,7 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
}
if (rel8->harq_process>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
return(-1);
}
AssertFatal(rel8->harq_process>=8, "Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
......@@ -1811,10 +1801,6 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
}
/*if (dlsch0_harq->nb_rb == 0)
return(-1);*/
// assume both TBs are active
if (dlsch0_harq != NULL)
dlsch0_harq->Nl = 1;
......@@ -1993,14 +1979,14 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
}
int fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *dci_alloc,nfapi_dl_config_mpdcch_pdu *pdu) {
void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *dci_alloc,nfapi_dl_config_mpdcch_pdu *pdu) {
LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
uint8_t *dci_pdu = &dci_alloc->dci_pdu[0];
nfapi_dl_config_mpdcch_pdu_rel13_t *rel13 = &pdu->mpdcch_pdu_rel13;
int harq_pid;
LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
LTE_eNB_DLSCH_t *dlsch0=NULL;
LTE_DL_eNB_HARQ_t *dlsch0_harq=NULL;
int UE_id;
int subframe = proc->subframe_tx;
......@@ -2470,1932 +2456,6 @@ void fill_ulsch(PHY_VARS_eNB *eNB,nfapi_ul_config_ulsch_pdu *ulsch_pdu,int frame
}
int generate_eNB_dlsch_params_from_dci(int frame,
uint8_t subframe,
void *dci_pdu,
uint16_t rnti,
DCI_format_t dci_format,
LTE_eNB_DLSCH_t **dlsch,
LTE_DL_FRAME_PARMS *fp,
PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
uint16_t si_rnti,
uint16_t ra_rnti,
uint16_t p_rnti,
uint16_t DL_pmi_single,
uint8_t beamforming_mode)
{
uint8_t harq_pid = UINT8_MAX;
uint32_t rballoc = UINT32_MAX;
uint32_t RIV_max = 0;
uint8_t NPRB,tbswap,tpmi=0;
LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
uint8_t frame_type=fp->frame_type;
uint8_t vrb_type=0;
uint8_t mcs=0,mcs1=0,mcs2=0;
uint8_t I_mcs = 0;
uint8_t rv=0,rv1=0,rv2=0;
uint8_t rah=0;
uint8_t TPC=0;
uint8_t TB0_active=0,TB1_active=0;
LTE_DL_eNB_HARQ_t *dlsch0_harq=NULL,*dlsch1_harq=NULL;
// printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);
switch (dci_format) {
case format0:
return(-1);
break;
case format1A: // This is DLSCH allocation for control traffic
dlsch[0]->subframe_tx[subframe] = 1;
switch (fp->N_RB_DL) {
case 6:
if (frame_type == TDD) {
vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->codeword=0;
AssertFatal(vrb_type==LOCALIZED,"Distributed RB allocation not done yet\n");
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT6[rballoc];
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT6[rballoc];//NPRB;
RIV_max = RIV_max6;
break;
case 25:
if (frame_type == TDD) {
vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
AssertFatal(vrb_type==LOCALIZED,"Distributed RB allocation not done yet\n");
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT25[rballoc];
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT25[rballoc];//NPRB;
RIV_max = RIV_max25;
break;
case 50:
if (frame_type == TDD) {
vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
//printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
AssertFatal(vrb_type==LOCALIZED,"Distributed RB allocation not done yet\n");
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT50_0[rballoc];
dlsch0_harq->rb_alloc[1] = localRIV2alloc_LUT50_1[rballoc];
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT50[rballoc];//NPRB;
RIV_max = RIV_max50;
break;
case 100:
if (frame_type == TDD) {
vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->vrb_type = vrb_type;
AssertFatal(vrb_type==LOCALIZED,"Distributed RB allocation not done yet\n");
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT100_0[rballoc];
dlsch0_harq->rb_alloc[1] = localRIV2alloc_LUT100_1[rballoc];
dlsch0_harq->rb_alloc[2] = localRIV2alloc_LUT100_2[rballoc];
dlsch0_harq->rb_alloc[3] = localRIV2alloc_LUT100_3[rballoc];
dlsch0_harq->nb_rb = RIV2nb_rb_LUT100[rballoc];//NPRB;
RIV_max = RIV_max100;
break;
default:
LOG_E(PHY,"Invalid N_RB_D %dL\n", fp->N_RB_DL);
DevParam (fp->N_RB_DL, 0, 0);
break;
}
// harq_pid field is reserved
if ((rnti==si_rnti) || (rnti==ra_rnti) || (rnti==p_rnti)) { //
harq_pid=0;
} else {
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
if (rballoc>RIV_max) {
LOG_E(PHY,"ERROR: Format 1A: rb_alloc (%x) > RIV_max (%x)\n",rballoc,RIV_max);
return(-1);
}
NPRB = dlsch0_harq->nb_rb;
I_mcs = get_I_TBS(mcs);
}
if (NPRB==0)
return(-1);
//printf("NPRB %d, nb_rb %d, ndi %d\n",NPRB,dlsch0_harq->nb_rb,ndi);
dlsch0_harq->rvidx = rv;
dlsch0_harq->Nl = 1;
//dlsch0_harq->layer_index = 0;
dlsch0_harq->mimo_mode = (fp->nb_antenna_ports_eNB == 1) ? SISO : ALAMOUTI;
/*
if ((rnti!=si_rnti)&&(rnti!=ra_rnti)&&(rnti!=p_rnti)) { //handle toggling for C-RNTI
if (dlsch0_harq->first_tx == 1) {
LOG_D(PHY,"First TX for TC-RNTI %x, clearing first_tx flag\n",rnti);
dlsch0_harq->first_tx=0;
dlsch0_harq->Ndi = 1;
}
else {
if (ndi == dlsch0_harq->DCINdi)
dlsch0_harq->Ndi = 0;
else
dlsch0_harq->Ndi = 1;
}
dlsch0_harq->DCINdi=ndi;
}
else {
dlsch0_harq->Ndi = 1;
}
*/
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[I_mcs][NPRB-1];
dlsch[0]->harq_ids[subframe] = harq_pid;
dlsch[0]->active = 1;
dlsch0 = dlsch[0];
dlsch[0]->rnti = rnti;
dlsch[0]->harq_ids[subframe] = harq_pid;
if (dlsch0_harq->round == 0)
dlsch0_harq->status = ACTIVE;
break;
case format1:
switch (fp->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_TDD_t *)dci_pdu)->ndi,harq_pid);
} else {
mcs = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_FDD_t *)dci_pdu)->ndi,harq_pid);
}
break;
case 50:
if (frame_type == TDD) {
mcs = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->codeword=0;
// printf("DCI: Setting subframe_tx for subframe %d\n",subframe);
dlsch[0]->subframe_tx[subframe] = 1;
conv_rballoc(rah,
rballoc,fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
fp->N_RB_DL);
NPRB = dlsch0_harq->nb_rb;
if (NPRB==0)
return(-1);
dlsch0_harq->rvidx = rv;
dlsch0_harq->Nl = 1;
// dlsch[0]->layer_index = 0;
if (beamforming_mode == 0)
dlsch0_harq->mimo_mode = (fp->nb_antenna_ports_eNB == 1) ? SISO : ALAMOUTI;
else if (beamforming_mode == 7)
dlsch0_harq->mimo_mode = TM7;
else
LOG_E(PHY,"Invalid beamforming mode %dL\n", beamforming_mode);
dlsch0_harq->dl_power_off = 1;
/*
if (dlsch[0]->harq_processes[harq_pid]->first_tx == 1) {
LOG_D(PHY,"First TX for C-RNTI %x, clearing first_tx flag, shouldn't happen!\n",rnti);
dlsch[0]->harq_processes[harq_pid]->first_tx=0;
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
else {
LOG_D(PHY,"Checking for Toggled Ndi for C-RNTI %x, old value %d, DCINdi %d\n",rnti,dlsch[0]->harq_processes[harq_pid]->DCINdi,ndi);
if (ndi == dlsch[0]->harq_processes[harq_pid]->DCINdi)
dlsch[0]->harq_processes[harq_pid]->Ndi = 0;
else
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
dlsch[0]->harq_processes[harq_pid]->DCINdi=ndi;
*/
dlsch[0]->active = 1;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
// MCS and TBS don't change across HARQ rounds
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][NPRB-1];
}
dlsch[0]->harq_ids[subframe] = harq_pid;
dlsch0 = dlsch[0];
dlsch[0]->rnti = rnti;
break;
case format2: // DL Scheduling assignment for MIMO including closed loop spatial multiplexing
switch (fp->N_RB_DL) {
case 6:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 25:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 50:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 100:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
// note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
TB0_active = 1;
TB1_active = 1;
if ((rv1 == 1) && (mcs1 == 0)) {
TB0_active=0;
}
if ((rv2 == 1) && (mcs2 == 0)) {
TB1_active=0;
}
#ifdef DEBUG_HARQ
printf("RV0 = %d, RV1 = %d. MCS0 = %d, MCS1=%d\n", rv1, rv2, mcs1, mcs2);
#endif
if (TB0_active && TB1_active && tbswap==0) {
dlsch0=dlsch[0];
dlsch1=dlsch[1];
dlsch0->active = 1;
dlsch1->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
dlsch0_harq->status = ACTIVE;
dlsch1_harq->status = ACTIVE;
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
#ifdef DEBUG_HARQ
printf("\n ENB: BOTH ACTIVE\n");
#endif
}
else if (TB0_active && TB1_active && tbswap==1) {
dlsch0=dlsch[0];
dlsch1=dlsch[1];
dlsch0->active = 1;
dlsch1->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
dlsch0_harq->status = ACTIVE;
dlsch1_harq->status = ACTIVE;
dlsch0_harq->codeword=1;
dlsch1_harq->codeword=0;
}
else if (TB0_active && (TB1_active==0)) {
dlsch0=dlsch[0];
dlsch0->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch0_harq->rvidx = rv1;
dlsch0_harq->status = ACTIVE;
dlsch0_harq->codeword = 0;
dlsch1=NULL;
dlsch1_harq = NULL;
#ifdef DEBUG_HARQ
printf("\n ENB: TB1 is deactivated, retransmit TB0 transmit in TM6\n");
#endif
}
else if ((TB0_active==0) && TB1_active) {
dlsch1=dlsch[1];
dlsch1->active = 1;
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch1_harq->mcs = mcs2;
dlsch1_harq->rvidx = rv2;
dlsch1_harq->status = ACTIVE;
dlsch1_harq->codeword = 0;
dlsch0=NULL;
dlsch0_harq = NULL;
#ifdef DEBUG_HARQ
printf("\n ENB: TB0 is deactivated, retransmit TB1 transmit in TM6\n");
#endif
}
if (dlsch0 != NULL){
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
}
if (dlsch1_harq != NULL){
dlsch1->harq_ids[subframe] = harq_pid;
}
if (dlsch0 != NULL ){
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch0_harq->nb_rb = conv_nprb(rah, rballoc, fp->N_RB_DL);
if (dlsch1 != NULL){
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
}
} else if ((dlsch0 == NULL ) && (dlsch1 != NULL )){
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch1_harq->rb_alloc);
dlsch1_harq->nb_rb = conv_nprb(rah, rballoc, fp->N_RB_DL);
}
/*if (dlsch0_harq->nb_rb == 0)
return(-1);*/
// assume both TBs are active
if (dlsch0_harq != NULL)
dlsch0_harq->Nl = 1;
if (dlsch1_harq != NULL)
dlsch1_harq->Nl = 1;
// check if either TB is disabled (see 36-213 V11.3 Section )
if (fp->nb_antenna_ports_eNB == 2) {
if ((dlsch0 != NULL) && (dlsch1 != NULL)) { //two CW active
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
switch (tpmi) {
case 0:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch0_harq->pmi_alloc = pmi_extend(fp,0,1);
dlsch1_harq->pmi_alloc = pmi_extend(fp,0,1);
break;
case 1:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch0_harq->pmi_alloc = pmi_extend(fp,1,1);
dlsch0_harq->pmi_alloc = pmi_extend(fp,1,1);
break;
case 2: // PUSCH precoding
dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch0_harq->pmi_alloc = DL_pmi_single;
dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
default:
break;
}
} else if ((dlsch0 != NULL) && (dlsch1 == NULL)) { // only CW 0 active
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->TBS= TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
switch (tpmi) {
case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(fp,0,0);
break;
case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(fp,1,0);
break;
case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(fp,2,0);
break;
case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(fp,3,0);
break;
case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
}
} else if ((dlsch0 == NULL) && (dlsch1 != NULL)) {
dlsch1_harq->dl_power_off = 1;
dlsch1_harq->TBS= TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
switch (tpmi) {
case 0 :
dlsch1_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch1_harq->pmi_alloc = pmi_extend(fp,0,0);
break;
case 2:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch1_harq->pmi_alloc = pmi_extend(fp,1,0);
break;
case 3:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch1_harq->pmi_alloc = pmi_extend(fp,2,0);
break;
case 4:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch1_harq->pmi_alloc = pmi_extend(fp,3,0);
break;
case 5:
dlsch1_harq->mimo_mode = PUSCH_PRECODING0;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch1_harq->mimo_mode = PUSCH_PRECODING1;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
}
}
} else if (fp->nb_antenna_ports_eNB == 4) {
// fill in later
}
// reset HARQ process if this is the first transmission
/* if (dlsch0_harq->round == 0)
dlsch0_harq->status = ACTIVE;
if (dlsch1_harq->round == 0)
dlsch1_harq->status = ACTIVE;*/
if (dlsch0_harq != NULL)
dlsch0->rnti = rnti;
if (dlsch1 != NULL)
dlsch1->rnti = rnti;
break;
case format2A:
switch (fp->N_RB_DL) {
case 6:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 25:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 50:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
case 100:
if (fp->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (fp->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,fp->nb_antenna_ports_eNB);
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
// note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
// This must be set as in TM4, does not work properly now.
if (tbswap == 0) {
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
} else {
dlsch0 = dlsch[1];
dlsch1 = dlsch[0];
}
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
fp->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
if (dlsch0_harq->nb_rb == 0)
return(-1);
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// assume both TBs are active
dlsch0_harq->Nl = 1;
dlsch1_harq->Nl = 1;
dlsch0->active = 1;
dlsch1->active = 1;
// check if either TB is disabled (see 36-213 V11.3 Section )
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
dlsch0->active = 0;
}
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
dlsch1->active = 0;
}
// dlsch0_harq->dl_power_off = 0;
// dlsch1_harq->dl_power_off = 0;
if (fp->nb_antenna_ports_eNB == 2) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
if ((dlsch0->active==1) && (dlsch1->active==1)) {
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
} else {
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
}
} else if (fp->nb_antenna_ports_eNB == 4) { // 4 antenna case
if ((dlsch0->active==1) && (dlsch1->active==1)) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case 1: // one-layers on TB 0, two on TB 1
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->Nl = 2;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case 2: // two-layers on TB 0, two on TB 1
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->Nl = 2;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
if (fp->N_RB_DL <= 56) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
} else {
LOG_E(PHY,"Add implementation of Table 7.1.7.2.2-1 for two-layer TBS conversion with N_RB_DL > 56\n");
}
break;
case 3: //
LOG_E(PHY,"Illegal value (3) for TPMI in Format 2A DCI\n");
break;
}
} else if (dlsch0->active == 1) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
break;
case 1: // two-layers on TB 0
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->Nl = 2;
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
break;
case 2: // two-layers on TB 0, two on TB 1
case 3: //
LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
break;
}
} else if (dlsch1->active == 1) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
break;
case 1: // two-layers on TB 0
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->Nl = 2;
dlsch1_harq->dl_power_off = 1;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
break;
case 2: // two-layers on TB 0, two on TB 1
case 3: //
LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
break;
}
}
} else {
LOG_E(PHY,"Illegal number of antennas for eNB %d\n",fp->nb_antenna_ports_eNB);
}
// reset HARQ process if this is the first transmission
if ((dlsch0->active==1) && (dlsch0_harq->round == 0))
dlsch0_harq->status = ACTIVE;
if ((dlsch1->active==1) && (dlsch1_harq->round == 0))
dlsch1_harq->status = ACTIVE;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
// printf("eNB: Format 2A TBS0 %d, TBS1 %d\n",dlsch0_harq->TBS,dlsch1_harq->TBS);
break;
case format2B:
switch (fp->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
fp->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0))
dlsch0_harq->status = DISABLED;
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0))
dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
dlsch0_harq->mcs = mcs1;
if (dlsch0_harq->nb_rb > 0) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case format2C:
switch (fp->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
fp->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
if (dlsch0_harq->nb_rb == 0)
return(-1);
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
dlsch0->active = 0;
}
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
dlsch1->active = 0;
}
if ((dlsch0_harq->round == 0) && (dlsch0->active == 1) ) {
dlsch0_harq->status = ACTIVE;
dlsch0_harq->mcs = mcs1;
}
if ((dlsch1_harq->round == 0) && (dlsch1->active == 1) ) {
dlsch1_harq->status = ACTIVE;
dlsch1_harq->mcs = mcs2;
}
// check TPMI information to compute TBS
if (fp->nb_antenna_ports_eNB == 2) {
if (dlsch1->active == 1) { // both TBs are active
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
}
} else if (fp->nb_antenna_ports_eNB == 4) {
}
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case format2D:
switch (fp->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah,
rballoc,
fp->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
fp->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0))
dlsch0_harq->status = DISABLED;
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0))
dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
dlsch0_harq->mcs = mcs1;
if (dlsch0_harq->nb_rb > 0) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case format1E_2A_M10PRB:
harq_pid = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1E_2A_M10PRB: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
/*
tbswap = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
if (tbswap == 0) {
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
}
else{
dlsch0 = dlsch[1];
dlsch1 = dlsch[0];
}
*/
dlsch0 = dlsch[0];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
conv_rballoc(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,fp->N_RB_DL,
dlsch0_harq->rb_alloc);
//dlsch1->rb_alloc[0] = dlsch0->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
fp->N_RB_DL);
//dlsch1->nb_rb = dlsch0->nb_rb;
dlsch0_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
//dlsch1_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
dlsch0_harq->rvidx = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv;
//dlsch1_harq->rvidx = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26) --> only for format 2 and 2A
//if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0))
// dlsch0_harq->status = DISABLED;
//if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0))
// dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1;
//dlsch0->layer_index = tbswap;
//dlsch1->layer_index = 1-tbswap;
// Fix this
tpmi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;
switch (tpmi) {
case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(fp,0, 0);
break;
case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(fp,1, 0);
break;
case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(fp,2, 0);
break;
case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(fp,3, 0);
break;
case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
return(-1);
break;
}
// printf("Set pmi %x (tpmi %d)\n",dlsch0->pmi_alloc,tpmi);
if (fp->nb_antenna_ports_eNB == 1)
dlsch0_harq->mimo_mode = SISO;
// dlsch0_harq->Ndi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
dlsch0_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
if (dlsch0_harq->nb_rb > 0) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1;
dlsch0->rnti = rnti;
//dlsch1->rnti = rnti;
// dlsch0->dl_power_off = 1;
dlsch0_harq->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
//dlsch1->dl_power_off = 1;
break;
default:
LOG_E(PHY,"Unknown DCI format\n");
return(-1);
break;
}
if (dlsch0_harq) {
dlsch0_harq->frame = frame;
dlsch0_harq->subframe = subframe;
}
if (dlsch1_harq) {
dlsch1_harq->frame = frame;
dlsch1_harq->subframe = subframe;
}
#ifdef DEBUG_DCI
if (dlsch0) {
printf("dlsch0 eNB: dlsch0 %p\n",dlsch0);
printf("dlsch0 eNB: rnti %x\n",dlsch0->rnti);
printf("dlsch0 eNB: NBRB %d\n",dlsch0_harq->nb_rb);
printf("dlsch0 eNB: rballoc %x\n",dlsch0_harq->rb_alloc[0]);
printf("dlsch0 eNB: harq_pid %d\n",harq_pid);
printf("dlsch0 eNB: round %d\n",dlsch0_harq->round);
printf("dlsch0 eNB: rvidx %d\n",dlsch0_harq->rvidx);
printf("dlsch0 eNB: TBS %d (NPRB %d)\n",dlsch0_harq->TBS,NPRB);
printf("dlsch0 eNB: mcs %d\n",dlsch0_harq->mcs);
printf("dlsch0 eNB: tpmi %d\n",tpmi);
printf("dlsch0 eNB: mimo_mode %d\n",dlsch0_harq->mimo_mode);
}
if (dlsch1) {
printf("dlsch1 eNB: dlsch1 %p\n",dlsch1);
printf("dlsch1 eNB: rnti %x\n",dlsch1->rnti);
printf("dlsch1 eNB: NBRB %d\n",dlsch1_harq->nb_rb);
printf("dlsch1 eNB: rballoc %x\n",dlsch1_harq->rb_alloc[0]);
printf("dlsch1 eNB: harq_pid %d\n",harq_pid);
printf("dlsch1 eNB: round %d\n",dlsch1_harq->round);
printf("dlsch1 eNB: rvidx %d\n",dlsch1_harq->rvidx);
printf("dlsch1 eNB: TBS %d (NPRB %d)\n",dlsch1_harq->TBS,NPRB);
printf("dlsch1 eNB: mcs %d\n",dlsch1_harq->mcs);
printf("dlsch1 eNB: tpmi %d\n",tpmi);
printf("dlsch1 eNB: mimo_mode %d\n",dlsch1_harq->mimo_mode);
}
#endif
// compute DL power control parameters
if (dlsch0 != NULL){
computeRhoA_eNB(pdsch_config_dedicated, dlsch[0],dlsch0_harq->dl_power_off, fp->nb_antenna_ports_eNB);
computeRhoB_eNB(pdsch_config_dedicated,&(fp->pdsch_config_common),fp->nb_antenna_ports_eNB,dlsch[0],dlsch0_harq->dl_power_off);
}
if (dlsch1 != NULL){
computeRhoA_eNB(pdsch_config_dedicated, dlsch[1],dlsch1_harq->dl_power_off, fp->nb_antenna_ports_eNB);
computeRhoB_eNB(pdsch_config_dedicated,&(fp->pdsch_config_common),fp->nb_antenna_ports_eNB,dlsch[1],dlsch1_harq->dl_power_off);
}
return(0);
}
int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci)
......
openair1/PHY/LTE_TRANSPORT/prach.c
View file @ d75dc39a
......@@ -1205,7 +1205,7 @@ void rx_prach0(PHY_VARS_eNB *eNB,
frame = eNB->proc.frame_prach_br;
subframe = eNB->proc.subframe_prach_br;
prachF = eNB->prach_vars_br.prachF;
rxsigF = eNB->prach_vars_br.rxsigF;
rxsigF = eNB->prach_vars_br.rxsigF[ce_level];
#ifdef PRACH_DEBUG
if ((frame&1023) < 20) LOG_I(PHY,"PRACH (eNB) : running rx_prach (br_flag %d, ce_level %d) for frame %d subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d, rootSequenceIndex %d, repetition number %d,numRepetitionsPrePreambleAttempt %d\n",
br_flag,ce_level,frame,subframe,
......@@ -1222,7 +1222,7 @@ void rx_prach0(PHY_VARS_eNB *eNB,
frame = eNB->proc.frame_prach;
subframe = eNB->proc.subframe_prach;
prachF = eNB->prach_vars.prachF;
rxsigF = eNB->prach_vars.rxsigF;
rxsigF = eNB->prach_vars.rxsigF[0];
#ifdef PRACH_DEBUG
if ((frame&1023) < 20) LOG_I(PHY,"PRACH (eNB) : running rx_prach for subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d , rootSequenceIndex %d\n",
subframe,fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset,prach_ConfigIndex,rootSequenceIndex);
......
openair1/PHY/LTE_TRANSPORT/proto.h
View file @ d75dc39a
......@@ -1656,12 +1656,12 @@ int generate_ue_dlsch_params_from_dci(int frame,
uint8_t beamforming_mode,
uint16_t tc_rnti);
int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,
void fill_dci_and_dlsch(PHY_VARS_eNB *eNB,
eNB_rxtx_proc_t *proc,
DCI_ALLOC_t *dci_alloc,
nfapi_dl_config_dci_dl_pdu *pdu);
int fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *dci_alloc,nfapi_dl_config_mpdcch_pdu *pdu);
void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *dci_alloc,nfapi_dl_config_mpdcch_pdu *pdu);
void fill_dci0(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_alloc,
nfapi_hi_dci0_dci_pdu *pdu);
......
openair1/PHY/LTE_TRANSPORT/pucch.c
View file @ d75dc39a
......@@ -506,7 +506,11 @@ void generate_pucch1x(int32_t **txdataF,
}
break;
case pucch_format1b_csA2:
case pucch_format1b_csA3:
case pucch_format1b_csA4:
AssertFatal(1==0,"PUCCH format 1b_csX not supported yet\n");
break;
case pucch_format2:
case pucch_format2a:
case pucch_format2b:
......
openair1/SCHED/phy_procedures_lte_eNb.c
View file @ d75dc39a
......@@ -768,7 +768,6 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
uint8_t SR_payload = 0,pucch_b0b1[4][2]= {{0,0},{0,0},{0,0},{0,0}},harq_ack[4]={0,0,0,0};
int32_t metric[4]={0,0,0,0},metric_SR=0,max_metric;
ANFBmode_t bundling_flag=1;
const int subframe = proc->subframe_rx;
const int frame = proc->frame_rx;
int i;
......@@ -894,8 +893,6 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
}
else { // frame_type == TDD
// This should be retrived from ulsch structure
bundling_flag = 1;
// if SR was detected, use the n1_pucch from SR
if (SR_payload==1) {
......@@ -963,7 +960,7 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
}
fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,2,0xffff); // special_bundling mode
}
else if ((bundling_flag == 0) && (res==2)){ // multiplexing + no SR, implement Table 10.1.3-5 (Rel14) for multiplexing with M=2
else if ((uci->tdd_bundling == 0) && (res==2)){ // multiplexing + no SR, implement Table 10.1.3-5 (Rel14) for multiplexing with M=2
if (pucch_b0b1[0][0] == 4 ||
pucch_b0b1[1][0] == 4) { // there isn't a likely transmission
harq_ack[0] = 4; // DTX
......@@ -1003,8 +1000,8 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
}
}
fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode
} //else if ((bundling_flag == 0) && (res==2))
else if ((bundling_flag == 0) && (res==3)){ // multiplexing + no SR, implement Table 10.1.3-6 (Rel14) for multiplexing with M=3
} //else if ((uci->tdd_bundling == 0) && (res==2))
else if ((uci->tdd_bundling == 0) && (res==3)){ // multiplexing + no SR, implement Table 10.1.3-6 (Rel14) for multiplexing with M=3
if (harq_ack[0] == 4 ||
harq_ack[1] == 4 ||
......@@ -1084,8 +1081,8 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
}
}
fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode
} //else if ((bundling_flag == 0) && (res==3))
else if ((bundling_flag == 0) && (res==4)){ // multiplexing + no SR, implement Table 10.1.3-7 (Rel14) for multiplexing with M=4
} //else if ((uci->tdd_bundling == 0) && (res==3))
else if ((uci->tdd_bundling == 0) && (res==4)){ // multiplexing + no SR, implement Table 10.1.3-7 (Rel14) for multiplexing with M=4
if (pucch_b0b1[0][0] == 4 ||
pucch_b0b1[1][0] == 4 ||
pucch_b0b1[2][0] == 4 ||
......@@ -1220,7 +1217,7 @@ void uci_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
}
}
fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode
} // else if ((bundling_flag == 0) && (res==4))
} // else if ((uci->tdd_bundling == 0) && (res==4))
else { // bundling
harq_ack[0] = pucch_b0b1[0][0];
harq_ack[1] = pucch_b0b1[0][1];
......
openair2/LAYER2/MAC/config.c
View file @ d75dc39a
......@@ -333,7 +333,7 @@ void config_sib2(int Mod_idP,
struct PRACH_ConfigSIB_v1310 *ext4_prach=radioResourceConfigCommon_BRP->ext4->prach_ConfigCommon_v1310;
PRACH_ParametersListCE_r13_t *prach_ParametersListCE_r13 = &ext4_prach->prach_ParametersListCE_r13;
int i;
PRACH_ParametersCE_r13_t *p;
cfg->emtc_config.prach_ce_level_0_enable.value=0;
cfg->emtc_config.prach_ce_level_1_enable.value=0;
......
openair2/LAYER2/MAC/eNB_scheduler.c
View file @ d75dc39a
......@@ -420,12 +420,6 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frameP, sub_frame
int mbsfn_status[MAX_NUM_CCs];
protocol_ctxt_t ctxt;
#if defined(ENABLE_ITTI)
MessageDef *msg_p;
const char *msg_name;
instance_t instance;
int result;
#endif
int CC_id,i; //,next_i;
UE_list_t *UE_list=&RC.mac[module_idP]->UE_list;
rnti_t rnti;
......
openair2/LAYER2/MAC/eNB_scheduler_RA.c
View file @ d75dc39a
......@@ -66,7 +66,7 @@ void add_msg3(module_id_t module_idP,int CC_id, RA_TEMPLATE *RA_template, frame_
eNB_MAC_INST *eNB = RC.mac[module_idP];
COMMON_channels_t *cc = &eNB->common_channels[CC_id];
uint8_t i,j;
uint8_t j;
nfapi_ul_config_request_t *ul_req;
nfapi_ul_config_request_pdu_t *ul_config_pdu;
nfapi_ul_config_request_body_t *ul_req_body;
......@@ -83,8 +83,8 @@ void add_msg3(module_id_t module_idP,int CC_id, RA_TEMPLATE *RA_template, frame_
#ifdef Rel14
if (RA_template->rach_resource_type>0) {
LOG_D(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA %d CE level %d is active, Msg3 in (%d,%d)\n",
module_idP,frameP,subframeP,CC_id,i,RA_template->rach_resource_type-1,
LOG_D(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d CE level %d is active, Msg3 in (%d,%d)\n",
module_idP,frameP,subframeP,CC_id,RA_template->rach_resource_type-1,
RA_template->Msg3_frame,RA_template->Msg3_subframe);
LOG_D(MAC,"Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d)\n",
frameP,subframeP,RA_template->Msg3_frame,RA_template->Msg3_subframe);
......@@ -120,8 +120,8 @@ void add_msg3(module_id_t module_idP,int CC_id, RA_TEMPLATE *RA_template, frame_
else
#endif
{
LOG_D(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA %d is active, Msg3 in (%d,%d)\n",
module_idP,frameP,subframeP,CC_id,i,RA_template->Msg3_frame,RA_template->Msg3_subframe);
LOG_D(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n",
module_idP,frameP,subframeP,CC_id,RA_template->Msg3_frame,RA_template->Msg3_subframe);
LOG_D(MAC,"Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d)\n",
frameP,subframeP,RA_template->Msg3_frame,RA_template->Msg3_subframe);
......@@ -164,8 +164,8 @@ void add_msg3(module_id_t module_idP,int CC_id, RA_TEMPLATE *RA_template, frame_
// save UL scheduling information for preprocessor
for (j=0;j<RA_template->msg3_nb_rb;j++) cc->vrb_map_UL[RA_template->msg3_first_rb+j]=1;
LOG_D(MAC,"[eNB %d][PUSCH-RA %x] CC_id %d Frame %d subframeP %d Scheduled (PHICH) RA %d (mcs %d, first rb %d, nb_rb %d,round %d)\n",
module_idP,RA_template->rnti,CC_id,frameP,subframeP,i,10,
LOG_D(MAC,"[eNB %d][PUSCH-RA %x] CC_id %d Frame %d subframeP %d Scheduled (PHICH) RA (mcs %d, first rb %d, nb_rb %d,round %d)\n",
module_idP,RA_template->rnti,CC_id,frameP,subframeP,10,
1,1,
RA_template->msg3_round-1);
} // if (RA_template->msg3_round != 0) { // program HI too
......
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
View file @ d75dc39a
......@@ -455,7 +455,6 @@ schedule_ue_spec(
int N_RBG[MAX_NUM_CCs];
nfapi_dl_config_request_body_t *dl_req;
nfapi_dl_config_request_pdu_t *dl_config_pdu;
nfapi_tx_request_pdu_t *TX_req;
int tdd_sfa;
#if 0
......@@ -1319,7 +1318,6 @@ fill_DLSCH_dci(
int N_RBG;
int N_RB_DL;
COMMON_channels_t *cc;
eNB_UE_STATS *eNB_UE_stats;
start_meas(&eNB->fill_DLSCH_dci);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_FILL_DLSCH_DCI,VCD_FUNCTION_IN);
......@@ -1347,7 +1345,6 @@ fill_DLSCH_dci(
else harq_pid = ((frameP*10)+subframeP)&7;
nb_rb = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid];
eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];
/// Synchronizing rballoc with rballoc_sub
......
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
View file @ d75dc39a
......@@ -780,7 +780,6 @@ void get_csi_params(COMMON_channels_t *cc,struct CQI_ReportPeriodic *cqi_ReportP
uint8_t get_dl_cqi_pmi_size_pusch(UE_sched_ctrl *sched_ctl,COMMON_channels_t *cc,uint8_t tmode,uint8_t ri, CQI_ReportModeAperiodic_t *cqi_ReportModeAperiodic) {
int Ntab[6] = {0,4,7,9,10,13};
int Ntab_uesel[6] = {0,8,13,17,19,25};
int N = Ntab[cc->p_eNB];
int Ltab_uesel[6] = {0,6,9,13,15,18};
int L = Ltab_uesel[cc->p_eNB];
......@@ -847,7 +846,8 @@ uint8_t get_dl_cqi_pmi_size_pusch(UE_sched_ctrl *sched_ctl,COMMON_channels_t *cc
break;
}
AssertFatal(1==0,"Shouldn't get here\n");
return(0);
}
uint8_t get_rel8_dl_cqi_pmi_size(UE_sched_ctrl *sched_ctl,int CC_idP,COMMON_channels_t *cc,uint8_t tmode, struct CQI_ReportPeriodic *cqi_ReportPeriodic) {
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @ d75dc39a
......@@ -1178,7 +1178,7 @@ abort();
LOG_I(MAC,"Frame %d, Subframe %d: Requesting CQI information for UE %d/%x => O_r1 %d, betaCQI %d\n",
frameP,subframeP,UE_id,rnti,
ul_config_pdu->ulsch_cqi_ri_pdu.cqi_ri_information.cqi_ri_information_rel9.aperiodic_cqi_pmi_ri_report.cc[0].dl_cqi_pmi_size[0],
UE_template->physicalConfigDedicated->pusch_ConfigDedicated->betaOffset_CQI_Index);
(int)UE_template->physicalConfigDedicated->pusch_ConfigDedicated->betaOffset_CQI_Index);
}
}
add_ue_ulsch_info(module_idP,
......
openair2/LAYER2/MAC/main.c
View file @ d75dc39a
......@@ -79,14 +79,10 @@ void mac_UE_out_of_sync_ind(module_id_t module_idP, frame_t frameP, uint16_t eNB
int mac_top_init_ue(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, uint8_t HO_active)
{
module_id_t Mod_id,i,j;
RA_TEMPLATE *RA_template;
UE_TEMPLATE *UE_template;
int size_bytes1,size_bytes2,size_bits1,size_bits2;
int CC_id;
module_id_t Mod_id,i;
int list_el;
UE_list_t *UE_list;
COMMON_channels_t *cc;
LOG_I(MAC,"[MAIN] Init function start:Nb_UE_INST=%d\n",NB_UE_INST);
if (NB_UE_INST>0) {
......@@ -107,36 +103,6 @@ int mac_top_init_ue(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active,
}
if (NB_eNB_INST>0) {
RC.mac = (eNB_MAC_INST**)malloc16(NB_eNB_INST*sizeof(eNB_MAC_INST*));
for (i=0;i<NB_eNB_INST;i++)
RC.mac[i] = (eNB_MAC_INST*)malloc16(sizeof(eNB_MAC_INST));
AssertFatal(RC.mac != NULL,
"[MAIN] can't ALLOCATE %zu Bytes for %d eNB_MAC_INST with size %zu \n",NB_eNB_INST*sizeof(eNB_MAC_INST*),NB_eNB_INST,sizeof(eNB_MAC_INST));
LOG_D(MAC,"[MAIN] ALLOCATE %zu Bytes for %d eNB_MAC_INST @ %p\n",sizeof(eNB_MAC_INST),NB_eNB_INST,RC.mac);
for (i=0;i<NB_eNB_INST;i++) bzero(RC.mac[i],sizeof(eNB_MAC_INST));
} else {
RC.mac = NULL;
}
// Initialize Linked-List for Active UEs
for(Mod_id=0; Mod_id<NB_eNB_INST; Mod_id++) {
UE_list = &RC.mac[Mod_id]->UE_list;
UE_list->num_UEs=0;
UE_list->head=-1;
UE_list->head_ul=-1;
UE_list->avail=0;
for (list_el=0; list_el<NUMBER_OF_UE_MAX-1; list_el++) {
UE_list->next[list_el]=list_el+1;
UE_list->next_ul[list_el]=list_el+1;
}
UE_list->next[list_el]=-1;
UE_list->next_ul[list_el]=-1;
}
LOG_I(MAC,"[MAIN] calling RRC\n");
openair_rrc_top_init_ue(eMBMS_active, uecap_xer, cba_group_active,HO_active);
......@@ -383,7 +349,6 @@ int l2_init_eNB()
{
int i;
LOG_I(MAC,"[MAIN] MAC_INIT_GLOBAL_PARAM IN...\n");
......
openair2/LAYER2/MAC/proto.h
View file @ d75dc39a
......@@ -141,10 +141,14 @@ int8_t get_deltaP_rampup(module_id_t module_idP,uint8_t CC_id);
uint16_t mac_computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs);
void add_msg3(module_id_t module_idP,int CC_id, RA_TEMPLATE *RA_template, frame_t frameP, sub_frame_t subframeP);
//main.c
int mac_top_init(int eMBMS_active, char *uecap_xer,uint8_t cba_group_active, uint8_t HO_active);
int mac_top_init_eNB(void);
char layer2_init_UE(module_id_t module_idP);
char layer2_init_eNB(module_id_t module_idP, uint8_t Free_ch_index);
......@@ -997,6 +1001,8 @@ int narrowband_to_first_rb(COMMON_channels_t *cc, int nb_index);
#endif
int l2_init_eNB(void);
#endif
......
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