add targets/ARCH/ORAN_FHI/lib in OAI

targets/ARCH/ORAN_FHI/lib/config.h

+/******************************************************************************
+*
+*   Copyright (c) 2020 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief
+ * @file
+ * @ingroup
+ * @author Intel Corporation
+ **/
+
+#ifndef _SAMPLEAPP__CONFIG_H_
+#define _SAMPLEAPP__CONFIG_H_
+
+#include <stdint.h>
+#include <rte_ether.h>
+#include "xran_fh_o_du.h"
+
+/** Run time configuration of application */
+typedef struct _RuntimeConfig
+{
+    uint8_t appMode;      /**< Application mode: lls-CU or RU  */
+    uint8_t xranTech;     /**< Radio Access Technology (NR or LTE) */
+    uint8_t xranCat;      /**< xran mode: NR Categoty A, NR Category B, LTE Cat A, LTE Cat B */
+    uint8_t numCC;        /**< Number of CC per ports supported by RU */
+    uint8_t numAxc;       /**< Number of Antenna Carriers per CC */
+    uint8_t numUlAxc;     /**< Number of Antenna Carriers per CC for UL (Cat B) */
+    uint32_t antElmTRx;   /**< Number of antenna elements for TX and RX */
+    uint32_t muMimoUEs;   /**< Number of UEs (with 1 RX ant)/beams */
+
+    uint32_t DlLayersPerUe; /**< Number of DL layer per UE */
+    uint32_t UlLayersPerUe; /**< Number of UL layer per UE */
+
+    uint32_t ttiPeriod;   /**< TTI period */
+    uint32_t testVect;    /**< Test Signal to send */
+    struct rte_ether_addr o_du_addr[XRAN_VF_MAX]; /**<  O-DU Ethernet Mac Address */
+    struct rte_ether_addr o_ru_addr[XRAN_VF_MAX]; /**<  O-RU Ethernet Mac Address */
+    struct rte_ether_addr tmp_addr; /**<  Temp Ethernet Mac Address */
+
+    uint32_t instance_id;  /**<  Instance ID of application */
+    uint32_t io_core;      /**<  Core used for IO */
+    uint64_t io_worker;    /**<  Mask for worker cores */
+    int32_t  io_sleep;     /**< enable sleep on PMD cores */
+    uint32_t system_core;  /* house keeping core */
+    int      iova_mode;    /**< DPDK IOVA Mode */
+
+    uint32_t mtu; /**< maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+                       xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) */
+    int numSlots;  /**< number of slots in IQ vector */
+    char ant_file[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**<  file to use for test vector */
+    char prach_file[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**<  file to use for test vector */
+
+    char dl_bfw_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file with beamforming weights for DL streams */
+    char ul_bfw_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR][512]; /**< file with beamforming weights for UL streams */
+
+    char ul_srs_file [XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR][512]; /**< file with SRS content for UL antenna elements */
+
+    /* prach config */
+    uint8_t enablePrach; /**<  enable PRACH */
+    uint8_t prachOffset; /**< Sets the PRACH position in frequency / subcarrier position, n_PRBoffset^RA and is expressed as a physical resource block number.
+                              Set by SIB2, prach-FreqOffset in E-UTRA. */
+
+    uint8_t prachConfigIndex;/**< TS36.211 - Table 5.7.1-2 : PRACH Configuration Index */
+    uint8_t iqswap;          /**< do swap of IQ before send to ETH */
+    uint8_t nebyteorderswap; /**< do swap of byte order from host byte order to network byte order. ETH */
+    uint8_t compression;     /**< enable use case with compression */
+    uint8_t CompHdrType;     /**< dynamic or static compression header */
+
+    uint16_t totalBfWeights; /**< The total number of beamforming weights on RU */
+
+    uint8_t enableSrs; /**< enable SRS (valid for Cat B only) */
+    uint16_t srsSymMask; /**< SRS symbol mask [014] within S/U slot [0-13] def is  13 */
+
+    uint16_t maxFrameId; /**< max value of frame id */
+
+    uint16_t Tadv_cp_dl;
+    uint16_t T2a_min_cp_dl;
+    uint16_t T2a_max_cp_dl;
+    uint16_t T2a_min_cp_ul;
+    uint16_t T2a_max_cp_ul;
+    uint16_t T2a_min_up;
+    uint16_t T2a_max_up;
+    uint16_t Ta3_min;
+    uint16_t Ta3_max;
+    uint16_t T1a_min_cp_dl;
+    uint16_t T1a_max_cp_dl;
+    uint16_t T1a_min_cp_ul;
+    uint16_t T1a_max_cp_ul;
+    uint16_t T1a_min_up;
+    uint16_t T1a_max_up;
+    uint16_t Ta4_min;
+    uint16_t Ta4_max;
+
+    uint8_t enableCP;    /**<  enable C-plane */
+    uint8_t cp_vlan_tag; /**<  C-plane vlan tag */
+    uint8_t up_vlan_tag; /**<  U-plane vlan tag */
+
+    int32_t debugStop;
+    int32_t debugStopCount;
+    int32_t bbdevMode;
+    int32_t DynamicSectionEna;
+    int32_t GPS_Alpha;
+    int32_t GPS_Beta;
+
+    uint8_t  mu_number;       /**< Mu numner as per 3GPP */
+    uint32_t nDLAbsFrePointA; /**< Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 */
+    uint32_t nULAbsFrePointA; /**< Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 */
+    uint32_t nDLBandwidth;    /**< Carrier bandwidth for in MHz. Value: 5->400 */
+    uint32_t nULBandwidth;    /**< Carrier bandwidth for in MHz. Value: 5->400 */
+    uint32_t nDLFftSize;      /**< DL FFT size */
+    uint32_t nULFftSize;      /**< UL FFT size */
+
+
+    uint8_t nFrameDuplexType;
+    uint8_t nTddPeriod;
+    struct xran_slot_config sSlotConfig[XRAN_MAX_TDD_PERIODICITY];
+    struct xran_prb_map PrbMapDl;
+    struct xran_prb_map PrbMapUl;
+
+    int32_t DU_Port_ID_bitwidth;
+    int32_t BandSector_ID_bitwidth;
+    int32_t CC_ID_bitwidth;
+    int32_t RU_Port_ID_bitwidth;
+
+} RuntimeConfig;
+
+/**
+ * Parse application configuration file.
+ *
+ * @param filename The name of the configuration file to be parsed.
+ * @param config The configuration structure to be filled with parsed data. */
+int parseConfigFile(char *filename, RuntimeConfig *config);
+
+#endif /* _SAMPLEAPP__CONFIG_H_ */

targets/ARCH/ORAN_FHI/lib/debug.h

+/******************************************************************************
+*
+*   Copyright (c) 2020 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief
+ * @file
+ * @ingroup
+ * @author Intel Corporation
+ **/
+
+#ifndef _SAMPLEAPP__DEBUG_H_
+#define _SAMPLEAPP__DEBUG_H_
+
+#include <stdio.h>
+
+#include "config.h"
+
+#define MAX_FILE_NAME_LEN (512)
+#define MAX_PATH_NAME_LEN (1024)
+
+#ifdef _DEBUG
+    #define log_dbg(fmt, ...)                       \
+        fprintf(stderr,                     \
+            "DEBUG: %s(%d): " fmt "\n",             \
+            __FILE__,                       \
+            __LINE__, ##__VA_ARGS__)
+#else
+    #define log_dbg(fmt, ...)
+#endif
+
+#if defined(_DEBUG) || defined(_VERBOSE)
+    #define log_wrn(fmt, ...)                               \
+        fprintf(                                            \
+            stderr,                                     \
+            "WARNING: %s(%d): " fmt "\n",                   \
+            __FILE__,                                       \
+            __LINE__, ##__VA_ARGS__)
+#else
+    #define log_dbg(fmt, ...)
+    #define log_wrn(fmt, ...)
+#endif
+
+
+#define log_err(fmt, ...)                       \
+    fprintf(stderr,                     \
+        "ERROR: %s(%d): " fmt "\n",             \
+        __FILE__,                       \
+        __LINE__, ##__VA_ARGS__)
+
+
+inline void ShowData(void* ptr, unsigned int size)
+{
+    uint8_t *d =  (uint8_t *)ptr;
+    unsigned int i;
+
+    for(i = 0; i < size; i++)
+    {
+        if ( !(i & 0xf) )
+            printf("\n");
+        printf("%02x ", d[i]);
+    }
+    printf("\n");
+}
+
+
+#endif /* _SAMPLEAPP__DEBUG_H_ */

targets/ARCH/ORAN_FHI/lib/ethdi.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has all definitions for the Ethernet Data Interface Layer
+ * @file ethdi.h
+ * @ingroup group_lte_source_auxlib
+ * @author Intel Corporation
+ **/
+
+
+#ifndef _ETHDI_H_
+#define _ETHDI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_config.h>
+#include <rte_mbuf.h>
+#include <rte_timer.h>
+
+/*  comment this to enable PDUMP
+ *  DPDK has to be compiled with
+ *      CONFIG_RTE_LIBRTE_PMD_PCAP=y
+ *      CONFIG_RTE_LIBRTE_PDUMP=y
+ */
+#undef RTE_LIBRTE_PDUMP
+
+#ifdef RTE_LIBRTE_PDUMP
+#include <rte_pdump.h>
+#endif
+
+#include "ethernet.h"
+#include "xran_fh_o_du.h"
+
+#define XRAN_THREAD_DEFAULT_PRIO (98)
+
+/* If we're not receiving packets for more then this threshold... */
+//#define SLEEP_THRESHOLD (rte_get_tsc_hz() / 30)    /* = 33.3(3)ms */
+/* we go to sleep for this long (usleep). Undef SLEEP_TRESHOLD to disable. */
+#define SLEEP_TIME 200      /* (us) */
+#define BCAST {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+
+#define TX_TIMER_INTERVAL ((rte_get_timer_hz() / 1000000000L)*interval_us*1000) /* nanosec */
+#define TX_RX_LOOP_TIME rte_get_timer_hz() / 1
+
+/* CAUTION: Keep in sync with the string table below. */
+enum xran_entities_id
+{
+    ID_O_DU,
+    ID_O_RU,
+    ID_BROADCAST,
+    ID_MAX
+};
+
+static char *const entity_names[] = {
+    "ORAN O-DU sim app",
+    "ORAN O-RU sim app",
+};
+
+typedef int (*PROCESS_CB)(void * arg);
+
+/**
+ * Structure storing internal configuration of workers
+ */
+struct xran_worker_config {
+    lcore_function_t *f;
+    void *arg;
+    int32_t state;
+};
+
+struct xran_ethdi_ctx
+{
+    struct xran_io_cfg io_cfg;
+    struct rte_ether_addr entities[XRAN_VF_MAX][ID_BROADCAST + 1];
+
+    struct rte_ring *tx_ring[XRAN_VF_MAX];
+    struct rte_ring *rx_ring[XRAN_VF_MAX];
+    struct rte_ring *pkt_dump_ring[XRAN_VF_MAX];
+    struct rte_timer timer_autodetect;
+    struct rte_timer timer_ping;
+    struct rte_timer timer_sync;
+    struct rte_timer timer_tx;
+
+    struct xran_worker_config pkt_wrk_cfg[RTE_MAX_LCORE];
+
+    unsigned pkt_stats[PKT_LAST + 1];
+};
+
+enum {
+    MBUF_KEEP,
+    MBUF_FREE
+};
+
+extern enum xran_if_state xran_if_current_state;
+
+static inline struct xran_ethdi_ctx *xran_ethdi_get_ctx(void)
+{
+    extern struct xran_ethdi_ctx g_ethdi_ctx;
+
+    return &g_ethdi_ctx;
+}
+typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint64_t rx_time);
+
+typedef int (*ethertype_handler)(struct rte_mbuf *, uint64_t rx_time);
+typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint64_t rx_time);
+
+int xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback);
+
+int32_t xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg,
+    int *lcore_id, struct rte_ether_addr *p_o_du_addr,
+    struct rte_ether_addr *p_ru_addr);
+
+struct rte_mbuf *xran_ethdi_mbuf_alloc(void);
+int32_t xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id);
+int32_t xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id);
+int32_t xran_ethdi_filter_packet(struct rte_mbuf *pkt, uint64_t rx_time);
+int32_t process_dpdk_io(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _ETHDI_H_ */

targets/ARCH/ORAN_FHI/lib/ethernet.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has all definitions for the Ethernet Data Interface Layer
+ * @file ethernet.h
+ * @ingroup group_lte_source_auxlib
+ * @author Intel Corporation
+ **/
+
+#ifndef AUXLIB_ETHERNET_H
+#define AUXLIB_ETHERNET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_config.h>
+#include <rte_ether.h>
+#include <rte_mbuf.h>
+
+#define BURST_SIZE 4096
+
+#define ETHER_TYPE_ETHDI RTE_ETHER_TYPE_IPV4    /* hack needed for jumbo frames */
+#define ETHER_TYPE_ECPRI 0xAEFE
+#define ETHER_TYPE_SYNC 0xBEFE
+#define ETHER_TYPE_START_TX 0xCEFE
+
+#define NUM_MBUFS 65535/*16383*/ /*65535*/ /** optimal is n = (2^q - 1) */
+#define NUM_MBUFS_RING NUM_MBUFS+1 /** The size of the ring (must be a power of 2) */
+
+#define MBUF_CACHE 256
+
+#define MBUF_POOL_ELM_SMALL (1500 + RTE_PKTMBUF_HEADROOM )/* regular ethernet MTU, most compatible */
+#define MBUF_POOL_ELEMENT (MAX_RX_LEN + RTE_PKTMBUF_HEADROOM)
+
+#define MAX_RX_LEN 9600
+#define MAX_TX_LEN (MAX_RX_LEN - 14) /* headroom for rx driver */
+#define MAX_DATA_SIZE (MAX_TX_LEN - sizeof(struct ether_hdr) - \
+    sizeof(struct ethdi_hdr) - sizeof(struct burst_hdr))
+
+/* Looks like mbuf size is limited to 16 bits - see the buf_len field. */
+#define MBUF_POOL_ELM_BIG USHRT_MAX
+#define NUM_MBUFS_BIG 64
+
+#define DEFAULT_DUMP_LENGTH 96
+
+extern struct rte_mempool *_eth_mbuf_pool;
+extern struct rte_mempool *_eth_mbuf_pool_small;
+extern struct rte_mempool *_eth_mbuf_pool_big;
+extern struct rte_mempool *socket_direct_pool;
+extern struct rte_mempool *socket_indirect_pool;
+
+/* Do NOT change the order of this enum and below
+ * - need to be in sync with the table of handlers in testue.c */
+enum pkt_type
+{
+    PKT_ZERO,
+    PKT_EMPTY,
+    PKT_DISCOVER_REQUEST,
+    PKT_PING,
+    PKT_PONG,
+    PKT_DISCOVER_REPLY,
+    PKT_LTE_DATA,
+    PKT_LTE_CONTROL,
+    PKT_BURST,
+    PKT_DATATEST,
+    PKT_ADD_ETHDEV,
+    PKT_SYNC_START,
+    PKT_LAST,
+};
+
+/* Do NOT change the order. */
+static char * const xran_pkt_descriptions[PKT_LAST + 1] = {
+    "ZERO",
+    "empty packet",
+    "discovery request packet",
+    "ping packet",
+    "pong packet",
+    "discovery reply packet",
+    "LTE data packet",
+    "LTE control packet",
+    "BURST packet",
+    "DATATEST packet",
+    "Add ethernet port command packet",
+    "SYNC-START packet",
+    "LAST packet",
+};
+
+struct burst_hdr {
+    int8_t pkt_idx;
+    int8_t total_pkts;
+    int8_t original_type;
+    int8_t data[];
+};
+
+struct ethdi_hdr {
+    uint8_t pkt_type;
+    uint8_t source_id;
+    uint8_t dest_id;
+    int8_t data[];    /* original raw data starts here! */
+};
+
+
+void xran_init_mbuf_pool(void);
+
+void xran_init_port(int port);
+
+void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb);
+
+#if 0
+void xran_memdump(void *addr, int len);
+void xran_add_eth_hdr(struct ether_addr *dst, uint16_t ethertype, struct rte_mbuf *);
+int xran_send_mbuf(struct ether_addr *dst, struct rte_mbuf *mb);
+int xran_send_message_burst(int dst_id, int pkt_type, void *body, int len);
+int xran_show_delayed_message(void);
+#endif
+/*
+ * Print a message after all critical processing done.
+ * Mt-safe. 4 variants - normal, warning, error and debug log.
+ */
+int __xran_delayed_msg(const char *fmt, ...);
+#define nlog(m, ...) __xran_delayed_msg("%s(): " m "\n", __FUNCTION__, ##__VA_ARGS__)
+#define delayed_message nlog    /* this is the old alias for this function */
+#define wlog(m, ...) nlog("WARNING: " m, ##__VA_ARGS__)
+#define elog(m, ...) nlog("ERROR: " m, ##__VA_ARGS__)
+#ifdef DEBUG
+# define dlog(m, ...) nlog("DEBUG: " m, ##__VA_ARGS__)
+#else
+# define dlog(m, ...)
+#endif
+
+#define PANIC_ON(x, m, ...) do { if (unlikely(x)) \
+    rte_panic("%s: " m "\n", #x, ##__VA_ARGS__); } while (0)
+
+/* Add mbuf to the TX ring. */
+static inline int xran_enqueue_mbuf(struct rte_mbuf *mb, struct rte_ring *r)
+{
+    if (rte_ring_enqueue(r, mb) == 0) {
+        return 1;   /* success */
+    }
+
+    rte_pktmbuf_free(mb);
+    wlog("failed to enqueue packet on port %d (ring full)", mb->port);
+
+    return 0;   /* fail */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AUXLIB_ETHERNET_H */

targets/ARCH/ORAN_FHI/lib/xran_app_frag.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+
+/**
+ * @brief Header file for functions to perform application level fragmentation
+ *
+ * @file xran_app_frag.h
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#ifndef _XRAN_APP_FRAG_
+#define _XRAN_APP_FRAG_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <rte_config.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#include <rte_mempool.h>
+#include <rte_byteorder.h>
+
+#include "xran_fh_o_du.h"
+#include "xran_cp_api.h"
+
+int32_t xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */
+                                    struct rte_mbuf **pkts_out,
+                                    uint16_t nb_pkts_out,
+                                    uint16_t mtu_size,
+                                    struct rte_mempool *pool_direct,
+                                    struct rte_mempool *pool_indirect,
+                                    struct xran_section_info *sectinfo,
+                                    uint8_t *seqid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XRAN_APP_FRAG_ */
+

targets/ARCH/ORAN_FHI/lib/xran_compression.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/*!
+    \file   xran_compression.h
+    \brief  External API for compading with the use BFP algorithm.
+*/
+
+#ifndef _XRAN_COMPRESSION_H_
+#define _XRAN_COMPRESSION_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+    \struct xranlib_compress_request
+    \brief Request structure containing pointer to data and its length.
+*/
+struct xranlib_compress_request {
+    int16_t *data_in;   /*!< Pointer to data to compress. */
+    int16_t numRBs;     /*!< numRBs  */
+    int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */
+    int16_t compMethod; /*!< Compression method */
+    int16_t iqWidth;    /*!< Bit size */
+    int32_t len;        /*!< Length of input buffer in bytes */
+};
+
+/*!
+    \struct xranlib_compress_response
+    \brief Response structure containing pointer to data and its length.
+*/
+struct xranlib_compress_response {
+    int8_t *data_out; /*!< Pointer to data after compression. */
+
+    int32_t len; /*!< Length of output data. */
+};
+
+/*!
+    \struct xranlib_decompress_request
+    \brief Request structure containing pointer to data and its length.
+*/
+struct xranlib_decompress_request {
+    int8_t *data_in; /*!< Pointer to data to decompress. */
+    int16_t numRBs;     /*!< numRBs  */
+    int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */
+    int16_t compMethod; /*!< Compression method */
+    int16_t iqWidth;    /*!< Bit size */
+
+    int32_t len; /*!< Length of input data. */
+};
+
+/*!
+    \struct xranlib_decompress_response
+    \brief Response structure containing pointer to data and its length.
+*/
+struct xranlib_decompress_response {
+    int16_t *data_out; /*!< Pointer to data after decompression. */
+
+    int32_t len; /*!< Length of output data. */
+};
+
+/*!
+    \brief Report the version number for the xranlib_companding library.
+    \param [in] version Pointer to a char buffer where the version string should be copied.
+    \param [in] buffer_size The length of the string buffer, must be at least
+               xranlib_SDK_VERSION_STRING_MAX_LEN characters.
+    \return 0 if the version string was populated, otherwise -1.
+*/
+int16_t
+xranlib_companding_version(char *version, int buffer_size);
+
+//! @{
+/*!
+    \brief Compress functions - it converts a 16-bit linear PCM value to 8-bt A-law.
+    \param [in]  request Structure containing the input data and data length.
+    \param [out] response Structure containing the output data and data length.
+    \return 0 for success, -1 for error
+*/
+int32_t
+xranlib_compress(const struct xranlib_compress_request *request,
+    struct xranlib_compress_response *response);
+int32_t
+xranlib_compress_sse(const struct xranlib_compress_request *request,
+    struct xranlib_compress_response *response);
+int32_t
+xranlib_compress_avx2(const struct xranlib_compress_request *request,
+    struct xranlib_compress_response *response);
+int32_t
+xranlib_compress_avx512(const struct xranlib_compress_request *request,
+    struct xranlib_compress_response *response);
+int32_t
+xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request,
+    struct xranlib_compress_response *response);
+//! @}
+
+//! @{
+/*!
+    \brief Decompress function - it converts an A-law value to 16-bit linear PCM.
+    \param [in] request Structure containing the input data and data length.
+    \param [out] response Structure containing the output data and data length.
+    \return 0 for success, -1 for error.
+**/
+int32_t
+xranlib_decompress(const struct xranlib_decompress_request *request,
+    struct xranlib_decompress_response *response);
+
+int32_t
+xranlib_decompress_sse(const struct xranlib_decompress_request *request,
+    struct xranlib_decompress_response *response);
+int32_t
+xranlib_decompress_avx2(const struct xranlib_decompress_request *request,
+    struct xranlib_decompress_response *response);
+int32_t
+xranlib_decompress_avx512(const struct xranlib_decompress_request *request,
+    struct xranlib_decompress_response *response);
+int32_t
+xranlib_decompress_avx512_bfw(const struct xranlib_decompress_request *request,
+     struct xranlib_decompress_response *response);
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XRAN_COMPRESSION_H_ */

targets/ARCH/ORAN_FHI/lib/xran_compression.hpp

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+#pragma once
+#include <stdint.h>
+#include <immintrin.h>
+
+// This configuration file sets global constants and macros which are
+// of general use throughout the project.
+
+// All current IA processors of interest align their cache lines on
+// this boundary. If the cache alignment for future processors changes
+// then the most restrictive alignment should be set.
+constexpr unsigned k_cacheByteAlignment = 64;
+
+// Force the data to which this macro is applied to be aligned on a cache line.
+// For example:
+//
+// CACHE_ALIGNED float data[64];
+#define CACHE_ALIGNED alignas(k_cacheByteAlignment)
+
+// Hint to the compiler that the data to which this macro is applied
+// can be assumed to be aligned to a cache line. This allows the
+// compiler to generate improved code by using aligned reads and
+// writes.
+#define ASSUME_CACHE_ALIGNED(data)
+// __assume_aligned(data, k_cacheByteAlignment);
+
+/// Intel compiler frequently complains about templates not being declared in an external
+/// header. Templates are used throughout this project's source files to define local type-specific
+/// versions of functions. Defining every one of these in a header is unnecessary, so the warnings
+/// about this are turned off globally.
+#pragma warning(disable:1418)
+#pragma warning(disable:1419)
+
+
+namespace BlockFloatCompander
+{
+  /// Compute 32 RB at a time
+  static constexpr int k_numBitsIQ = 16;
+  static constexpr int k_numBitsIQPair = 2 * k_numBitsIQ;
+  static constexpr int k_maxNumBlocks = 16;
+  static constexpr int k_maxNumElements = 128;
+  static constexpr int k_numSampsExpanded = k_maxNumBlocks * k_maxNumElements;
+  static constexpr int k_numSampsCompressed = (k_numSampsExpanded * 2) + k_maxNumBlocks;
+
+  struct CompressedData
+  {
+    /// Compressed data
+    CACHE_ALIGNED uint8_t dataCompressedDataOut[k_numSampsCompressed];
+    CACHE_ALIGNED uint8_t *dataCompressed;
+    /// Size of mantissa including sign bit
+    int iqWidth;
+
+    /// Number of BFP blocks in message
+    int numBlocks;
+
+    /// Number of data elements per compression block (only required for reference function)
+    int numDataElements;
+  };
+
+  struct ExpandedData
+  {
+    /// Expanded data or input data to compressor
+    CACHE_ALIGNED int16_t dataExpandedIn[k_numSampsExpanded];
+    CACHE_ALIGNED int16_t *dataExpanded;
+
+    /// Size of mantissa including sign bit
+    int iqWidth;
+
+    /// Number of BFP blocks in message
+    int numBlocks;
+
+    /// Number of data elements per compression block (only required for reference function)
+    int numDataElements;
+  };
+
+  /// Reference compression and expansion functions
+  void BFPCompressRef(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandRef(const CompressedData& dataIn, ExpandedData* dataOut);
+
+  /// User-Plane specific compression and expansion functions
+  void BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut);
+
+  /// Control-Plane specific compression and expansion functions for 8 antennas
+  void BFPCompressCtrlPlane8Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandCtrlPlane8Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
+
+  /// Control-Plane specific compression and expansion functions for 16 antennas
+  void BFPCompressCtrlPlane16Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandCtrlPlane16Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
+
+  /// Control-Plane specific compression and expansion functions for 32 antennas
+  void BFPCompressCtrlPlane32Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandCtrlPlane32Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
+
+  /// Control-Plane specific compression and expansion functions for 64 antennas
+  void BFPCompressCtrlPlane64Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+  void BFPExpandCtrlPlane64Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
+}
+

targets/ARCH/ORAN_FHI/lib/xran_frame_struct.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+
+/**
+ * @brief Header file for function to work with 5G NR frame structure and related
+ *        routines
+ * @file xran_frame_struct.h
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#ifndef _XRAN_FRAME_STRUCT_
+#define _XRAN_FRAME_STRUCT_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "xran_fh_o_du.h"
+
+uint32_t xran_fs_get_tti_interval(uint8_t nMu);
+uint32_t xran_fs_get_scs(uint8_t nMu);
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_nr5g_source_phy_common
+ *
+ *  @param[in]   nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz,  1: 30khz,  2: 60khz 3: 120khz, 4: 240khz
+ *  @param[in]   nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
+ *  @param[in]   nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+ *
+ *  @return  Number of RBs in cell
+ *
+ *  @description
+ *  Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint16_t xran_fs_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA);
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup phy_cal_nrarfcn
+ *
+ *  @param[in]   center frequency
+ *
+ *  @return  NR-ARFCN
+ *
+ *  @description
+ *  This calculates NR-ARFCN value according to center frequency
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq);
+int32_t xran_fs_slot_limit(int32_t nSlotIdx);
+void xran_fs_clear_slot_type(uint32_t nCcId);
+int32_t xran_fs_set_slot_type(uint32_t nCcId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig);
+int32_t xran_fs_get_slot_type(int32_t nCcId, int32_t nSlotIdx, int32_t nType);
+uint32_t xran_fs_slot_limit_init(int32_t tti_interval_us);
+uint32_t xran_fs_get_max_slot(void);
+uint32_t xran_fs_get_max_slot_SFN(void);
+int32_t xran_fs_get_symbol_type(int32_t nCellIdx, int32_t nSlotdx,  int32_t nSymbIdx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XRAN_FRAME_STRUCT_ */
+

targets/ARCH/ORAN_FHI/lib/xran_lib_mlog_tasks_id.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has the System Debug Trace Logger (Mlog) Task IDs used by XRAN library
+ * @file mlog_task_id.h
+ * @ingroup group_lte_source_common
+ * @author Intel Corporation
+ **/
+
+#ifndef _XRAN_TASK_ID_H_
+#define _XRAN_TASK_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RESOURCE_CORE_0                             0
+#define RESOURCE_CORE_1                             1
+#define RESOURCE_CORE_2                             2
+#define RESOURCE_CORE_3                             3
+#define RESOURCE_CORE_4                             4
+#define RESOURCE_CORE_5                             5
+#define RESOURCE_CORE_6                             6
+#define RESOURCE_CORE_7                             7
+#define RESOURCE_CORE_8                             8
+#define RESOURCE_CORE_9                             9
+#define RESOURCE_CORE_10                            10
+#define RESOURCE_CORE_11                            11
+#define RESOURCE_CORE_12                            12
+#define RESOURCE_CORE_13                            13
+#define RESOURCE_CORE_14                            14
+#define RESOURCE_CORE_15                            15
+#define RESOURCE_CORE_16                            16
+
+#define RESOURCE_IA_CORE                            100
+
+//--------------------------------------------------------------------
+// XRAN
+//--------------------------------------------------------------------
+
+//--------------------------------------------------------------------
+// POLLING
+//--------------------------------------------------------------------
+#define PID_XRAN_BBDEV_DL_POLL                  51
+#define PID_XRAN_BBDEV_DL_POLL_DISPATCH         52
+#define PID_XRAN_BBDEV_UL_POLL                  53
+#define PID_XRAN_BBDEV_UL_POLL_DISPATCH         54
+
+#define PID_TTI_TIMER                           2100
+#define PID_TTI_CB                              2101
+
+#define PID_SYM_TIMER                           2102
+#define PID_GNB_PROC_TIMING_TIMEOUT             2103
+
+#define PID_TIME_SYSTIME_POLL                   2104
+#define PID_TIME_SYSTIME_STOP                   2105
+#define PID_TIME_ARM_TIMER                      2106
+#define PID_TIME_ARM_TIMER_DEADLINE             2107
+
+
+
+#define PID_RADIO_FREQ_RX_PKT                   2400
+#define PID_RADIO_RX_STOP                       2401
+#define PID_RADIO_RX_UL_IQ                      2402
+#define PID_RADIO_PRACH_PKT                     2403
+#define PID_RADIO_FE_COMPRESS                   2404
+#define PID_RADIO_FE_DECOMPRESS                 2405
+#define PID_RADIO_TX_BYPASS_PROC                2406
+#define PID_RADIO_ETH_TX_BURST                  2407
+#define PID_RADIO_TX_DL_IQ                      2408
+#define PID_RADIO_RX_VALIDATE                   2409
+
+#define PID_RADIO_RX_IRQ_ON                     2410
+#define PID_RADIO_RX_IRQ_OFF                    2411
+#define PID_RADIO_RX_EPOLL_WAIT                 2412
+
+#define PID_RADIO_TX_LTEMODE_PROC               2413
+#define PID_RADIO_RX_LTEMODE_PROC               2414
+
+#define PID_RADIO_TX_PLAY_BACK_IQ               2415
+
+#define PID_PROCESS_TX_SYM                      2416
+
+#define PID_CP_DL_CB                               2500
+#define PID_CP_UL_CB                               2501
+#define PID_UP_DL_CB                               2502
+#define PID_SYM_OTA_CB                             2503
+#define PID_TTI_CB_TO_PHY                          2504
+#define PID_HALF_SLOT_CB_TO_PHY                    2505
+#define PID_FULL_SLOT_CB_TO_PHY                    2506
+#define PID_UP_UL_HALF_DEAD_LINE_CB                2507
+#define PID_UP_UL_FULL_DEAD_LINE_CB                2508
+
+#define PID_PROCESS_UP_PKT                      2600
+#define PID_PROCESS_CP_PKT                      2700
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XRAN_TASK_ID_H_ */
+

targets/ARCH/ORAN_FHI/lib/xran_mlog_lnx.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+#ifndef _XRAN_MLOG_LNX_H_
+#define _XRAN_MLOG_LNX_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef MLOG_ENABLED
+#include <mlog_lnx.h>
+#else
+
+/* stubs for MLOG functions */
+#define MLOG_FALSE                  ( 0 )
+
+#define MLogOpen(a, b, c, d, e)     MLOG_FALSE
+#define MLogRestart(a)              MLOG_FALSE
+#define MLogPrint(a)                MLOG_FALSE
+#define MLogGetFileLocation()       NULL
+#define MLogGetFileSize()           0
+#define MLogSetMask(a)              MLOG_FALSE
+#define MLogGetMask()
+#define MLogRegisterTick()
+#define MLogTick()                  0
+#define MLogIncrementCounter()      0
+#define MLogTask(w,x,y)             0
+#define MLogTaskCore(w,x,y,z)       0
+#define MLogMark(x,y)
+#define MLogDevInfo(x)
+#define MLogRegisterFrameSubframe(x,y)
+#define MLogAddVariables(x,y,z)
+#define MLogGetStats(a, b, c, d, e) MLOG_FALSE
+#define MLogGetAvgStats(a, b, c, d) MLOG_FALSE
+#define MLogAddTestCase(a, b)       MLOG_FALSE
+#define MLogAddPowerStats(a, b, c, d, e) MLOG_FALSE
+
+#endif /* MLOG_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif /* #ifdef __cplusplus */
+
+#endif  /* #ifndef _XRAN_MLOG_LNX_H_ */
+

targets/ARCH/ORAN_FHI/lib/xran_mlog_task_id.h

+/******************************************************************************
+*
+*   Copyright (c) 2020 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has the System Debug Trace Logger (Mlog) Task IDs used by PHY
+ * @file mlog_task_id.h
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#ifndef _XRAN_TASK_ID_H_
+#define _XRAN_TASK_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RESOURCE_CORE_0                             0
+#define RESOURCE_CORE_1                             1
+#define RESOURCE_CORE_2                             2
+#define RESOURCE_CORE_3                             3
+#define RESOURCE_CORE_4                             4
+#define RESOURCE_CORE_5                             5
+#define RESOURCE_CORE_6                             6
+#define RESOURCE_CORE_7                             7
+#define RESOURCE_CORE_8                             8
+#define RESOURCE_CORE_9                             9
+#define RESOURCE_CORE_10                            10
+#define RESOURCE_CORE_11                            11
+#define RESOURCE_CORE_12                            12
+#define RESOURCE_CORE_13                            13
+#define RESOURCE_CORE_14                            14
+#define RESOURCE_CORE_15                            15
+#define RESOURCE_CORE_16                            16
+
+#define RESOURCE_IA_CORE                            100
+
+//--------------------------------------------------------------------
+// XRAN APP
+//--------------------------------------------------------------------
+
+#define PID_GNB_PROC_TIMING                             70
+#define PID_GNB_PROC_TIMING_TIMEOUT                     71
+#define PID_GNB_SYM_CB                                  72
+#define PID_GNB_PRACH_CB                                73
+#define PID_GNB_SRS_CB                                  74
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XRAN_TASK_ID_H_ */
+

targets/ARCH/ORAN_FHI/lib/xran_pkt.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief Definitions and support functions to process XRAN packet
+ * @file xran_pkt.h
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+/* ORAN-WG4.CUS.0-v01.00 O-RAN Fronthaul Working Group
+                         Control, User and Synchronization Plane Specification
+*/
+
+/*
+ * Layer common to data and control packets
+ */
+
+#ifndef _XRAN_PKT_H_
+#define _XRAN_PKT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include <rte_ether.h>
+#include <rte_byteorder.h>
+
+/**
+ *****************************************************************************
+ * @file xran_pkt.h
+ *
+ * @defgroup xran_common_pkt XRAN Packet definitions and functions
+ * @ingroup xran
+ *
+ * @description
+ *      Definitions and support functions to process XRAN packet
+ *****************************************************************************/
+
+#define ECPRI_MAX_PAYLOAD_SIZE 65535 /**< Max packet size taken in this implementation */
+
+/* XRAN spec: For this encapsulation, either the eCPRI Ethertype or the IEEE 1914.3 Ethertype shall be use */
+#define XRAN_ETHER_TYPE 0xAEFE /**< defined by eCPRI Specification V1.1 */
+
+#define XRAN_ECPRI_VER      0x0001      /**< eCPRI protocol revision 3.1.3.1.1 */
+#define XRAN_PAYLOAD_VER    0x0001      /**< Payload version 5.4.4.2 */
+
+#define VLAN_ID  0 /**< Default Tag protocol identifier (TPID)*/
+#define VLAN_PCP 7 /**< U-Plane and C-Plane only see Table 3 5 : Quality of service classes */
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       eCPRI message types
+ *       as per eCPRI spec 3.2.4. Message Types
+ *****************************************************************************/
+enum ecpri_msg_type
+{
+     ECPRI_IQ_DATA           = 0x00, /**< U-plane: IQ data */
+     ECPRI_BIT_SEQUENCE      = 0x01, /* msg type is not supported */
+     ECPRI_RT_CONTROL_DATA   = 0x02, /**< C-plane: Control */
+
+     /* Below msg types are not supported */
+     ECPRI_GEN_DATA_TRANSFER = 0x03,
+     ECPRI_REMOTE_MEM_ACCESS = 0x04,
+     ECPRI_DELAY_MEASUREMENT = 0x05,
+     ECPRI_REMOTE_RESET      = 0x06,
+     ECPRI_EVENT_INDICATION  = 0x07,
+     ECPRI_MSG_TYPE_MAX
+};
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       see 3.1.3.1.7 ecpriSeqid (message identifier)
+ *****************************************************************************/
+struct ecpri_seq_id
+{
+    uint8_t seq_id:8;       /**< Sequence ID */
+    uint8_t sub_seq_id:7;   /**< Subsequence ID */
+    uint8_t e_bit:1;        /**< E bit */
+} __rte_packed;
+
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       Structure holds common eCPRI header as per
+ *       Table 3 1 : eCPRI Transport Header Field Definitions
+ *****************************************************************************/
+struct xran_ecpri_cmn_hdr
+{
+    uint8_t     ecpri_concat:1;     /**< 3.1.3.1.3 eCPRI concatenation indicator */
+    uint8_t     ecpri_resv:3;       /**< 3.1.3.1.2 eCPRI reserved */
+    uint8_t     ecpri_ver:4;        /**< 3.1.3.1.1 eCPRI protocol revision, defined in XRAN_ECPRI_VER */
+    uint8_t     ecpri_mesg_type;    /**< 3.1.3.1.4 eCPRI message type, defined in ecpri_msg_type */
+    uint16_t    ecpri_payl_size;    /**< 3.1.3.1.5 eCPRI payload size, without common header and any padding bytes */
+} __rte_packed;
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       Structure holds eCPRI transport header as per
+ *       Table 3 1 : eCPRI Transport Header Field Definitions
+ *****************************************************************************/
+struct xran_ecpri_hdr
+{
+    struct xran_ecpri_cmn_hdr cmnhdr;
+    rte_be16_t ecpri_xtc_id;            /**< 3.1.3.1.6 real time control data / IQ data transfer message series identifier */
+    struct ecpri_seq_id ecpri_seq_id;   /**< 3.1.3.1.7 message identifier */
+} __rte_packed;
+
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *      Enum used to set xRAN packet data direction (gNB Tx/Rx 5.4.4.1)
+ *      uplink or downlink
+ *****************************************************************************/
+enum xran_pkt_dir
+{
+     XRAN_DIR_UL  = 0, /**< UL direction */
+     XRAN_DIR_DL  = 1, /**< DL direction */
+     XRAN_DIR_MAX
+};
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       Structure holds components of radio application header
+ *       5.4.4 Coding of Information Elements - Application Layer, Common
+ *       for U-plane as per 6.3.2	DL/UL Data
+ *****************************************************************************/
+struct radio_app_common_hdr
+{
+   /* Octet 9 */
+   uint8_t filter_id:4; /**< This parameter defines an index to the channel filter to be
+                              used between IQ data and air interface, both in DL and UL.
+                              For most physical channels filterIndex =0000b is used which
+                              indexes the standard channel filter, e.g. 100MHz channel filter
+                              for 100MHz nominal carrier bandwidth. (see 5.4.4.3 for more) */
+   uint8_t payl_ver:3; /**< This parameter defines the payload protocol version valid
+                            for the following IEs in the application layer. In this version of
+                            the specification payloadVersion=001b shall be used. */
+   uint8_t data_direction:1; /**< This parameter indicates the gNB data direction. */
+
+   /* Octet 10 */
+   uint8_t frame_id:8;    /**< This parameter is a counter for 10 ms frames (wrapping period 2.56 seconds) */
+
+   /* Octet 11 */
+   /* Octet 12 */
+   union {
+       uint16_t value;
+       struct {
+           uint16_t symb_id:6; /**< This parameter identifies the first symbol number within slot,
+                                          to which the information of this message is applies. */
+           uint16_t slot_id:6; /**< This parameter is the slot number within a 1ms sub-frame. All slots in
+                                   one sub-frame are counted by this parameter, slotId running from 0 to Nslot-1.
+                                   In this version of the specification the maximum Nslot=16, All
+                                   other values of the 6 bits are reserved for future use. */
+           uint16_t subframe_id:4; /**< This parameter is a counter for 1 ms sub-frames within 10ms frame. */
+       };
+   }sf_slot_sym;
+
+} __rte_packed;
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *      This parameter defines the compression method and IQ bit width for the
+ *      user data in the data section.  This field is absent from U-Plane messages
+ *      when the static IQ format and compression method is configured via the M-Plane.
+ *      In this way a single compression method and IQ bit width is provided
+ *     (per UL and DL, per LTE and NR) without adding more overhead to U-Plane messages.
+ *****************************************************************************/
+struct compression_hdr
+{
+    uint8_t ud_comp_meth:4;
+    /**< udCompMeth|  compression method         |udIqWidth meaning
+    ---------------+-----------------------------+--------------------------------------------
+    0000b          | no compression              |bitwidth of each uncompressed I and Q value
+    0001b          | block floating point        |bitwidth of each I and Q mantissa value
+    0010b          | block scaling               |bitwidth of each I and Q scaled value
+    0011b          | mu-law                      |bitwidth of each compressed I and Q value
+    0100b          | modulation compression      |bitwidth of each compressed I and Q value
+    0100b - 1111b  | reserved for future methods |depends on the specific compression method
+    */
+    uint8_t ud_iq_width:4; /**< Bit width of each I and each Q
+                                16 for udIqWidth=0, otherwise equals udIqWidth e.g. udIqWidth = 0000b means I and Q are each 16 bits wide;
+                                e.g. udIQWidth = 0001b means I and Q are each 1 bit wide;
+                                e.g. udIqWidth = 1111b means I and Q are each 15 bits wide
+                                */
+} __rte_packed;
+
+/**
+ ******************************************************************************
+ * @ingroup xran_common_pkt
+ *
+ * @description
+ *       Structure holds common xran packet header
+ *       3.1.1	Ethernet Encapsulation
+ *****************************************************************************/
+struct xran_pkt_comm_hdr
+{
+    struct rte_ether_hdr eth_hdr; /**< Ethernet Header */
+    struct xran_ecpri_hdr ecpri_hdr; /**< eCPRI Transport Header */
+} __rte_packed;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/ARCH/ORAN_FHI/lib/xran_printf.h

+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief Modules provide debug prints and utility functions
+ * @file xran_printf.h
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#ifndef XRAN_PRINTF_H
+#define XRAN_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdio.h>
+#include <stdlib.h>
+
+#define PRINTF_LOG_OK
+#define PRINTF_INF_OK
+#define PRINTF_ERR_OK
+//#define PRINTF_DBG_OK
+
+#ifndef WIN32
+#ifdef PRINTF_LOG_OK
+#define print_log(fmt, args...) printf("%s:" fmt "\n", __FUNCTION__, ## args)
+#else  /* PRINTF_LOG_OK */
+#define print_log(fmt, args...)
+#endif  /* PRINTF_LOG_OK */
+#else
+#define print_log(fmt, ...) printf("%s:" fmt "\n", __FUNCTION__, __VA_ARGS__)
+#endif
+
+#ifndef WIN32
+#ifdef PRINTF_DBG_OK
+#define print_dbg(fmt, args...) printf("%s:[dbg] " fmt "\n", __FUNCTION__, ## args)
+#else  /* PRINTF_LOG_OK */
+#define print_dbg(fmt, args...)
+#endif  /* PRINTF_LOG_OK */
+#else
+#define print_dbg(fmt, ...) printf("%s:[dbg] " fmt "\n", __FUNCTION__, __VA_ARGS__)
+#endif
+
+#ifndef WIN32
+#ifdef PRINTF_ERR_OK
+#define print_err(fmt, args...) printf("%s:[err] " fmt "\n", __FUNCTION__, ## args)
+#else  /* PRINTF_LOG_OK */
+#define print_err(fmt, args...)
+#endif  /* PRINTF_LOG_OK */
+#else
+#define print_err(fmt, ...) printf("%s:[err] " fmt "\n", __FUNCTION__, __VA_ARGS__)
+#endif
+
+#ifndef WIN32
+#ifdef PRINTF_INF_OK
+#define print_inf               printf
+#else  /* PRINTF_LOG_OK */
+#define print_inf
+#endif  /* PRINTF_LOG_OK */
+#else
+#define print_inf               printf
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifndef _IASSERT_
+#define _IASSERT_
+
+#ifdef _DEBUG
+#define iAssert(p) if(!(p)){fprintf(stderr,\
+    "Assertion failed: %s, file %s, line %d, val %d\n",\
+    #p, __FILE__, __LINE__, p);exit(-1);}
+#else /* _DEBUG */
+#define iAssert(p)
+#endif /* _DEBUG */
+
+#ifndef PHY_APP
+#ifndef _assert
+#define _assert(x)
+#endif
+#endif
+
+#endif /* _IASSERT_*/
+
+#ifdef CHECK_PARAMS
+#define CHECK_NOT_NULL(param, returnValue)      \
+if (param == NULL)                          \
+{                                           \
+    print_err("%s is NULL!\n", #param);   \
+    return returnValue;                     \
+}
+#else
+#define CHECK_NOT_NULL(param, returnValue)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PHY_PRINTF_H