Commit f086c07c authored by Francesco's avatar Francesco

Merge remote-tracking branch 'origin/NR_RRCConfiguration' into NR_RRC_CP_bugfix

parents ef0aad0d 9c75cda8
...@@ -1260,7 +1260,7 @@ function start_rf_sim_nr_ue { ...@@ -1260,7 +1260,7 @@ function start_rf_sim_nr_ue {
echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
if [ $LOC_S1_CONFIGURATION -eq 0 ] if [ $LOC_S1_CONFIGURATION -eq 0 ]
then then
echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --numerology 1 -C ${LOC_FREQUENCY}000000 -r $LOC_PRB --nokrnmod 1 --rfsim --phy-test --rcc_config_path /home/ubuntu/tmp/ci-scripts/rcc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --numerology 1 -C ${LOC_FREQUENCY}000000 -r $LOC_PRB --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/ci-scripts/rrc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1
fi fi
echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1 echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1
echo "cat ./my-nr-softmodem-run.sh" >> $1 echo "cat ./my-nr-softmodem-run.sh" >> $1
......
...@@ -127,7 +127,7 @@ endfunction() ...@@ -127,7 +127,7 @@ endfunction()
#set(CMAKE_BUILD_TYPE "Debug") #set(CMAKE_BUILD_TYPE "Debug")
if (CMAKE_BUILD_TYPE STREQUAL "") if (CMAKE_BUILD_TYPE STREQUAL "")
set(CMAKE_BUILD_TYPE "Release") set(CMAKE_BUILD_TYPE "RelWithDebInfo")
endif() endif()
message("CMAKE_BUILD_TYPE is ${CMAKE_BUILD_TYPE}") message("CMAKE_BUILD_TYPE is ${CMAKE_BUILD_TYPE}")
add_list_string_option(CMAKE_BUILD_TYPE "RelWithDebInfo" "Choose the type of build, options are: None(CMAKE_CXX_FLAGS or CMAKE_C_FLAGS used) Debug Release RelWithDebInfo MinSizeRel." Debug Release RelWithDebInfo MinSizeRel) add_list_string_option(CMAKE_BUILD_TYPE "RelWithDebInfo" "Choose the type of build, options are: None(CMAKE_CXX_FLAGS or CMAKE_C_FLAGS used) Debug Release RelWithDebInfo MinSizeRel." Debug Release RelWithDebInfo MinSizeRel)
...@@ -2766,7 +2766,6 @@ target_link_libraries(nr_pucchsim ...@@ -2766,7 +2766,6 @@ target_link_libraries(nr_pucchsim
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
) )
#PUCCH ---> Prashanth
add_executable(nr_dlsim add_executable(nr_dlsim
${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlsim.c ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlsim.c
......
...@@ -1089,25 +1089,29 @@ ...@@ -1089,25 +1089,29 @@
(Test8: 217 PRB 100 PDSCH-PRBs), (Test8: 217 PRB 100 PDSCH-PRBs),
(Test9: 217 PRB 80 PDSCH-Offset), (Test9: 217 PRB 80 PDSCH-Offset),
(Test10: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset), (Test10: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset),
(Test11: 106 PRBs 50 PDSCH-PRBs MCS Index 28</desc> (Test11: 106 PRBs 50 PDSCH-PRBs MCS Index 28)
(Test12: 106 PRBs 50 PDSCH-PRBs MCS Index 16)</desc>
<pre_compile_prog></pre_compile_prog> <pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog> <compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args> <compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec> <pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args> <pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_dlsim.Rel15</main_exec> <main_exec> $OPENAIR_DIR/targets/bin/nr_dlsim.Rel15</main_exec>
<main_exec_args>-n100 -R106 -b106 <main_exec_args>
-n100 -R217 -b217 -n100 -R106 -b106 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R273 -b273 -n100 -R217 -b217 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R106 -o12 -n100 -R273 -b273 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R217 -o48 -n100 -R106 -o12 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R106 -a25 -n100 -R217 -o48 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R106 -a51 -n100 -R106 -a25 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R217 -b100 -n100 -R106 -a51 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R217 -a80 -n100 -R217 -b100 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -R217 -a110 -b100 -n100 -R217 -a80 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -e28</main_exec_args> -n100 -R217 -a110 -s5 -b100 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11</tags> -n100 -e28 -s20 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-n100 -e16 -s10 -s5 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
</main_exec_args>
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12</tags>
<search_expr_true>PDSCH test OK</search_expr_true> <search_expr_true>PDSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false> <search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns> <nruns>3</nruns>
...@@ -1249,11 +1253,11 @@ ...@@ -1249,11 +1253,11 @@
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec> <pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args> <pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_ulsim.Rel15</main_exec> <main_exec> $OPENAIR_DIR/targets/bin/nr_ulsim.Rel15</main_exec>
<main_exec_args>-f100 -m9 -r106 -s10 <main_exec_args>-n100 -m9 -r106 -s0 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-f100 -m16 -s20 -n100 -m16 -s10 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-f100 -m28 -s30 -n100 -m28 -s20 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-f100 -m9 -R217 -r217 -s10 -n100 -m9 -R217 -r217 -s0 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw
-f100 -m9 -R273 -r273 -s10</main_exec_args> -n100 -m9 -R273 -r273 -s0 -f $OPENAIR_DIR/ci-scripts/rrc-files/reconfig.raw</main_exec_args>
<tags>nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5</tags> <tags>nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5</tags>
<search_expr_true>PUSCH test OK</search_expr_true> <search_expr_true>PUSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false> <search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
......
...@@ -480,8 +480,6 @@ int wakeup_txfh(PHY_VARS_gNB *gNB,gNB_L1_rxtx_proc_t *proc,int frame_tx,int slot ...@@ -480,8 +480,6 @@ int wakeup_txfh(PHY_VARS_gNB *gNB,gNB_L1_rxtx_proc_t *proc,int frame_tx,int slot
} }
AssertFatal((ret = pthread_mutex_lock(&ru_proc->mutex_gNBs))==0,"ERROR pthread_mutex_lock failed on mutex_gNBs L1_thread_tx with ret=%d\n",ret); AssertFatal((ret = pthread_mutex_lock(&ru_proc->mutex_gNBs))==0,"ERROR pthread_mutex_lock failed on mutex_gNBs L1_thread_tx with ret=%d\n",ret);
AssertFatal((ret=pthread_mutex_lock(&ru_proc->mutex_gNBs))==0,"mutex_lock returned %d\n",ret);
ru_proc->instance_cnt_gNBs = 0; ru_proc->instance_cnt_gNBs = 0;
ru_proc->timestamp_tx = timestamp_tx; ru_proc->timestamp_tx = timestamp_tx;
ru_proc->tti_tx = slot_tx; ru_proc->tti_tx = slot_tx;
......
...@@ -760,6 +760,18 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { ...@@ -760,6 +760,18 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
flags = 3; // end of burst flags = 3; // end of burst
} }
if (fp->freq_range==nr_FR2) {
// the beam index is written in bits 8-10 of the flags
// bit 11 enables the gpio programming
int beam=0;
if (slot==0 || slot==40) beam=0&8;
if (slot==10 || slot==50) beam=1&8;
if (slot==20 || slot==60) beam=2&8;
if (slot==30 || slot==70) beam=3&8;
flags |= beam<<8;
}
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_WRITE_FLAGS, flags ); VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_WRITE_FLAGS, flags );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame ); VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot ); VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot );
......
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#define MAX_TURBO_ITERATIONS_MBSFN 8 #define MAX_TURBO_ITERATIONS_MBSFN 8
#define MAX_TURBO_ITERATIONS max_turbo_iterations #define MAX_TURBO_ITERATIONS max_turbo_iterations
#define MAX_LDPC_ITERATIONS 10//5 #define MAX_LDPC_ITERATIONS 5
#define MAX_LDPC_ITERATIONS_MBSFN 4 #define MAX_LDPC_ITERATIONS_MBSFN 4
#define LTE_NULL 2 #define LTE_NULL 2
......
...@@ -360,12 +360,16 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, ...@@ -360,12 +360,16 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
nfapi_nr_config_request_scf_t *gNB_config = &gNB->gNB_config; nfapi_nr_config_request_scf_t *gNB_config = &gNB->gNB_config;
//overwrite for new NR parameters //overwrite for new NR parameters
uint64_t rev_burst=0;
for (int i=0; i<64; i++)
rev_burst |= (((position_in_burst>>(63-i))&0x01)<<i);
gNB_config->cell_config.phy_cell_id.value = Nid_cell; gNB_config->cell_config.phy_cell_id.value = Nid_cell;
gNB_config->ssb_config.scs_common.value = mu; gNB_config->ssb_config.scs_common.value = mu;
gNB_config->ssb_table.ssb_subcarrier_offset.value = 0; gNB_config->ssb_table.ssb_subcarrier_offset.value = 0;
gNB_config->ssb_table.ssb_offset_point_a.value = (N_RB_DL-20)>>1; gNB_config->ssb_table.ssb_offset_point_a.value = (N_RB_DL-20)>>1;
gNB_config->ssb_table.ssb_mask_list[0].ssb_mask.value = position_in_burst; gNB_config->ssb_table.ssb_mask_list[1].ssb_mask.value = (rev_burst)&(0xFFFFFFFF);
gNB_config->ssb_table.ssb_mask_list[1].ssb_mask.value = position_in_burst>>32; gNB_config->ssb_table.ssb_mask_list[0].ssb_mask.value = (rev_burst>>32)&(0xFFFFFFFF);
gNB_config->cell_config.frame_duplex_type.value = TDD; gNB_config->cell_config.frame_duplex_type.value = TDD;
gNB_config->ssb_table.ssb_period.value = 1; //10ms gNB_config->ssb_table.ssb_period.value = 1; //10ms
gNB_config->carrier_config.dl_grid_size[mu].value = N_RB_DL; gNB_config->carrier_config.dl_grid_size[mu].value = N_RB_DL;
...@@ -381,6 +385,9 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, ...@@ -381,6 +385,9 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000); fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000);
fp->nr_band = 78; fp->nr_band = 78;
fp->threequarter_fs= 0; fp->threequarter_fs= 0;
gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band);
nr_init_frame_parms(gNB_config, fp); nr_init_frame_parms(gNB_config, fp);
gNB->configured = 1; gNB->configured = 1;
LOG_I(PHY,"gNB configured\n"); LOG_I(PHY,"gNB configured\n");
......
...@@ -148,21 +148,21 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw) ...@@ -148,21 +148,21 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw)
break; break;
case 90: case 90:
AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for N_RB %d and MU %d\n",fp->N_RB_DL,mu); AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for %d MHz band and MU %d\n",bw,mu);
fp->ofdm_symbol_size = 4096; fp->ofdm_symbol_size = 4096;
fp->first_carrier_offset = 2626; //4096 - ( (245*12) / 2 ) fp->first_carrier_offset = 2626; //4096 - ( (245*12) / 2 )
fp->nb_prefix_samples0 = 352; fp->nb_prefix_samples0 = 352;
fp->nb_prefix_samples = 288; fp->nb_prefix_samples = 288;
break; break;
case 100: case 100:
AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for N_RB %d and MU %d\n",fp->N_RB_DL,mu); AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for %d MHz band and MU %d\n",bw,mu);
fp->ofdm_symbol_size = 4096; fp->ofdm_symbol_size = 4096;
fp->first_carrier_offset = 2458; //4096 - ( (273*12) / 2 ) fp->first_carrier_offset = 2458; //4096 - ( (273*12) / 2 )
fp->nb_prefix_samples0 = 352; fp->nb_prefix_samples0 = 352;
fp->nb_prefix_samples = 288; fp->nb_prefix_samples = 288;
break; break;
default: default:
AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", fp->N_RB_DL, mu, fp); AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp);
} }
break; break;
...@@ -184,7 +184,7 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw) ...@@ -184,7 +184,7 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw)
case 90: case 90:
case 100: case 100:
default: default:
AssertFatal(1==0,"Bandwidth of %d MHz undefined for mu %d, frame parms = %p\n", bw, mu, fp); AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp);
} }
break; break;
...@@ -206,7 +206,7 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw) ...@@ -206,7 +206,7 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw)
fp->nb_prefix_samples = 36; fp->nb_prefix_samples = 36;
break; break;
default: default:
AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", fp->N_RB_DL, mu, fp); AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp);
} }
break; break;
...@@ -252,7 +252,7 @@ int nr_init_frame_parms(nfapi_nr_config_request_scf_t* cfg, ...@@ -252,7 +252,7 @@ int nr_init_frame_parms(nfapi_nr_config_request_scf_t* cfg,
{ {
fp->frame_type = cfg->cell_config.frame_duplex_type.value; fp->frame_type = cfg->cell_config.frame_duplex_type.value;
fp->L_ssb = (((uint64_t) cfg->ssb_table.ssb_mask_list[1].ssb_mask.value)<<32) | cfg->ssb_table.ssb_mask_list[0].ssb_mask.value ; fp->L_ssb = (((uint64_t) cfg->ssb_table.ssb_mask_list[0].ssb_mask.value)<<32) | cfg->ssb_table.ssb_mask_list[1].ssb_mask.value ;
fp->N_RB_DL = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; fp->N_RB_DL = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value;
fp->N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; fp->N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
...@@ -385,7 +385,7 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp, ...@@ -385,7 +385,7 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp,
fp->Lmax = 64; fp->Lmax = 64;
} }
fp->L_ssb = (((uint64_t) config->ssb_table.ssb_mask_list[1].ssb_mask)<<32) | config->ssb_table.ssb_mask_list[0].ssb_mask; fp->L_ssb = (((uint64_t) config->ssb_table.ssb_mask_list[1].ssb_mask)<<32) | config->ssb_table.ssb_mask_list[1].ssb_mask;
fp->N_ssb = 0; fp->N_ssb = 0;
for (int p=0; p<fp->Lmax; p++) for (int p=0; p<fp->Lmax; p++)
......
...@@ -166,7 +166,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, ...@@ -166,7 +166,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
int k,l,k_prime,dci_idx, dmrs_idx; int k,l,k_prime,dci_idx, dmrs_idx;
/*First iteration: single DCI*/ /*First iteration: single DCI*/
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15; nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15=NULL;
// find coreset descriptor // find coreset descriptor
...@@ -273,9 +273,10 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, ...@@ -273,9 +273,10 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
/*Reorder REG list for a freq first mapping*/ /*Reorder REG list for a freq first mapping*/
uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE; uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE;
uint8_t reg_idx0 = pdcch_pdu_rel15->CceIndex[d]*NR_NB_REG_PER_CCE;
/*Mapping the encoded DCI along with the DMRS */ /*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) { for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) {
k = cset_start_sc + (12*reg_idx/cset_nsymb); k = cset_start_sc + (12*reg_idx/cset_nsymb);
if (k >= frame_parms.ofdm_symbol_size) if (k >= frame_parms.ofdm_symbol_size)
......
...@@ -684,7 +684,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ...@@ -684,7 +684,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
} }
harq_process->handled = 1; harq_process->handled = 1;
return (ulsch->max_ldpc_iterations + 1); ret = ulsch->max_ldpc_iterations + 1;
} else { } else {
...@@ -705,7 +705,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ...@@ -705,7 +705,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
{ {
LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
} }
}
// Reassembly of Transport block here // Reassembly of Transport block here
offset = 0; offset = 0;
...@@ -727,7 +726,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ...@@ -727,7 +726,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
#endif #endif
} }
}
ulsch->last_iteration_cnt = ret; ulsch->last_iteration_cnt = ret;
return(ret); return(ret);
......
...@@ -150,7 +150,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr, ...@@ -150,7 +150,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
for (int i=0; i<9; i++) { for (int i=0; i<9; i++) {
z[index_z + i] = llr[index_llr + i]; z[index_z + i] = llr[index_llr + i];
LOG_DDD("[reg=%d,bundle_j=%d] z[%d]=(%d,%d) <-> \t[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d) \n", LOG_D(PHY,"[reg=%d,bundle_j=%d] z[%d]=(%d,%d) <-> \t[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d) \n",
reg,bundle_j,(index_z + i),*(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i]), reg,bundle_j,(index_z + i),*(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i]),
f_reg,f_bundle_j,(index_llr + i),*(int16_t *) &llr[index_llr + i], *(1 + (int16_t *) &llr[index_llr + i])); f_reg,f_bundle_j,(index_llr + i),*(int16_t *) &llr[index_llr + i], *(1 + (int16_t *) &llr[index_llr + i]));
} }
...@@ -678,7 +678,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -678,7 +678,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
int n_rb,rb_offset; int n_rb,rb_offset;
get_coreset_rballoc(rel15->coreset.frequency_domain_resource,&n_rb,&rb_offset); get_coreset_rballoc(rel15->coreset.frequency_domain_resource,&n_rb,&rb_offset);
for (int s=rel15->coreset.StartSymbolIndex; s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration); s++) { for (int s=rel15->coreset.StartSymbolIndex; s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration); s++) {
LOG_DD("in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n"); LOG_D(PHY,"in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n");
nr_pdcch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[slot]].rxdataF, nr_pdcch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[slot]].rxdataF,
pdcch_vars->dl_ch_estimates, pdcch_vars->dl_ch_estimates,
...@@ -690,8 +690,8 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -690,8 +690,8 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
n_rb, n_rb,
rel15->BWPStart); rel15->BWPStart);
LOG_DD("we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP); LOG_D(PHY,"we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP);
LOG_DD("in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n"); LOG_D(PHY,"in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n");
// compute channel level based on ofdm symbol 0 // compute channel level based on ofdm symbol 0
nr_pdcch_channel_level(pdcch_vars->dl_ch_estimates_ext, nr_pdcch_channel_level(pdcch_vars->dl_ch_estimates_ext,
frame_parms, frame_parms,
...@@ -710,8 +710,8 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -710,8 +710,8 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(frame%1024), T_INT(slot), T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(frame%1024), T_INT(slot),
T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3])); T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3]));
#endif #endif
LOG_DD("we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh); LOG_D(PHY,"we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh);
LOG_DD("in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n"); LOG_D(PHY,"in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n");
// compute LLRs for ofdm symbol 0 only // compute LLRs for ofdm symbol 0 only
nr_pdcch_channel_compensation(pdcch_vars->rxdataF_ext, nr_pdcch_channel_compensation(pdcch_vars->rxdataF_ext,
pdcch_vars->dl_ch_estimates_ext, pdcch_vars->dl_ch_estimates_ext,
...@@ -722,12 +722,12 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -722,12 +722,12 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
log2_maxh, log2_maxh,
n_rb); // log2_maxh+I0_shift n_rb); // log2_maxh+I0_shift
if (frame_parms->nb_antennas_rx > 1) { if (frame_parms->nb_antennas_rx > 1) {
LOG_DD("we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", frame_parms->nb_antennas_rx); LOG_D(PHY,"we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", frame_parms->nb_antennas_rx);
nr_pdcch_detection_mrc(frame_parms, pdcch_vars->rxdataF_comp,s); nr_pdcch_detection_mrc(frame_parms, pdcch_vars->rxdataF_comp,s);
} }
LOG_DD("we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s); LOG_D(PHY,"we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s);
LOG_DD("in nr_pdcch_llr(rxdataF_comp -> llr)\n"); LOG_D(PHY,"in nr_pdcch_llr(rxdataF_comp -> llr)\n");
nr_pdcch_llr(frame_parms, nr_pdcch_llr(frame_parms,
pdcch_vars->rxdataF_comp, pdcch_vars->rxdataF_comp,
pdcch_vars->llr, pdcch_vars->llr,
...@@ -745,7 +745,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -745,7 +745,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
#endif #endif
} }
LOG_DD("we enter nr_pdcch_demapping_deinterleaving()\n"); LOG_D(PHY,"we enter nr_pdcch_demapping_deinterleaving()\n");
nr_pdcch_demapping_deinterleaving((uint32_t *) pdcch_vars->llr, nr_pdcch_demapping_deinterleaving((uint32_t *) pdcch_vars->llr,
(uint32_t *) pdcch_vars->e_rx, (uint32_t *) pdcch_vars->e_rx,
frame_parms, frame_parms,
...@@ -754,6 +754,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -754,6 +754,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
rel15->coreset.RegBundleSize, rel15->coreset.RegBundleSize,
rel15->coreset.InterleaverSize, rel15->coreset.InterleaverSize,
rel15->coreset.ShiftIndex); rel15->coreset.ShiftIndex);
/*
nr_pdcch_unscrambling(rel15->rnti, nr_pdcch_unscrambling(rel15->rnti,
frame_parms, frame_parms,
slot, slot,
...@@ -761,8 +762,9 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, ...@@ -761,8 +762,9 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
rel15->coreset.duration*n_rb*9*2, rel15->coreset.duration*n_rb*9*2,
// get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72,
rel15->coreset.pdcch_dmrs_scrambling_id); rel15->coreset.pdcch_dmrs_scrambling_id);
LOG_DD("we end nr_pdcch_unscrambling()\n"); */
LOG_DD("Ending nr_rx_pdcch() function\n"); LOG_D(PHY,"we end nr_pdcch_unscrambling()\n");
LOG_D(PHY,"Ending nr_rx_pdcch() function\n");
} }
return (0); return (0);
...@@ -798,7 +800,7 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms, ...@@ -798,7 +800,7 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms,
#ifdef NR_PDCCH_DCI_RUN #ifdef NR_PDCCH_DCI_RUN
void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id) { int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id) {
int i; int i;
uint8_t reset; uint8_t reset;
uint32_t x1, x2, s = 0; uint32_t x1, x2, s = 0;
...@@ -818,7 +820,8 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8 ...@@ -818,7 +820,8 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8
reset = 0; reset = 0;
} }
if (((s >> (i % 32)) & 1) == 1) z[i] = -z[i]; if (((s >> (i % 32)) & 1) == 1) z2[i] = -z[i];
else z2[i]=z[i];
} }
} }
...@@ -837,15 +840,29 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -837,15 +840,29 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
rel15 = &pdcch_vars->pdcch_config[i]; rel15 = &pdcch_vars->pdcch_config[i];
int dci_length = rel15->dci_length; int dci_length = rel15->dci_length;
int16_t tmp_e[16*108];
for (int j=0;j<rel15->number_of_candidates;j++) { for (int j=0;j<rel15->number_of_candidates;j++) {
LOG_D(PHY,"Trying DCI candidate %d, CCE %d (%d), L %d\n",j,rel15->CCE[j],rel15->CCE[j]*9*6*2,rel15->L[j]);
int CCEind = rel15->CCE[j]; int CCEind = rel15->CCE[j];
int L = rel15->L[j]; int L = rel15->L[j];
uint64_t dci_estimation[2]= {0}; uint64_t dci_estimation[2]= {0};
const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList); const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList);
uint16_t crc = polar_decoder_int16(&pdcch_vars->e_rx[CCEind*9*6*2],
nr_pdcch_unscrambling(rel15->rnti,
&ue->frame_parms,
slot,
&pdcch_vars->e_rx[CCEind*108],
tmp_e,
L*108,
// get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72,
rel15->coreset.pdcch_dmrs_scrambling_id);
uint16_t crc = polar_decoder_int16(tmp_e,
dci_estimation, dci_estimation,
1, 1,
currentPtrDCI); currentPtrDCI);
LOG_D(PHY,"Decoded crc %x\n",crc);
if (crc == rel15->rnti) { if (crc == rel15->rnti) {
dci_ind->SFN = frame; dci_ind->SFN = frame;
dci_ind->slot = slot; dci_ind->slot = slot;
......
...@@ -546,7 +546,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, ...@@ -546,7 +546,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
//LOG_E(PHY,"AbsSubframe %d.%d Start LDPC segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A); //LOG_E(PHY,"AbsSubframe %d.%d Start LDPC segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A);
printf("harq process dr iteration %d\n", p_decParams->numMaxIter); //printf("harq process dr iteration %d\n", p_decParams->numMaxIter);
memset(pv,0,2*harq_process->Z*sizeof(int16_t)); memset(pv,0,2*harq_process->Z*sizeof(int16_t));
//memset(pl,0,2*p_decParams->Z*sizeof(int8_t)); //memset(pl,0,2*p_decParams->Z*sizeof(int8_t));
......
...@@ -1539,7 +1539,7 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME ...@@ -1539,7 +1539,7 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME
void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi);
void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id); int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id);
......
...@@ -61,7 +61,7 @@ void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME ...@@ -61,7 +61,7 @@ void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME
sco = cfg->ssb_table.ssb_subcarrier_offset.value; sco = cfg->ssb_table.ssb_subcarrier_offset.value;
fp->ssb_start_subcarrier = (12 * cfg->ssb_table.ssb_offset_point_a.value + sco); fp->ssb_start_subcarrier = (12 * cfg->ssb_table.ssb_offset_point_a.value + sco);
LOG_I(PHY, "SSB first subcarrier %d (%d,%d)\n", fp->ssb_start_subcarrier,cfg->ssb_table.ssb_offset_point_a.value,sco); LOG_D(PHY, "SSB first subcarrier %d (%d,%d)\n", fp->ssb_start_subcarrier,cfg->ssb_table.ssb_offset_point_a.value,sco);
} }
void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) { void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) {
...@@ -95,8 +95,7 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) { ...@@ -95,8 +95,7 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) {
ssb_index = i + SSB_Table[rel_slot]; // computing the ssb_index ssb_index = i + SSB_Table[rel_slot]; // computing the ssb_index
if ((ssb_index<64) && ((fp->L_ssb >> ssb_index) & 0x01)) { // generating the ssb only if the bit of L_ssb at current ssb index is 1 if ((ssb_index<64) && ((fp->L_ssb >> (63-ssb_index)) & 0x01)) { // generating the ssb only if the bit of L_ssb at current ssb index is 1
fp->ssb_index = ssb_index; fp->ssb_index = ssb_index;
int ssb_start_symbol_abs = nr_get_ssb_start_symbol(fp); // computing the starting symbol for current ssb int ssb_start_symbol_abs = nr_get_ssb_start_symbol(fp); // computing the starting symbol for current ssb
ssb_start_symbol = ssb_start_symbol_abs % fp->symbols_per_slot; // start symbol wrt slot ssb_start_symbol = ssb_start_symbol_abs % fp->symbols_per_slot; // start symbol wrt slot
...@@ -279,9 +278,9 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH ...@@ -279,9 +278,9 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
0); 0);
if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations) if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations)
LOG_I(PHY, "ULSCH in error\n"); LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id);
else else
LOG_I(PHY, "ULSCH received ok\n"); LOG_I(PHY, "ULSCH %d received ok\n",ULSCH_id);
} }
......
...@@ -229,17 +229,18 @@ int main(int argc, char **argv) ...@@ -229,17 +229,18 @@ int main(int argc, char **argv)
int mcsIndex_set=0,rbStart_set=0,rbSize_set=0; int mcsIndex_set=0,rbStart_set=0,rbSize_set=0;
int print_perf = 0; int print_perf = 0;
FILE *scg_fd=NULL;
while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) { while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) {
switch (c) { switch (c) {
/*case 'f': case 'f':
write_output_file=1; scg_fd = fopen(optarg,"r");
output_fd = fopen(optarg,"w");
if (output_fd==NULL) { if (scg_fd==NULL) {
printf("Error opening %s\n",optarg); printf("Error opening %s\n",optarg);
exit(-1); exit(-1);
} }
break;*/ break;
/*case 'd': /*case 'd':
frame_type = 1; frame_type = 1;
...@@ -429,7 +430,7 @@ int main(int argc, char **argv) ...@@ -429,7 +430,7 @@ int main(int argc, char **argv)
printf("-O oversampling factor (1,2,4,8,16)\n"); printf("-O oversampling factor (1,2,4,8,16)\n");
printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n");
//printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
//printf("-f Output filename (.txt format) for Pe/SNR results\n"); printf("-f raw file containing RRC configuration (generated by gNB)\n");
printf("-F Input filename (.txt format) for RX conformance testing\n"); printf("-F Input filename (.txt format) for RX conformance testing\n");
printf("-E used CSS scheduler\n"); printf("-E used CSS scheduler\n");
printf("-o CORESET offset\n"); printf("-o CORESET offset\n");
...@@ -470,8 +471,8 @@ int main(int argc, char **argv) ...@@ -470,8 +471,8 @@ int main(int argc, char **argv)
gNB_mac = RC.nrmac[0]; gNB_mac = RC.nrmac[0];
gNB_RRC_INST rrc; gNB_RRC_INST rrc;
memset((void*)&rrc,0,sizeof(rrc)); memset((void*)&rrc,0,sizeof(rrc));
// read in SCGroupConfig // read in SCGroupConfig
FILE *scg_fd = fopen("reconfig.raw","r");
AssertFatal(scg_fd != NULL,"no reconfig.raw file\n"); AssertFatal(scg_fd != NULL,"no reconfig.raw file\n");
char buffer[1024]; char buffer[1024];
int msg_len=fread(buffer,1,1024,scg_fd); int msg_len=fread(buffer,1,1024,scg_fd);
......
...@@ -589,7 +589,8 @@ int main(int argc, char **argv) ...@@ -589,7 +589,8 @@ int main(int argc, char **argv)
while (!((SSB_positions >> ssb_index) & 0x01)) ssb_index++; // to select the first transmitted ssb while (!((SSB_positions >> ssb_index) & 0x01)) ssb_index++; // to select the first transmitted ssb
frame_parms->ssb_index = ssb_index; frame_parms->ssb_index = ssb_index;
UE->symbol_offset = nr_get_ssb_start_symbol(frame_parms); UE->symbol_offset = nr_get_ssb_start_symbol(frame_parms);
int ssb_slot = (ssb_index/2)+(n_hf*frame_parms->slots_per_frame);
int ssb_slot = (ssb_index>>1)+(n_hf*frame_parms->slots_per_frame);
for (int i=UE->symbol_offset+1; i<UE->symbol_offset+4; i++) { for (int i=UE->symbol_offset+1; i<UE->symbol_offset+4; i++) {
nr_slot_fep(UE, nr_slot_fep(UE,
i%frame_parms->symbols_per_slot, i%frame_parms->symbols_per_slot,
......
This diff is collapsed.
...@@ -301,7 +301,7 @@ ...@@ -301,7 +301,7 @@
{GNB_CONFIG_STRING_PRACHMSG1FDM,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM,defint64val:NR_RACH_ConfigGeneric__msg1_FDM_one,TYPE_INT64,0/*72*/},\ {GNB_CONFIG_STRING_PRACHMSG1FDM,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM,defint64val:NR_RACH_ConfigGeneric__msg1_FDM_one,TYPE_INT64,0/*72*/},\
{GNB_CONFIG_STRING_PRACHMSG1FREQUENCYSTART,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart,defint64val:0,TYPE_INT64,0/*73*/},\ {GNB_CONFIG_STRING_PRACHMSG1FREQUENCYSTART,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart,defint64val:0,TYPE_INT64,0/*73*/},\
{GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig,defint64val:13,TYPE_INT64,0/*74*/},\ {GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig,defint64val:13,TYPE_INT64,0/*74*/},\
{GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER,NULL,0,iptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower,defintval:-118,TYPE_INT32,0/*75*/},\ {GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower,defintval:-118,TYPE_INT64,0/*75*/},\
{GNB_CONFIG_STRING_PREAMBLETRANSMAX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleTransMax,defint64val:NR_RACH_ConfigGeneric__preambleTransMax_n10,TYPE_INT64,0/*76*/},\ {GNB_CONFIG_STRING_PREAMBLETRANSMAX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleTransMax,defint64val:NR_RACH_ConfigGeneric__preambleTransMax_n10,TYPE_INT64,0/*76*/},\
{GNB_CONFIG_STRING_POWERRAMPINGSTEP,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.powerRampingStep,defint64val:NR_RACH_ConfigGeneric__powerRampingStep_dB2,TYPE_INT64,0/*77*/},\ {GNB_CONFIG_STRING_POWERRAMPINGSTEP,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.powerRampingStep,defint64val:NR_RACH_ConfigGeneric__powerRampingStep_dB2,TYPE_INT64,0/*77*/},\
{GNB_CONFIG_STRING_RARESPONSEWINDOW,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow,defint64val:NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20,TYPE_INT64,0/*78*/},\ {GNB_CONFIG_STRING_RARESPONSEWINDOW,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow,defint64val:NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20,TYPE_INT64,0/*78*/},\
......
...@@ -212,23 +212,40 @@ void prepare_scc(NR_ServingCellConfigCommon_t *scc) { ...@@ -212,23 +212,40 @@ void prepare_scc(NR_ServingCellConfigCommon_t *scc) {
void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) {
int ssbmaplen = (int)scc->ssb_PositionsInBurst->present; int ssbmaplen = (int)scc->ssb_PositionsInBurst->present;
uint8_t curr_bit;
AssertFatal(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_longBitmap, "illegal ssbmaplen %d\n",ssbmaplen); AssertFatal(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_longBitmap, "illegal ssbmaplen %d\n",ssbmaplen);
// changing endianicity of ssbmap and filling the ssb_PositionsInBurst buffers
if(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap){ if(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap){
scc->ssb_PositionsInBurst->choice.shortBitmap.size = 1; scc->ssb_PositionsInBurst->choice.shortBitmap.size = 1;
scc->ssb_PositionsInBurst->choice.shortBitmap.bits_unused = 4; scc->ssb_PositionsInBurst->choice.shortBitmap.bits_unused = 4;
scc->ssb_PositionsInBurst->choice.shortBitmap.buf = CALLOC(1,1); scc->ssb_PositionsInBurst->choice.shortBitmap.buf = CALLOC(1,1);
scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0] = ssbmap; scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0] = 0;
for (int i=0; i<8; i++) {
if (i<scc->ssb_PositionsInBurst->choice.shortBitmap.bits_unused)
curr_bit = 0;
else
curr_bit = (ssbmap>>(7-i))&0x01;
scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0] |= curr_bit<<i;
}
}else if(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap){ }else if(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap){
scc->ssb_PositionsInBurst->choice.mediumBitmap.size = 1; scc->ssb_PositionsInBurst->choice.mediumBitmap.size = 1;
scc->ssb_PositionsInBurst->choice.mediumBitmap.bits_unused = 0; scc->ssb_PositionsInBurst->choice.mediumBitmap.bits_unused = 0;
scc->ssb_PositionsInBurst->choice.mediumBitmap.buf = CALLOC(1,1); scc->ssb_PositionsInBurst->choice.mediumBitmap.buf = CALLOC(1,1);
scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = ssbmap; scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0;
for (int i=0; i<8; i++)
scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] |= (((ssbmap>>(7-i))&0x01)<<i);
}else { }else {
scc->ssb_PositionsInBurst->choice.longBitmap.size = 8; scc->ssb_PositionsInBurst->choice.longBitmap.size = 8;
scc->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0; scc->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0;
scc->ssb_PositionsInBurst->choice.longBitmap.buf = CALLOC(1,8); scc->ssb_PositionsInBurst->choice.longBitmap.buf = CALLOC(1,8);
for (int j=0; j<8; j++) {
scc->ssb_PositionsInBurst->choice.longBitmap.buf[7-j] = 0;
curr_bit = (ssbmap>>(j<<3))&(0xff);
for (int i=0; i<8; i++) for (int i=0; i<8; i++)
scc->ssb_PositionsInBurst->choice.longBitmap.buf[i] = (ssbmap>>(i<<3))&(0xff); scc->ssb_PositionsInBurst->choice.longBitmap.buf[7-j] |= (((curr_bit>>(7-i))&0x01)<<i);
}
} }
// fix UL absolute frequency // fix UL absolute frequency
......
...@@ -224,21 +224,22 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, ...@@ -224,21 +224,22 @@ void config_common_ue(NR_UE_MAC_INST_t *mac,
cfg->ssb_table.ssb_offset_point_a = absolute_diff/(12*scs_scaling) - 10; cfg->ssb_table.ssb_offset_point_a = absolute_diff/(12*scs_scaling) - 10;
cfg->ssb_table.ssb_period = *scc->ssb_periodicityServingCell; cfg->ssb_table.ssb_period = *scc->ssb_periodicityServingCell;
cfg->ssb_table.ssb_subcarrier_offset = 0; // TODO currently not in RRC? cfg->ssb_table.ssb_subcarrier_offset = 0; // TODO currently not in RRC?
switch (scc->ssb_PositionsInBurst->present) { switch (scc->ssb_PositionsInBurst->present) {
case 1 : case 1 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]; cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]<<24;
cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0;
break; break;
case 2 : case 2 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]; cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]<<24;
cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0;
break; break;
case 3 : case 3 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask = 0; cfg->ssb_table.ssb_mask_list[0].ssb_mask = 0;
cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0;
for (i=0; i<4; i++) { for (i=0; i<4; i++) {
cfg->ssb_table.ssb_mask_list[0].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<<i*8); cfg->ssb_table.ssb_mask_list[0].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<<i*8);
cfg->ssb_table.ssb_mask_list[1].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<<i*8); cfg->ssb_table.ssb_mask_list[1].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<<i*8);
} }
break; break;
default: default:
......
...@@ -49,15 +49,20 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd ...@@ -49,15 +49,20 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
LOG_D(MAC,"Filling search candidates for DCI\n"); LOG_D(MAC,"Filling search candidates for DCI\n");
rel15->number_of_candidates=1; rel15->number_of_candidates=3;
rel15->CCE[0]=0; rel15->CCE[0]=0;
rel15->L[0]=4; rel15->L[0]=4;
rel15->CCE[1]=4;
rel15->L[1]=4;
rel15->CCE[2]=8;
rel15->L[2]=4;
} }
void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) {
// check if DL slot // check if DL slot
if (is_nr_DL_slot(mac->scc->tdd_UL_DL_ConfigurationCommon,slot)==1) { if (is_nr_DL_slot(mac->scc,slot)==1) {
// get BWP 1, Coreset 0, SearchSpace 0 // get BWP 1, Coreset 0, SearchSpace 0
if (mac->DLbwp[0]==NULL) { if (mac->DLbwp[0]==NULL) {
......
...@@ -207,6 +207,8 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm ...@@ -207,6 +207,8 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA > 2016666) if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA > 2016666)
scs_scaling = scs_scaling>>2; scs_scaling = scs_scaling>>2;
uint32_t absolute_diff = (*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA); uint32_t absolute_diff = (*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA);
uint16_t sco = absolute_diff%(12*scs_scaling);
AssertFatal(sco==0,"absoluteFrequencySSB has a subcarrier offset of %d while it should be alligned with CRBs\n",sco);
cfg->ssb_table.ssb_offset_point_a.value = absolute_diff/(12*scs_scaling) - 10; //absoluteFrequencySSB is the central frequency of SSB which is made by 20RBs in total cfg->ssb_table.ssb_offset_point_a.value = absolute_diff/(12*scs_scaling) - 10; //absoluteFrequencySSB is the central frequency of SSB which is made by 20RBs in total
cfg->ssb_table.ssb_offset_point_a.tl.tag = NFAPI_NR_CONFIG_SSB_OFFSET_POINT_A_TAG; cfg->ssb_table.ssb_offset_point_a.tl.tag = NFAPI_NR_CONFIG_SSB_OFFSET_POINT_A_TAG;
cfg->num_tlv++; cfg->num_tlv++;
...@@ -216,19 +218,19 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm ...@@ -216,19 +218,19 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
switch (scc->ssb_PositionsInBurst->present) { switch (scc->ssb_PositionsInBurst->present) {
case 1 : case 1 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]; cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]<<24;
cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0;
break; break;
case 2 : case 2 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]; cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]<<24;
cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0;
break; break;
case 3 : case 3 :
cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = 0; cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = 0;
cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0;
for (i=0; i<4; i++) { for (i=0; i<4; i++) {
cfg->ssb_table.ssb_mask_list[0].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<<i*8); cfg->ssb_table.ssb_mask_list[0].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<<i*8);
cfg->ssb_table.ssb_mask_list[1].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<<i*8); cfg->ssb_table.ssb_mask_list[1].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<<i*8);
} }
break; break;
default: default:
......
...@@ -505,7 +505,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ...@@ -505,7 +505,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[gNB_mac->TX_req[CC_id].Number_of_PDUs]; nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[gNB_mac->TX_req[CC_id].Number_of_PDUs];
mac_rlc_status_resp_t rlc_status; mac_rlc_status_resp_t rlc_status;
nfapi_nr_config_request_t *cfg = &gNB_mac->config[0];
NR_UE_list_t *UE_list = &gNB_mac->UE_list; NR_UE_list_t *UE_list = &gNB_mac->UE_list;
...@@ -775,7 +774,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -775,7 +774,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
//pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE]
pusch_pdu->uplink_frequency_shift_7p5khz = 0; pusch_pdu->uplink_frequency_shift_7p5khz = 0;
//Resource Allocation in time domain //Resource Allocation in time domain
pusch_pdu->start_symbol_index = 2; pusch_pdu->start_symbol_index = 0;
pusch_pdu->nr_of_symbols = 12; pusch_pdu->nr_of_symbols = 12;
//Optional Data only included if indicated in pduBitmap //Optional Data only included if indicated in pduBitmap
pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.rv_index = 0;
......
...@@ -112,7 +112,7 @@ typedef struct { ...@@ -112,7 +112,7 @@ typedef struct {
DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB];
/// scheduling control info /// scheduling control info
NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB];
int next[MAX_MOBILES_PER_GNB]; int next[MAX_MOBILES_PER_GNB];
int head; int head;
int next_ul[MAX_MOBILES_PER_GNB]; int next_ul[MAX_MOBILES_PER_GNB];
......
...@@ -276,14 +276,17 @@ static int trx_usrp_start(openair0_device *device) { ...@@ -276,14 +276,17 @@ static int trx_usrp_start(openair0_device *device) {
// setup GPIO for TDD, GPIO(4) = ATR_RX // setup GPIO for TDD, GPIO(4) = ATR_RX
//set data direction register (DDR) to output //set data direction register (DDR) to output
s->usrp->set_gpio_attr("FP0", "DDR", 0x7f, 0x7f); s->usrp->set_gpio_attr("FP0", "DDR", 0xfff, 0xfff);
//set control register to ATR //set lower 7 bits to be controlled automatically by ATR (the rest 5 bits are controlled manually)
s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0x7f); s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0xfff);
//set pins 4 (RX_TX_Switch) and 6 (Shutdown PA) to 1 when the radio is only receiving (ATR_RX) //set pins 4 (RX_TX_Switch) and 6 (Shutdown PA) to 1 when the radio is only receiving (ATR_RX)
s->usrp->set_gpio_attr("FP0", "ATR_RX", (1<<4)|(1<<6), 0x7f); s->usrp->set_gpio_attr("FP0", "ATR_RX", (1<<4)|(1<<6), 0x7f);
// set pin 5 (Shutdown LNA) to 1 when the radio is transmitting and receiveing (ATR_XX) // set pin 5 (Shutdown LNA) to 1 when the radio is transmitting and receiveing (ATR_XX)
// (we use full duplex here, because our RX is on all the time - this might need to change later) // (we use full duplex here, because our RX is on all the time - this might need to change later)
s->usrp->set_gpio_attr("FP0", "ATR_XX", (1<<5), 0x7f); s->usrp->set_gpio_attr("FP0", "ATR_XX", (1<<5), 0x7f);
// set the output pins to 0
s->usrp->set_gpio_attr("FP0", "OUT", 7<<7, 0xf80);
// init recv and send streaming // init recv and send streaming
uhd::stream_cmd_t cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS); uhd::stream_cmd_t cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
LOG_I(HW,"Time in secs now: %llu \n", s->usrp->get_time_now().to_ticks(s->sample_rate)); LOG_I(HW,"Time in secs now: %llu \n", s->usrp->get_time_now().to_ticks(s->sample_rate));
...@@ -404,10 +407,19 @@ static int trx_usrp_write_recplay(openair0_device *device, openair0_timestamp ti ...@@ -404,10 +407,19 @@ static int trx_usrp_write_recplay(openair0_device *device, openair0_timestamp ti
@param antenna_id index of the antenna if the device has multiple antennas @param antenna_id index of the antenna if the device has multiple antennas
@param flags flags must be set to TRUE if timestamp parameter needs to be applied @param flags flags must be set to TRUE if timestamp parameter needs to be applied
*/ */
static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, void **buff, int nsamps, int cc, int flags) { static int trx_usrp_write(openair0_device *device,
openair0_timestamp timestamp,
void **buff,
int nsamps,
int cc,
int flags) {
int ret=0; int ret=0;
usrp_state_t *s = (usrp_state_t *)device->priv; usrp_state_t *s = (usrp_state_t *)device->priv;
int nsamps2; // aligned to upper 32 or 16 byte boundary int nsamps2; // aligned to upper 32 or 16 byte boundary
int flags_lsb = flags&0xff;
int flags_msb = (flags>>8)&0xff;
#if defined(__x86_64) || defined(__i386__) #if defined(__x86_64) || defined(__i386__)
#ifdef __AVX2__ #ifdef __AVX2__
nsamps2 = (nsamps+7)>>3; nsamps2 = (nsamps+7)>>3;
...@@ -441,27 +453,28 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, ...@@ -441,27 +453,28 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
boolean_t first_packet_state=false,last_packet_state=false; boolean_t first_packet_state=false,last_packet_state=false;
if (flags == 2) { // start of burst if (flags_lsb == 2) { // start of burst
// s->tx_md.start_of_burst = true; // s->tx_md.start_of_burst = true;
// s->tx_md.end_of_burst = false; // s->tx_md.end_of_burst = false;
first_packet_state = true; first_packet_state = true;
last_packet_state = false; last_packet_state = false;
} else if (flags == 3) { // end of burst } else if (flags_lsb == 3) { // end of burst
//s->tx_md.start_of_burst = false; //s->tx_md.start_of_burst = false;
//s->tx_md.end_of_burst = true; //s->tx_md.end_of_burst = true;
first_packet_state = false; first_packet_state = false;
last_packet_state = true; last_packet_state = true;
} else if (flags == 4) { // start and end } else if (flags_lsb == 4) { // start and end
// s->tx_md.start_of_burst = true; // s->tx_md.start_of_burst = true;
// s->tx_md.end_of_burst = true; // s->tx_md.end_of_burst = true;
first_packet_state = true; first_packet_state = true;
last_packet_state = true; last_packet_state = true;
} else if (flags==1) { // middle of burst } else if (flags_lsb==1) { // middle of burst
// s->tx_md.start_of_burst = false; // s->tx_md.start_of_burst = false;
// s->tx_md.end_of_burst = false; // s->tx_md.end_of_burst = false;
first_packet_state = false; first_packet_state = false;
last_packet_state = false; last_packet_state = false;
} else if (flags==10) { // fail safe mode }
else if (flags_lsb==10) { // fail safe mode
// s->tx_md.has_time_spec = false; // s->tx_md.has_time_spec = false;
// s->tx_md.start_of_burst = false; // s->tx_md.start_of_burst = false;
// s->tx_md.end_of_burst = true; // s->tx_md.end_of_burst = true;
...@@ -469,12 +482,22 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, ...@@ -469,12 +482,22 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
last_packet_state = true; last_packet_state = true;
} }
s->tx_md.has_time_spec = true; s->tx_md.has_time_spec = true;
s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state; s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state;
s->tx_md.end_of_burst = last_packet_state; s->tx_md.end_of_burst = last_packet_state;
s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate); s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate);
s->tx_count++; s->tx_count++;
// bit 3 enables gpio (for backward compatibility)
if (flags_msb&8) {
// push GPIO bits 7-9 from flags_msb
int gpio789=(flags_msb&7)<<7;
s->usrp->set_command_time(s->tx_md.time_spec);
s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380);
s->usrp->clear_command_time();
}
if (cc>1) { if (cc>1) {
std::vector<void *> buff_ptrs; std::vector<void *> buff_ptrs;
...@@ -482,7 +505,11 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, ...@@ -482,7 +505,11 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
buff_ptrs.push_back(&(((int16_t *)buff_tx[i])[0])); buff_ptrs.push_back(&(((int16_t *)buff_tx[i])[0]));
ret = (int)s->tx_stream->send(buff_ptrs, nsamps, s->tx_md); ret = (int)s->tx_stream->send(buff_ptrs, nsamps, s->tx_md);
} else ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md); }
else {
ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md);
}
if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps); if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
return ret; return ret;
......
...@@ -33,7 +33,7 @@ gNBs = ...@@ -33,7 +33,7 @@ gNBs =
# downlinkConfigCommon # downlinkConfigCommon
#frequencyInfoDL #frequencyInfoDL
# this is pointA + 23 PRBs@120kHz SCS (same as initial BWP) # this is pointA + 23 PRBs@120kHz SCS (same as initial BWP)
absoluteFrequencySSB = 2077643; absoluteFrequencySSB = 2077907;
dl_frequencyBand = 257; dl_frequencyBand = 257;
# this is 27.900 GHz # this is 27.900 GHz
dl_absoluteFrequencyPointA = 2077499; dl_absoluteFrequencyPointA = 2077499;
...@@ -148,11 +148,11 @@ gNBs = ...@@ -148,11 +148,11 @@ gNBs =
# ssb_PositionsInBurs_BitmapPR # ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long # 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 3; ssb_PositionsInBurst_PR = 3;
ssb_PositionsInBurst_Bitmap = 1; ssb_PositionsInBurst_Bitmap = 0x100000001L;
# ssb_periodicityServingCell # ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 # 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 1; ssb_periodicityServingCell = 2;
# dmrs_TypeA_position # dmrs_TypeA_position
# 0 = pos2, 1 = pos3 # 0 = pos2, 1 = pos3
...@@ -170,8 +170,8 @@ gNBs = ...@@ -170,8 +170,8 @@ gNBs =
# pattern1 # pattern1
# dl_UL_TransmissionPeriodicity # dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6; dl_UL_TransmissionPeriodicity = 5;
nrofDownlinkSlots = 30; nrofDownlinkSlots = 10;
nrofDownlinkSymbols = 0; nrofDownlinkSymbols = 0;
nrofUplinkSlots = 10; nrofUplinkSlots = 10;
nrofUplinkSymbols = 0; nrofUplinkSymbols = 0;
...@@ -237,8 +237,8 @@ RUs = ( ...@@ -237,8 +237,8 @@ RUs = (
max_pdschReferenceSignalPower = -27; max_pdschReferenceSignalPower = -27;
max_rxgain = 114; max_rxgain = 114;
eNB_instances = [0]; eNB_instances = [0];
sdr_addrs = "type=x300"; sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2";
if_freq = 3000000000; if_freq = 5300000000;
} }
); );
......
...@@ -33,7 +33,7 @@ gNBs = ...@@ -33,7 +33,7 @@ gNBs =
# downlinkConfigCommon # downlinkConfigCommon
#frequencyInfoDL #frequencyInfoDL
# this is pointA + 23 PRBs@120kHz SCS (same as initial BWP) # this is pointA + 23 PRBs@120kHz SCS (same as initial BWP)
absoluteFrequencySSB = 2078051; absoluteFrequencySSB = 2078315;
dl_frequencyBand = 257; dl_frequencyBand = 257;
# this is 27.900 GHz # this is 27.900 GHz
dl_absoluteFrequencyPointA = 2077499; dl_absoluteFrequencyPointA = 2077499;
......
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