Skip to content

O
OpenXG-RAN
Commit fcbf8706 authored by hardy's avatar hardy
Browse files
Options

Merge remote-tracking branch 'origin/NR_msg3_retransmission' into integration_2021_wk34

parents b7987553 b356a816
Expand all Show whitespace changes
Inline Side-by-side
Showing with 517 additions and 220 deletions
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ fcbf8706
......@@ -992,6 +992,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
}
}
}
pdcch_vars->nb_search_space = 0;
return(dci_ind->number_of_dcis);
}
......
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @ fcbf8706
......@@ -70,7 +70,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
for (i = 0; i < dl_config->number_pdus; ++i){
AssertFatal(dl_config->number_pdus < FAPI_NR_DL_CONFIG_LIST_NUM,"dl_config->number_pdus %d out of bounds\n",dl_config->number_pdus);
AssertFatal(dl_config->dl_config_list[i].pdu_type<=FAPI_NR_DL_CONFIG_TYPES,"pdu_type %d > 2\n",dl_config->dl_config_list[i].pdu_type);
LOG_D(PHY, "In %s: received 1 DL %s PDU of %d total DL PDUs:\n", __FUNCTION__, dl_pdu_type[dl_config->dl_config_list[i].pdu_type - 1], dl_config->number_pdus);
LOG_D(PHY, "In %s: frame %d slot %d received 1 DL %s PDU of %d total DL PDUs:\n",
__FUNCTION__, scheduled_response->frame, slot, dl_pdu_type[dl_config->dl_config_list[i].pdu_type - 1], dl_config->number_pdus);
if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) {
......@@ -225,9 +226,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
break;
}
}
memset(ul_config, 0, sizeof(fapi_nr_ul_config_request_t));
}
}
return 0;
......
openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c
View file @ fcbf8706
......@@ -321,7 +321,7 @@ void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint
mac->RA_attempt_number++;
}
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, slot_t slotP, uint8_t gNB_id){
AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP);
NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
......
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ fcbf8706
......@@ -292,8 +292,8 @@ typedef struct {
/// Random-access Contention Resolution Timer active flag
uint8_t RA_contention_resolution_timer_active;
/// Random-access Contention Resolution Timer count value
uint8_t RA_contention_resolution_cnt;
int RA_contention_resolution_target_frame;
int RA_contention_resolution_target_slot;
/// Transmitted UE Contention Resolution Identifier
uint8_t cont_res_id[6];
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ fcbf8706
......@@ -352,7 +352,7 @@ void nr_get_prach_resources(module_id_t mod_id,
void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id);
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id);
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, slot_t slotP, uint8_t gNB_id);
void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach_slot, uint16_t *msg2_frame, uint16_t *msg2_slot);
......
openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
View file @ fcbf8706
......@@ -457,18 +457,27 @@ void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint
ra->RA_attempt_number++;
}
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, slot_t slotP, uint8_t gNB_id){
NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
RA_config_t *ra = &mac->ra;
NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (mac->scc) ?
mac->scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup:
mac->scc_SIB->uplinkConfigCommon->initialUplinkBWP.rach_ConfigCommon->choice.setup;
RA_config_t *ra = &mac->ra;
long mu = (mac->scc) ?
mac->scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing :
mac->scc_SIB->downlinkConfigCommon.frequencyInfoDL.scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
int subframes_per_slot = nr_slots_per_frame[mu]/10;
// start contention resolution timer (cnt in slots)
int RA_contention_resolution_timer_subframes = (nr_rach_ConfigCommon->ra_ContentionResolutionTimer + 1)<<3;
LOG_D(MAC,"In %s: [UE %d] Frame %d, CB-RA: starting contention resolution timer\n", __FUNCTION__, mod_id, frameP);
ra->RA_contention_resolution_target_frame = frameP + (RA_contention_resolution_timer_subframes/10);
ra->RA_contention_resolution_target_slot = (slotP + (RA_contention_resolution_timer_subframes * subframes_per_slot)) % nr_slots_per_frame[mu];
LOG_D(MAC,"In %s: [UE %d] CB-RA: contention resolution timer set in frame.slot %d.%d and expiring in %d.%d\n",
__FUNCTION__, mod_id, frameP, slotP, ra->RA_contention_resolution_target_frame, ra->RA_contention_resolution_target_slot);
// start contention resolution timer
ra->RA_contention_resolution_cnt = (nr_rach_ConfigCommon->ra_ContentionResolutionTimer + 1) * 8;
ra->RA_contention_resolution_timer_active = 1;
ra->ra_state = WAIT_CONTENTION_RESOLUTION;
......@@ -739,12 +748,8 @@ void nr_ue_contention_resolution(module_id_t module_id, int cc_id, frame_t frame
RA_config_t *ra = &mac->ra;
if (ra->RA_contention_resolution_timer_active == 1) {
ra->RA_contention_resolution_cnt--;
LOG_D(MAC, "In %s: [%d.%d] RA contention resolution timer %d\n", __FUNCTION__, frame, slot, ra->RA_contention_resolution_cnt);
if (ra->RA_contention_resolution_cnt == 0) {
if (frame >= ra->RA_contention_resolution_target_frame &&
slot >= ra->RA_contention_resolution_target_slot) {
ra->t_crnti = 0;
ra->RA_active = 0;
ra->RA_contention_resolution_timer_active = 0;
......@@ -752,7 +757,6 @@ void nr_ue_contention_resolution(module_id_t module_id, int cc_id, frame_t frame
LOG_E(MAC, "[UE %d] CB-RA: Contention resolution timer has expired, RA procedure has failed...\n", module_id);
nr_ra_failed(module_id, cc_id, prach_resources, frame, slot);
}
}
}
......@@ -775,7 +779,6 @@ void nr_ra_succeeded(module_id_t mod_id, frame_t frame, int slot){
LOG_I(MAC, "[UE %d][%d.%d][RAPROC] RA procedure succeeded. CB-RA: Contention Resolution is successful.\n", mod_id, frame, slot);
ra->RA_contention_resolution_cnt = -1;
ra->RA_contention_resolution_timer_active = 0;
mac->crnti = ra->t_crnti;
ra->t_crnti = 0;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @ fcbf8706
......@@ -183,7 +183,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->BWPStart = NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
rel15->dci_length_options[0] = nr_dci_size(initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[0]], rel15->dci_format_options[0], NR_RNTI_TC, rel15->BWPSize, bwp_id);
for (int i = 0; i < rel15->num_dci_options; i++)
rel15->dci_length_options[i] = nr_dci_size(initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_TC, rel15->BWPSize, bwp_id);
break;
case NR_RNTI_SP_CSI:
break;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ fcbf8706
......@@ -512,7 +512,10 @@ int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_in
dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits);
int8_t ret = nr_extract_dci_info(mac, dci->dci_format, dci->payloadSize, dci->rnti, (uint64_t *)dci->payloadBits, def_dci_pdu_rel15);
if ((ret&1) == 1) return -1;
else if (ret == 2) dci->dci_format = NR_UL_DCI_FORMAT_0_0;
else if (ret == 2) {
dci->dci_format = NR_UL_DCI_FORMAT_0_0;
def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[dci->dci_format];
}
return (nr_ue_process_dci(module_id, cc_id, gNB_index, frame, slot, def_dci_pdu_rel15, dci));
}
......@@ -2493,9 +2496,10 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
//switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0)
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[NR_UL_DCI_FORMAT_0_0];
return 2+nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, dci_pdu, dci_pdu_rel15);
}
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu);
#endif
......@@ -2691,6 +2695,12 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
//switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[NR_UL_DCI_FORMAT_0_0];
return 2+nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, dci_pdu, dci_pdu_rel15);
}
if (dci_pdu_rel15->format_indicator == 0)
return 1; // discard dci, format indicator not corresponding to dci_format
......@@ -2829,40 +2839,62 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
break;
case NR_RNTI_TC:
/*
// indicating a DL DCI format 1bit
dci_pdu->= (*dci_pdu>>(dci_size-pos)format_indicator&1)<<(dci_size-pos++);
// Freq domain assignment max 16 bit
//Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
#endif
if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format
fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
for (int i=0; i<fsize; i++)
dci_pdu->= ((*dci_pdu>>(dci_size-pos)frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
#endif
// Time domain assignment 4bit
for (int i=0; i<4; i++)
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
#endif
// Frequency hopping flag  E1 bit
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)frequency_hopping_flag&1)<<(dci_size-pos++);
pos++;
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu);
#endif
// MCS 5 bit
for (int i=0; i<5; i++)
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)mcs>>(4-i))&1)<<(dci_size-pos++);
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
#endif
// New data indicator 1bit
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ndi&1)<<(dci_size-pos++);
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit
for (int i=0; i<2; i++)
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)rv>>(1-i))&1)<<(dci_size-pos++);
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)*dci_pdu>>(dci_size-pos)harq_pid>>(3-i))&1)<<(dci_size-pos++);
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits
for (int i=0; i<2; i++)
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)tpc>>(1-i))&1)<<(dci_size-pos++);
*/
// UL/SUL indicator  E1 bit
/*
commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
*/
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
#endif
break;
}
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ fcbf8706
......@@ -944,12 +944,15 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
}
// this is for Msg2/Msg4
if (mac->ra.ra_state >= WAIT_RAR) {
rel15->num_dci_options = 1;
rel15->num_dci_options = mac->ra.ra_state == WAIT_RAR ? 1 : 2;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
if (mac->ra.ra_state == WAIT_CONTENTION_RESOLUTION)
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0; // msg3 retransmission
config_dci_pdu(mac, rel15, dl_config, mac->ra.ra_state == WAIT_RAR ? NR_RNTI_RA : NR_RNTI_TC , -1);
fill_dci_search_candidates(ss0, rel15);
dl_config->number_pdus = 1;
LOG_D(NR_MAC,"mac->cg %p: Calling fill_scheduled_response rnti %x, type0_pdcch, num_pdus %d\n",mac->cg,rel15->rnti,dl_config->number_pdus);
LOG_D(NR_MAC,"mac->cg %p: Calling fill_scheduled_response rnti %x, type0_pdcch, num_pdus %d frame %d slot %d\n",
mac->cg,rel15->rnti,dl_config->number_pdus,rx_frame,rx_slot);
fill_scheduled_response(&scheduled_response, dl_config, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id);
if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL)
mac->if_module->scheduled_response(&scheduled_response);
......@@ -1016,7 +1019,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
if (ulcfg_pdu->pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
uint16_t TBS_bytes = ulcfg_pdu->pusch_config_pdu.pusch_data.tb_size;
LOG_D(NR_MAC,"harq_id %d, NDI %d NDI_DCI %d, TBS_bytes %d (ra_state %d\n",
LOG_D(NR_MAC,"harq_id %d, NDI %d NDI_DCI %d, TBS_bytes %d (ra_state %d)\n",
ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id,
mac->UL_ndi[ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id],
ulcfg_pdu->pusch_config_pdu.pusch_data.new_data_indicator,
......@@ -1054,11 +1057,15 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
tx_req.tx_request_body[0].pdu_index = j;
tx_req.tx_request_body[0].pdu = ulsch_input_buffer;
if (ra->ra_state == WAIT_CONTENTION_RESOLUTION && !ra->cfra){
LOG_I(NR_MAC,"[RAPROC] RA-Msg3 retransmitted\n");
// 38.321 restart the ra-ContentionResolutionTimer at each HARQ retransmission in the first symbol after the end of the Msg3 transmission
nr_Msg3_transmitted(ul_info->module_id, ul_info->cc_id, ul_info->frame_tx, ul_info->slot_tx, ul_info->gNB_index);
}
if (ra->ra_state == WAIT_RAR && !ra->cfra){
LOG_I(NR_MAC,"[RAPROC] RA-Msg3 transmitted\n");
nr_Msg3_transmitted(ul_info->module_id, ul_info->cc_id, ul_info->frame_tx, ul_info->gNB_index);
nr_Msg3_transmitted(ul_info->module_id, ul_info->cc_id, ul_info->frame_tx, ul_info->slot_tx, ul_info->gNB_index);
}
}
}
......@@ -1090,7 +1097,6 @@ int nr_ue_pusch_scheduler(NR_UE_MAC_INST_t *mac,
int delta = 0;
NR_BWP_Uplink_t *ubwp = mac->ULbwp[0];
// Get the numerology to calculate the Tx frame and slot
int mu = ubwp ?
ubwp->bwp_Common->genericParameters.subcarrierSpacing :
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ fcbf8706
......@@ -607,6 +607,7 @@ void config_uldci(const NR_BWP_Uplink_t *ubwp,
uint8_t tpc,
int n_ubwp,
int bwp_id) {
const int bw = NRRIV2BW(ubwp ?
ubwp->bwp_Common->genericParameters.locationAndBandwidth :
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
......@@ -1385,41 +1386,53 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
break;
case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit
*dci_pdu |= (dci_pdu_rel15->format_indicator & 1) << (dci_size - pos++);
// indicating a UL DCI format 1bit
pos=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator & 1) << (dci_size - pos);
// Freq domain assignment max 16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
for (int i = 0; i < fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val >> (fsize - i - 1)) & 1) << (dci_size - pos++);
pos+=fsize;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val & ((1 << fsize) - 1)) << (dci_size - pos);
// Time domain assignment 4bit
for (int i = 0; i < 4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val >> (3 - i)) & 1) << (dci_size - pos++);
pos += 4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val & ((1 << 4) - 1)) << (dci_size - pos);
// Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val & 1) << (dci_size - pos++);
pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val & 1) << (dci_size - pos);
// MCS 5 bit
for (int i = 0; i < 5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs >> (4 - i)) & 1) << (dci_size - pos++);
pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs & 0x1f) << (dci_size - pos);
// New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi & 1) << (dci_size - pos++);
pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi & 1) << (dci_size - pos);
// Redundancy version 2bit
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv >> (1 - i)) & 1) << (dci_size - pos++);
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
// HARQ process number 4bit
for (int i = 0; i < 4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid >> (3 - i)) & 1) << (dci_size - pos++);
// TPC command for scheduled PUSCH – 2 bits
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc >> (1 - i)) & 1) << (dci_size - pos++);
pos+=4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// Padding bits
for (int a = pos; a < 32; a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding & 1) << (dci_size - pos++);
// UL/SUL indicator – 1 bit
/*
commented for now (RK): need to get this information from BWP descriptor
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |=
((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_hopping_flag.val = %i\n", dci_pdu_rel15->frequency_hopping_flag.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->ndi = %i\n", dci_pdu_rel15->ndi);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->padding = %i\n", dci_pdu_rel15->padding);
break;
}
break;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ fcbf8706
......@@ -526,19 +526,26 @@ void abort_nr_ul_harq(module_id_t mod_id, int UE_id, int8_t harq_pid)
sched_ctrl->sched_ul_bytes = 0;
}
void handle_nr_ul_harq(module_id_t mod_id,
void handle_nr_ul_harq(const int CC_idP,
module_id_t mod_id,
frame_t frame,
sub_frame_t slot,
const nfapi_nr_crc_t *crc_pdu)
{
gNB_MAC_INST *gNB_mac = RC.nrmac[mod_id];
int UE_id = find_nr_UE_id(mod_id, crc_pdu->rnti);
if (UE_id < 0) {
for (int i = 0; i < NR_NB_RA_PROC_MAX; ++i) {
NR_RA_t *ra = &gNB_mac->common_channels[CC_idP].ra[i];
if (ra->state >= WAIT_Msg3 &&
ra->rnti == crc_pdu->rnti)
return;
}
LOG_E(NR_MAC, "%s(): unknown RNTI %04x in PUSCH\n", __func__, crc_pdu->rnti);
return;
}
NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
int8_t harq_pid = sched_ctrl->feedback_ul_harq.head;
while (crc_pdu->harq_id != harq_pid || harq_pid < 0) {
LOG_W(NR_MAC,
......@@ -601,6 +608,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
const uint16_t timing_advance,
const uint8_t ul_cqi,
const uint16_t rssi){
gNB_MAC_INST *gNB_mac = RC.nrmac[gnb_mod_idP];
NR_UE_info_t *UE_info = &gNB_mac->UE_info;
......@@ -799,9 +807,19 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
if (ra->state != WAIT_Msg3)
continue;
LOG_W(NR_MAC, "Random Access %i failed at state %i (state is not WAIT_Msg3)\n", i, ra->state);
if( (frameP!=ra->Msg3_frame) || (slotP!=ra->Msg3_slot))
continue;
if (ra->msg3_round >= MAX_HARQ_ROUNDS - 1) {
LOG_W(NR_MAC, "Random Access %i failed at state %i (Reached msg3 max harq rounds)\n", i, ra->state);
nr_mac_remove_ra_rnti(gnb_mod_idP, ra->rnti);
nr_clear_ra_proc(gnb_mod_idP, CC_idP, frameP, ra);
return;
}
LOG_W(NR_MAC, "Random Access %i Msg3 CRC did not pass)\n", i);
ra->msg3_round++;
ra->state = Msg3_retransmission;
}
}
}
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ fcbf8706
......@@ -124,6 +124,8 @@ void nr_get_Msg3alloc(module_id_t module_id,
NR_RA_t *ra,
int16_t *tdd_beam_association);
void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t *ra);
/* \brief Function in gNB to fill RAR pdu when requested by PHY.
@param ra Instance of RA resources of gNB
@param dlsch_buffer Pointer to RAR input buffer
......@@ -134,6 +136,15 @@ void nr_fill_rar(uint8_t Mod_idP,
uint8_t * dlsch_buffer,
nfapi_nr_pusch_pdu_t *pusch_pdu);
void fill_msg3_pusch_pdu(nfapi_nr_pusch_pdu_t *pusch_pdu,
NR_ServingCellConfigCommon_t *scc,
int round,
int startSymbolAndLength,
rnti_t rnti, int scs,
int bwp_size, int bwp_start,
int mappingtype, int fh,
int msg3_first_rb, int msg3_nb_rb);
void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP);
......@@ -388,7 +399,8 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
const uint8_t ul_cqi,
const uint16_t rssi);
void handle_nr_ul_harq(module_id_t mod_id,
void handle_nr_ul_harq(const int CC_idP,
module_id_t mod_id,
frame_t frame,
sub_frame_t slot,
const nfapi_nr_crc_t *crc_pdu);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ fcbf8706
......@@ -93,8 +93,9 @@ typedef enum {
RA_IDLE = 0,
Msg2 = 1,
WAIT_Msg3 = 2,
Msg4 = 3,
WAIT_Msg4_ACK = 4
Msg3_retransmission = 3,
Msg4 = 4,
WAIT_Msg4_ACK = 5
} RA_gNB_state_t;
typedef struct NR_preamble_ue {
......
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
View file @ fcbf8706
......@@ -182,7 +182,7 @@ void handle_nr_ulsch(NR_UL_IND_t *UL_info)
rx->timing_advance,
rx->ul_cqi,
rx->rssi);
handle_nr_ul_harq(UL_info->module_id, UL_info->frame, UL_info->slot, crc);
handle_nr_ul_harq(UL_info->CC_id, UL_info->module_id, UL_info->frame, UL_info->slot, crc);
break;
} // for (j=0;j<UL_info->crc_ind.number_crcs;j++)
} // for (i=0;i<UL_info->rx_ind.number_of_pdus;i++)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment