nr_ue_procedures.c 129 KB
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/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
 * the OAI Public License, Version 1.1  (the "License"); you may not use this file
 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */

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/* \file ue_procedures.c
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 * \brief procedures related to UE
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 * \author R. Knopp, K.H. HSU
 * \date 2018
 * \version 0.1
 * \company Eurecom / NTUST
 * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr
 * \note
 * \warning
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 */
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#include "mac_proto.h"
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#include "mac_extern.h"
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#include "RRC/NR_UE/rrc_proto.h"
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#include "assertions.h"
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#include "PHY/defs_nr_UE.h"
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#include "common/utils/LOG/log.h"
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#include "openair2/LAYER2/MAC/mac.h"
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#include "openair2/LAYER2/RLC/rlc.h"
#include "SIMULATION/TOOLS/sim.h" // for taus
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#include <stdio.h>
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#include <math.h>
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//#define ENABLE_MAC_PAYLOAD_DEBUG 1
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extern void mac_rlc_data_ind     (
  const module_id_t         module_idP,
  const rnti_t              rntiP,
  const eNB_index_t         eNB_index,
  const frame_t             frameP,
  const eNB_flag_t          enb_flagP,
  const MBMS_flag_t         MBMS_flagP,
  const logical_chan_id_t   channel_idP,
  char                     *buffer_pP,
  const tb_size_t           tb_sizeP,
  num_tb_t                  num_tbP,
  crc_t                    *crcs_pP);

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uint32_t get_ssb_slot(uint32_t ssb_index){
    //  this function now only support f <= 3GHz
    return ssb_index & 0x3 ;

    //  return first_symbol(case, freq, ssb_index) / 14
}

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uint8_t table_9_2_2_1[16][8]={
{0,12,2, 0, 0,3,0,0},
{0,12,2, 0, 0,4,8,0},
{0,12,2, 3, 0,4,8,0},
{1,10,4, 0, 0,6,0,0},
{1,10,4, 0, 0,3,6,9},
{1,10,4, 2, 0,3,6,9},
{1,10,4, 4, 0,3,6,9},
{1,4, 10,0, 0,6,0,0},
{1,4, 10,0, 0,3,6,9},
{1,4, 10,2, 0,3,6,9},
{1,4, 10,4, 0,3,6,9},
{1,0, 14,0, 0,6,0,0},
{1,0, 14,0, 0,3,6,9},
{1,0, 14,2, 0,3,6,9},
{1,0, 14,4, 0,3,6,9},
{1,0, 14,26,0,3,0,0}
};
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int8_t nr_ue_process_dlsch(module_id_t module_id,
		                   int cc_id,
						   uint8_t gNB_index,
						   fapi_nr_dci_indication_t *dci_ind,
						   void *pduP,
						   uint32_t pdu_len)
{
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    NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
    fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
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    //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
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    nr_phy_config_t *phy_config = &mac->phy_config;

    //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
    // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ.
    ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
    for (int i=0; i<10; i++) {
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    	if(dci_ind!=NULL){
    		if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
    	}
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    }
    if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
        // fill in the elements in config request inside P5 message
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0;
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      for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0;
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      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0;
      //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0;
      ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0;
    } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ
      ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
      // If we handle PUCCH common
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format              = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0];              /* format   0    1    2    3    4    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift  = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4];  /*          x    x                   */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols         = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2];         /*          x    x    x    x    x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /*          x    x    x    x    x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0;       /*               x                   */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0;            /*                    x    x         */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB         = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3];         /*                                     maxNrofPhysicalResourceBlocks  = 275 */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0;          /*                              x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0;           /*                              x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping  = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId           = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal          = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
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      for (int i=0;i<NUMBER_PUCCH_FORMAT_NR;i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
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      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0;     /* INTEGER (1..8)     */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;
      // If we handle PUCCH dedicated
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format              = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format;              /* format   0    1    2    3    4    */
      switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){
        case pucch_format1_nr:
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS            = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots                 = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK                   = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI  = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi;
        break;
        case pucch_format2_nr:
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS            = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots                 = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK                   = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI  = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi;
        break;
        case pucch_format3_nr:
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS            = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots                 = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK                   = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI  = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi;
        break;
        case pucch_format4_nr:
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS            = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots                 = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK                   = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk;
            ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI  = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi;
        break;
        default:
        break;
      }
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift        = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift;  /*          x    x                   */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols;         /*          x    x    x    x    x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex       = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /*          x    x    x    x    x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC             = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ;       /*               x                   */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs                  = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs;            /*                    x    x         */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB               = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb;         /*                                     maxNrofPhysicalResourceBlocks  = 275 */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length                = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length;          /*                              x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index                 = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index;           /*                              x    */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB              = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping        = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId                 = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal                = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
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      for (int i=0;i<NUMBER_PUCCH_FORMAT_NR; i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
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      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0;     /* INTEGER (1..8)     */
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
      ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;

    }
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    if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){
        mac->if_module->scheduled_response(&mac->scheduled_response);
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    }
    return 0;
}

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int8_t nr_ue_decode_mib(UE_nr_rxtx_proc_t *proc,
                        module_id_t module_id,
                        int cc_id,
                        uint8_t gNB_index,
                        uint8_t extra_bits,	//	8bits 38.212 c7.1.1
                        uint32_t ssb_length,
                        uint32_t ssb_index,
                        void *pduP,
                        uint16_t cell_id)
{
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    LOG_I(MAC,"[L2][MAC] decode mib\n");
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	NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);

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    nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 );    //  fixed 3 bytes MIB PDU
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    AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n");
    //if(mac->mib != NULL){
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	    uint16_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused);
	    uint16_t frame_number_4lsb = 0;
      for (int i=0; i<4; i++)
        frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i);
	    uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1;               //	extra bits[4]
	    uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1;    //	extra bits[5]
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	    uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset;
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	    //uint32_t ssb_index = 0;    //  TODO: ssb_index should obtain from L1 in case Lssb != 64
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	    frame = frame << 4;
	    frame = frame | frame_number_4lsb;
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	    if(ssb_length == 64){
	    	ssb_index = ssb_index & (( extra_bits >> 2 ) & 0x1C );    //	{ extra_bits[5:7], ssb_index[2:0] }
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	    }else{
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			if(ssb_subcarrier_offset_msb){
			    ssb_subcarrier_offset = ssb_subcarrier_offset | 0x10;
			}
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	    }
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#ifdef DEBUG_MIB
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		LOG_I(MAC,"system frame number(6 MSB bits): %d\n",  mac->mib->systemFrameNumber.buf[0]);
		LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame);
		LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon);
		LOG_I(MAC,"ssb carrier offset(with MSB):  %d\n", (int)ssb_subcarrier_offset);
		LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position);
		LOG_I(MAC,"pdcch config sib1:             %d\n", (int)mac->mib->pdcch_ConfigSIB1);
		LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
		LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
		LOG_I(MAC,"half frame bit(extra bits):    %d\n", (int)half_frame_bit);
		LOG_I(MAC,"ssb index(extra bits):         %d\n", (int)ssb_index);
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#endif

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	    subcarrier_spacing_t scs_ssb = scs_30kHz;      //  default for 
        //const uint32_t scs_index = 0;
        const uint32_t num_slot_per_frame = 20;
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	    subcarrier_spacing_t scs_pdcch;

        //  assume carrier frequency < 6GHz
        if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){
            scs_pdcch = scs_15kHz;
        }else{  //NR_MIB__subCarrierSpacingCommon_scs30or120
            scs_pdcch = scs_30kHz;
        }

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	channel_bandwidth_t min_channel_bw = bw_10MHz;  //  deafult for testing
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        uint32_t is_condition_A = (ssb_subcarrier_offset == 0);   //  38.213 ch.13
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        frequency_range_t frequency_range = FR1;
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        uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero);
        uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
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        int32_t num_rbs = -1;
        int32_t num_symbols = -1;
        int32_t rb_offset = -1;
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        //LOG_I(MAC,"<<<<<<<<<configSIB1 %d index_4msb %d index_4lsb %d scs_ssb %d scs_pdcch %d switch %d ",
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        //mac->mib->pdcch_ConfigSIB1,index_4msb,index_4lsb,scs_ssb,scs_pdcch, (scs_ssb << 5)|scs_pdcch);
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        //  type0-pdcch coreset
	    switch( (scs_ssb << 5)|scs_pdcch ){
            case (scs_15kHz << 5) | scs_15kHz :
                AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n");
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                mac->type0_pdcch_ss_mux_pattern = 1;
                num_rbs     = table_38213_13_1_c2[index_4msb];
                num_symbols = table_38213_13_1_c3[index_4msb];
                rb_offset   = table_38213_13_1_c4[index_4msb];
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                break;

	        case (scs_15kHz << 5) | scs_30kHz:
                AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n");
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                mac->type0_pdcch_ss_mux_pattern = 1;
                num_rbs     = table_38213_13_2_c2[index_4msb];
                num_symbols = table_38213_13_2_c3[index_4msb];
                rb_offset   = table_38213_13_2_c4[index_4msb];
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                break;

            case (scs_30kHz << 5) | scs_15kHz:
                if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
                    AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n");
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                    mac->type0_pdcch_ss_mux_pattern = 1;
                    num_rbs     = table_38213_13_3_c2[index_4msb];
                    num_symbols = table_38213_13_3_c3[index_4msb];
                    rb_offset   = table_38213_13_3_c4[index_4msb];
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                }else if(min_channel_bw & bw_40MHz){
                    AssertFatal(index_4msb < 9, "38.213 Table 13-5 4 MSB out of range\n");
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                    mac->type0_pdcch_ss_mux_pattern = 1;
                    num_rbs     = table_38213_13_5_c2[index_4msb];
                    num_symbols = table_38213_13_5_c3[index_4msb];
                    rb_offset   = table_38213_13_5_c4[index_4msb];
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                }else{ ; }

                break;

            case (scs_30kHz << 5) | scs_30kHz:
                if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
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                    mac->type0_pdcch_ss_mux_pattern = 1;
                    num_rbs     = table_38213_13_4_c2[index_4msb];
                    num_symbols = table_38213_13_4_c3[index_4msb];
                    rb_offset   = table_38213_13_4_c4[index_4msb];
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                    LOG_I(MAC,"<<<<<<<<<index_4msb %d num_rbs %d num_symb %d rb_offset %d\n",index_4msb,num_rbs,num_symbols,rb_offset );
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                }else if(min_channel_bw & bw_40MHz){
                    AssertFatal(index_4msb < 10, "38.213 Table 13-6 4 MSB out of range\n");
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                    mac->type0_pdcch_ss_mux_pattern = 1;
                    num_rbs     = table_38213_13_6_c2[index_4msb];
                    num_symbols = table_38213_13_6_c3[index_4msb];
                    rb_offset   = table_38213_13_6_c4[index_4msb];
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                }else{ ; }
                break;

            case (scs_120kHz << 5) | scs_60kHz:
                AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n");
                if(index_4msb & 0x7){
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                    mac->type0_pdcch_ss_mux_pattern = 1;
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                }else if(index_4msb & 0x18){
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                    mac->type0_pdcch_ss_mux_pattern = 2;
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                }else{ ; }

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                num_rbs     = table_38213_13_7_c2[index_4msb];
                num_symbols = table_38213_13_7_c3[index_4msb];
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                if(!is_condition_A && (index_4msb == 8 || index_4msb == 10)){
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                    rb_offset   = table_38213_13_7_c4[index_4msb] - 1;
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                }else{
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                    rb_offset   = table_38213_13_7_c4[index_4msb];
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                }
                break;

            case (scs_120kHz << 5) | scs_120kHz:
                AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n");
                if(index_4msb & 0x3){
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                    mac->type0_pdcch_ss_mux_pattern = 1;
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                }else if(index_4msb & 0x0c){
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                    mac->type0_pdcch_ss_mux_pattern = 3;
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                }

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                num_rbs     = table_38213_13_8_c2[index_4msb];
                num_symbols = table_38213_13_8_c3[index_4msb];
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                if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
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                    rb_offset   = table_38213_13_8_c4[index_4msb] - 1;
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                }else{
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                    rb_offset   = table_38213_13_8_c4[index_4msb];
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                }
                break;

            case (scs_240kHz << 5) | scs_60kHz:
                AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n");
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                mac->type0_pdcch_ss_mux_pattern = 1;
                num_rbs     = table_38213_13_9_c2[index_4msb];
                num_symbols = table_38213_13_9_c3[index_4msb];
                rb_offset   = table_38213_13_9_c4[index_4msb];
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                break;

            case (scs_240kHz << 5) | scs_120kHz:
                AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n");
                if(index_4msb & 0x3){
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                    mac->type0_pdcch_ss_mux_pattern = 1;
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                }else if(index_4msb & 0x0c){
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                    mac->type0_pdcch_ss_mux_pattern = 2;
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                }
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                num_rbs     = table_38213_13_10_c2[index_4msb];
                num_symbols = table_38213_13_10_c3[index_4msb];
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                if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
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                    rb_offset   = table_38213_13_10_c4[index_4msb]-1;
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                }else{
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                    rb_offset   = table_38213_13_10_c4[index_4msb];
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                }
                
                break;

	        default:
	            break;
	    }

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        AssertFatal(num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined");
        AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
        AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
        
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        //uint32_t cell_id = 0;   //  obtain from L1 later
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        //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset;
        //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1;
        uint64_t mask = 0x0;
        uint8_t i;
        for(i=0; i<(num_rbs/6); ++i){   //  38.331 Each bit corresponds a group of 6 RBs
            mask = mask >> 1;
            mask = mask | 0x100000000000;
        }
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        //LOG_I(MAC,">>>>>>>>mask %x num_rbs %d rb_offset %d\n", mask, num_rbs, rb_offset);
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        mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask;
        mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset;  //  additional parameter other than coreset

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        //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols;
        mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED;
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        mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6;   //  L 38.211 7.3.2.2
        mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2;  //  R 38.211 7.3.2.2
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        mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id;
        mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
        mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id;
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        // type0-pdcch search space
        float big_o;
        float big_m;
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        uint32_t temp;
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        SFN_C_TYPE sfn_c = SFN_C_IMPOSSIBLE; // only valid for mux=1
        uint32_t n_c = UINT_MAX;
        uint32_t number_of_search_space_per_slot = UINT_MAX;
        uint32_t first_symbol_index = UINT_MAX;
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        uint32_t search_space_duration; // element of search space
        uint32_t coreset_duration;      // element of coreset
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        //  38.213 table 10.1-1
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        /// MUX PATTERN 1
        if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR1){
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            big_o = table_38213_13_11_c1[index_4lsb];
            number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
            big_m = table_38213_13_11_c3[index_4lsb];

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            temp = (uint32_t)(big_o*pow(2, scs_pdcch)) + (uint32_t)(ssb_index*big_m);
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            n_c = temp / num_slot_per_frame;
            if((temp/num_slot_per_frame) & 0x1){
                sfn_c = SFN_C_MOD_2_EQ_1;
            }else{
                sfn_c = SFN_C_MOD_2_EQ_0;
            }

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            if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (ssb_index&1)){
                first_symbol_index = num_symbols;
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            }else{
                first_symbol_index = table_38213_13_11_c4[index_4lsb];
            }
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            //  38.213 chapter 13: over two consecutive slots
            search_space_duration = 2;
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        }

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        if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){
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            big_o = table_38213_13_12_c1[index_4lsb];
            number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
            big_m = table_38213_13_12_c3[index_4lsb];

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            if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (ssb_index&1)){
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                first_symbol_index = 7;
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            }else if((index_4lsb == 6 || index_4lsb == 7 || index_4lsb == 8 || index_4lsb == 11) && (ssb_index&1)){
                first_symbol_index = num_symbols;
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            }else{
                first_symbol_index = 0;
            }
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            //  38.213 chapter 13: over two consecutive slots
            search_space_duration = 2;
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        }

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        /// MUX PATTERN 2
        if(mac->type0_pdcch_ss_mux_pattern == 2){
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            if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_60kHz)){
                //  38.213 Table 13-13
                AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n");
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                //  PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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                //sfn_c = SFN_C_EQ_SFN_SSB;
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                n_c = get_ssb_slot(ssb_index);
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                switch(ssb_index & 0x3){    //  ssb_index(i) mod 4
                    case 0: 
                        first_symbol_index = 0;
                        break;
                    case 1: 
                        first_symbol_index = 1;
                        break;
                    case 2: 
                        first_symbol_index = 6;
                        break;
                    case 3: 
                        first_symbol_index = 7;
                        break;
                    default: break; 
                }
                
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            }else if((scs_ssb == scs_240kHz) && (scs_pdcch == scs_120kHz)){
                //  38.213 Table 13-14
                AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
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                //  PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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                //sfn_c = SFN_C_EQ_SFN_SSB;
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                n_c = get_ssb_slot(ssb_index);
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                switch(ssb_index & 0x7){    //  ssb_index(i) mod 8
                    case 0: 
                        first_symbol_index = 0;
                        break;
                    case 1: 
                        first_symbol_index = 1;
                        break;
                    case 2: 
                        first_symbol_index = 2;
                        break;
                    case 3: 
                        first_symbol_index = 3;
                        break;
                    case 4: 
                        first_symbol_index = 12;
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                        n_c = get_ssb_slot(ssb_index) - 1;
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                        break;
                    case 5: 
                        first_symbol_index = 13;
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                        n_c = get_ssb_slot(ssb_index) - 1;
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                        break;
                    case 6: 
                        first_symbol_index = 0;
                        break;
                    case 7: 
                        first_symbol_index = 1;
                        break;
                    default: break; 
                }
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            }else{ ; }
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            //  38.213 chapter 13: over one slot
            search_space_duration = 1;
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        }

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        /// MUX PATTERN 3
        if(mac->type0_pdcch_ss_mux_pattern == 3){
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            if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_120kHz)){
                //  38.213 Table 13-15
                AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n");
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                //  PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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                //sfn_c = SFN_C_EQ_SFN_SSB;
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                n_c = get_ssb_slot(ssb_index);
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                switch(ssb_index & 0x3){    //  ssb_index(i) mod 4
                    case 0: 
                        first_symbol_index = 4;
                        break;
                    case 1: 
                        first_symbol_index = 8;
                        break;
                    case 2: 
                        first_symbol_index = 2;
                        break;
                    case 3: 
                        first_symbol_index = 6;
                        break;
                    default: break; 
                }
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            }else{ ; }
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            //  38.213 chapter 13: over one slot
            search_space_duration = 1;
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        }
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	AssertFatal(number_of_search_space_per_slot!=UINT_MAX,"");
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        coreset_duration = num_symbols * number_of_search_space_per_slot;

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        mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0];
        mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1];
        mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2];   //  CCE aggregation level = 4
        mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3];   //  CCE aggregation level = 8
        mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4];   //  CCE aggregation level = 16
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        mac->type0_pdcch_dci_config.duration = search_space_duration;
        mac->type0_pdcch_dci_config.coreset.duration = coreset_duration;   //  coreset
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	AssertFatal(first_symbol_index!=UINT_MAX,"");
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        mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;

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	AssertFatal(sfn_c!=SFN_C_IMPOSSIBLE,"");
	AssertFatal(n_c!=UINT_MAX,"");
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        mac->type0_pdcch_ss_sfn_c = sfn_c;
        mac->type0_pdcch_ss_n_c = n_c;
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	    // fill in the elements in config request inside P5 message
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        mac->phy_config.Mod_id = module_id;
        mac->phy_config.CC_id = cc_id;
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	    mac->phy_config.config_req.pbch_config.system_frame_number = frame;    //  after calculation
	    mac->phy_config.config_req.pbch_config.subcarrier_spacing_common = mac->mib->subCarrierSpacingCommon;
	    mac->phy_config.config_req.pbch_config.ssb_subcarrier_offset = ssb_subcarrier_offset;  //  after calculation
	    mac->phy_config.config_req.pbch_config.dmrs_type_a_position = mac->mib->dmrs_TypeA_Position;
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	    mac->phy_config.config_req.pbch_config.pdcch_config_sib1 = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero) * 16 + (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
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	    mac->phy_config.config_req.pbch_config.cell_barred = mac->mib->cellBarred;
	    mac->phy_config.config_req.pbch_config.intra_frequency_reselection = mac->mib->intraFreqReselection;
	    mac->phy_config.config_req.pbch_config.half_frame_bit = half_frame_bit;
	    mac->phy_config.config_req.pbch_config.ssb_index = ssb_index;
	    mac->phy_config.config_req.config_mask |= FAPI_NR_CONFIG_REQUEST_MASK_PBCH;
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	    if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL){
		mac->if_module->phy_config_request(&mac->phy_config);
	    }
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	    proc->decoded_frame_rx=frame;
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    //}
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    return 0;
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}
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//  TODO: change to UE parameter, scs: 15KHz, slot duration: 1ms
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uint32_t get_ssb_frame(uint32_t test){
	return test;
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}

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// Performs :
// 1. TODO: Call RRC for link status return to PHY
// 2. TODO: Perform SR/BSR procedures for scheduling feedback
// 3. TODO: Perform PHR procedures
NR_UE_L2_STATE_t nr_ue_scheduler(
    const module_id_t module_id,
    const uint8_t gNB_index,
    const int cc_id,
    const frame_t rx_frame,
    const slot_t rx_slot,
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    const int32_t ssb_index,
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    const frame_t tx_frame,
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    const slot_t tx_slot ){

    uint32_t search_space_mask = 0;
    NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
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    //  check type0 from 38.213 13
    if(ssb_index != -1){

        if(mac->type0_pdcch_ss_mux_pattern == 1){
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            //	38.213 chapter 13
            if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
            	search_space_mask = search_space_mask | type0_pdcch;
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                mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
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            }
            if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) &&  (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
            	search_space_mask = search_space_mask | type0_pdcch;
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                mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
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            }
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        }
        if(mac->type0_pdcch_ss_mux_pattern == 2){
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            //	38.213 Table 13-13, 13-14
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            if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
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                search_space_mask = search_space_mask | type0_pdcch;
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                mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
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            }
        }
        if(mac->type0_pdcch_ss_mux_pattern == 3){
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        	//	38.213 Table 13-15
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            if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
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                search_space_mask = search_space_mask | type0_pdcch;
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                mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
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            }
        }
    }
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    fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
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    //  Type0 PDCCH search space
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    if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
        mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
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        dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
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        dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
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	/*
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    	dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa;	//	to be set
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    	dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106;	//	to be set
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	LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n",
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	       dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti,
	       dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP);  
	*/   
        dl_config->number_pdus = dl_config->number_pdus + 1;
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    }

    if(search_space_mask & type0a_pdcch){
    }

    if(search_space_mask & type1_pdcch){
    }

    if(search_space_mask & type2_pdcch){
    }

    if(search_space_mask & type3_pdcch){
    }


    mac->scheduled_response.dl_config = dl_config;
    
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	return UE_CONNECTION_OK;
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}

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//////////////
/*
 * This code contains all the functions needed to process all dci fields.
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 * These tables and functions are going to be called by function nr_ue_process_dci
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 */
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// table_7_3_1_1_2_2_3_4_5 contains values for number of layers and precoding information for tables 7.3.1.1.2-2/3/4/5 from TS 38.212 subclause 7.3.1.1.2
// the first 6 columns contain table 7.3.1.1.2-2: Precoding information and number of layers, for 4 antenna ports, if transformPrecoder=disabled and maxRank = 2 or 3 or 4
// next six columns contain table 7.3.1.1.2-3: Precoding information and number of layers for 4 antenna ports, if transformPrecoder= enabled, or if transformPrecoder=disabled and maxRank = 1
// next four columns contain table 7.3.1.1.2-4: Precoding information and number of layers, for 2 antenna ports, if transformPrecoder=disabled and maxRank = 2
// next four columns contain table 7.3.1.1.2-5: Precoding information and number of layers, for 2 antenna ports, if transformPrecoder= enabled, or if transformPrecoder= disabled and maxRank = 1
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uint8_t table_7_3_1_1_2_2_3_4_5[64][20] = {
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{1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0},
{1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1},
{1,  2,  1,  2,  1,  2,  1,  2,  1,  2,  1,  2,  2,  0,  2,  0,  1,  2,  0,  0},
{1,  3,  1,  3,  1,  3,  1,  3,  1,  3,  1,  3,  1,  2,  0,  0,  1,  3,  0,  0},
{2,  0,  2,  0,  2,  0,  1,  4,  1,  4,  0,  0,  1,  3,  0,  0,  1,  4,  0,  0},
{2,  1,  2,  1,  2,  1,  1,  5,  1,  5,  0,  0,  1,  4,  0,  0,  1,  5,  0,  0},
{2,  2,  2,  2,  2,  2,  1,  6,  1,  6,  0,  0,  1,  5,  0,  0,  0,  0,  0,  0},
{2,  3,  2,  3,  2,  3,  1,  7,  1,  7,  0,  0,  2,  1,  0,  0,  0,  0,  0,  0},
{2,  4,  2,  4,  2,  4,  1,  8,  1,  8,  0,  0,  2,  2,  0,  0,  0,  0,  0,  0},
{2,  5,  2,  5,  2,  5,  1,  9,  1,  9,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  0,  3,  0,  3,  0,  1,  10, 1,  10, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{4,  0,  4,  0,  4,  0,  1,  11, 1,  11, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  4,  1,  4,  0,  0,  1,  12, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  5,  1,  5,  0,  0,  1,  13, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  6,  1,  6,  0,  0,  1,  14, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  7,  1,  7,  0,  0,  1,  15, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  8,  1,  8,  0,  0,  1,  16, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  9,  1,  9,  0,  0,  1,  17, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  10, 1,  10, 0,  0,  1,  18, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  11, 1,  11, 0,  0,  1,  19, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  6,  2,  6,  0,  0,  1,  20, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  7,  2,  7,  0,  0,  1,  21, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  8,  2,  8,  0,  0,  1,  22, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  9,  2,  9,  0,  0,  1,  23, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  10, 2,  10, 0,  0,  1,  24, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  11, 2,  11, 0,  0,  1,  25, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  12, 2,  12, 0,  0,  1,  26, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  13, 2,  13, 0,  0,  1,  27, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  1,  3,  1,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  2,  3,  2,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{4,  1,  4,  1,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{4,  2,  4,  2,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  12, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  13, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  14, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  15, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  16, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  17, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  18, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  19, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  20, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  21, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  22, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  23, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  24, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  25, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  26, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{1,  27, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  14, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  15, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  16, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  17, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  18, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  19, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  20, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{2,  21, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  3,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  4,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  5,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{3,  6,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{4,  3,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{4,  4,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0},
{0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0}
};
uint8_t table_7_3_1_1_2_12[14][3] = {
{1,0,1},
{1,1,1},
{2,0,1},
{2,1,1},
{2,2,1},
{2,3,1},
{2,0,2},
{2,1,2},
{2,2,2},
{2,3,2},
{2,4,2},
{2,5,2},
{2,6,2},
{2,7,2}
};
uint8_t table_7_3_1_1_2_13[10][4] = {
{1,0,1,1},
{2,0,1,1},
{2,2,3,1},
{2,0,2,1},
{2,0,1,2},
{2,2,3,2},
{2,4,5,2},
{2,6,7,2},
{2,0,4,2},
{2,2,6,2}
};
uint8_t table_7_3_1_1_2_14[3][5] = {
{2,0,1,2,1},
{2,0,1,4,2},
{2,2,3,6,2}
};
uint8_t table_7_3_1_1_2_15[4][6] = {
{2,0,1,2,3,1},
{2,0,1,4,5,2},
{2,2,3,6,7,2},
{2,0,2,4,6,2}
};
uint8_t table_7_3_1_1_2_16[12][2] = {
{1,0},
{1,1},
{2,0},
{2,1},
{2,2},
{2,3},
{3,0},
{3,1},
{3,2},
{3,3},
{3,4},
{3,5}
};
uint8_t table_7_3_1_1_2_17[7][3] = {
{1,0,1},
{2,0,1},
{2,2,3},
{3,0,1},
{3,2,3},
{3,4,5},
{2,0,2}
};
uint8_t table_7_3_1_1_2_18[3][4] = {
{2,0,1,2},
{3,0,1,2},
{3,3,4,5}
};
uint8_t table_7_3_1_1_2_19[2][5] = {
{2,0,1,2,3},
{3,0,1,2,3}
};
uint8_t table_7_3_1_1_2_20[28][3] = {
{1,0,1},
{1,1,1},
{2,0,1},
{2,1,1},
{2,2,1},
{2,3,1},
{3,0,1},
{3,1,1},
{3,2,1},
{3,3,1},
{3,4,1},
{3,5,1},
{3,0,2},
{3,1,2},
{3,2,2},
{3,3,2},
{3,4,2},
{3,5,2},
{3,6,2},
{3,7,2},
{3,8,2},
{3,9,2},
{3,10,2},
{3,11,2},
{1,0,2},
{1,1,2},
{1,6,2},
{1,7,2}
};
uint8_t table_7_3_1_1_2_21[19][4] = {
{1,0,1,1},
{2,0,1,1},
{2,2,3,1},
{3,0,1,1},
{3,2,3,1},
{3,4,5,1},
{2,0,2,1},
{3,0,1,2},
{3,2,3,2},
{3,4,5,2},
{3,6,7,2},
{3,8,9,2},
{3,10,11,2},
{1,0,1,2},
{1,6,7,2},
{2,0,1,2},
{2,2,3,2},
{2,6,7,2},
{2,8,9,2}
};
uint8_t table_7_3_1_1_2_22[6][5] = {
{2,0,1,2,1},
{3,0,1,2,1},
{3,3,4,5,1},
{3,0,1,6,2},
{3,2,3,8,2},
{3,4,5,10,2}
};
uint8_t table_7_3_1_1_2_23[5][6] = {
{2,0,1,2,3,1},
{3,0,1,2,3,1},
{3,0,1,6,7,2},
{3,2,3,8,9,2},
{3,4,5,10,11,2}
};
uint8_t table_7_3_2_3_3_1[12][5] = {
{1,0,0,0,0},
{1,1,0,0,0},
{1,0,1,0,0},
{2,0,0,0,0},
{2,1,0,0,0},
{2,2,0,0,0},
{2,3,0,0,0},
{2,0,1,0,0},
{2,2,3,0,0},
{2,0,1,2,0},
{2,0,1,2,3},
{2,0,2,0,0}
};
uint8_t table_7_3_2_3_3_2_oneCodeword[31][6] = {
{1,0,0,0,0,1},
{1,1,0,0,0,1},
{1,0,1,0,0,1},
{2,0,0,0,0,1},
{2,1,0,0,0,1},
{2,2,0,0,0,1},
{2,3,0,0,0,1},
{2,0,1,0,0,1},
{2,2,3,0,0,1},
{2,0,1,2,0,1},
{2,0,1,2,3,1},
{2,0,2,0,0,1},
{2,0,0,0,0,2},
{2,1,0,0,0,2},
{2,2,0,0,0,2},
{2,3,0,0,0,2},
{2,4,0,0,0,2},
{2,5,0,0,0,2},
{2,6,0,0,0,2},
{2,7,0,0,0,2},
{2,0,1,0,0,2},
{2,2,3,0,0,2},
{2,4,5,0,0,2},
{2,6,7,0,0,2},
{2,0,4,0,0,2},
{2,2,6,0,0,2},
{2,0,1,4,0,2},
{2,2,3,6,0,2},
{2,0,1,4,5,2},
{2,2,3,6,7,2},
{2,0,2,4,6,2}
};
uint8_t table_7_3_2_3_3_2_twoCodeword[4][10] = {
{2,0,1,2,3,4,0,0,0,2},
{2,0,1,2,3,4,6,0,0,2},
{2,0,1,2,3,4,5,6,0,2},
{2,0,1,2,3,4,5,6,7,2}
};
uint8_t table_7_3_2_3_3_3_oneCodeword[24][5] = {
{1,0,0,0,0},
{1,1,0,0,0},
{1,0,1,0,0},
{2,0,0,0,0},
{2,1,0,0,0},
{2,2,0,0,0},
{2,3,0,0,0},
{2,0,1,0,0},
{2,2,3,0,0},
{2,0,1,2,0},
{2,0,1,2,3},
{3,0,0,0,0},
{3,1,0,0,0},
{3,2,0,0,0},
{3,3,0,0,0},
{3,4,0,0,0},
{3,5,0,0,0},
{3,0,1,0,0},
{3,2,3,0,0},
{3,4,5,0,0},
{3,0,1,2,0},
{3,3,4,5,0},
{3,0,1,2,3},
{2,0,2,0,0}
};
uint8_t table_7_3_2_3_3_3_twoCodeword[2][7] = {
{3,0,1,2,3,4,0},
{3,0,1,2,3,4,5}
};
uint8_t table_7_3_2_3_3_4_oneCodeword[58][6] = {
{1,0,0,0,0,1},
{1,1,0,0,0,1},
{1,0,1,0,0,1},
{2,0,0,0,0,1},
{2,1,0,0,0,1},
{2,2,0,0,0,1},
{2,3,0,0,0,1},
{2,0,1,0,0,1},
{2,2,3,0,0,1},
{2,0,1,2,0,1},
{2,0,1,2,3,1},
{3,0,0,0,0,1},
{3,1,0,0,0,1},
{3,2,0,0,0,1},
{3,3,0,0,0,1},
{3,4,0,0,0,1},
{3,5,0,0,0,1},
{3,0,1,0,0,1},
{3,2,3,0,0,1},
{3,4,5,0,0,1},
{3,0,1,2,0,1},
{3,3,4,5,0,1},
{3,0,1,2,3,1},
{2,0,2,0,0,1},
{3,0,0,0,0,2},
{3,1,0,0,0,2},
{3,2,0,0,0,2},
{3,3,0,0,0,2},
{3,4,0,0,0,2},
{3,5,0,0,0,2},
{3,6,0,0,0,2},
{3,7,0,0,0,2},
{3,8,0,0,0,2},
{3,9,0,0,0,2},
{3,10,0,0,0,2},
{3,11,0,0,0,2},
{3,0,1,0,0,2},
{3,2,3,0,0,2},
{3,4,5,0,0,2},
{3,6,7,0,0,2},
{3,8,9,0,0,2},
{3,10,11,0,0,2},
{3,0,1,6,0,2},
{3,2,3,8,0,2},
{3,4,5,10,0,2},
{3,0,1,6,7,2},
{3,2,3,8,9,2},
{3,4,5,10,11,2},
{1,0,0,0,0,2},
{1,1,0,0,0,2},
{1,6,0,0,0,2},
{1,7,0,0,0,2},
{1,0,1,0,0,2},
{1,6,7,0,0,2},
{2,0,1,0,0,2},
{2,2,3,0,0,2},
{2,6,7,0,0,2},
{2,8,9,0,0,2}
};
uint8_t table_7_3_2_3_3_4_twoCodeword[6][10] = {
{3,0,1,2,3,4,0,0,0,1},
{3,0,1,2,3,4,5,0,0,1},
{2,0,1,2,3,6,0,0,0,2},
{2,0,1,2,3,6,8,0,0,2},
{2,0,1,2,3,6,7,8,0,2},
{2,0,1,2,3,6,7,8,9,2}
};
1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
int8_t nr_ue_process_dci_freq_dom_resource_assignment(
  fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
  fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
  uint16_t n_RB_ULBWP,
  uint16_t n_RB_DLBWP,
  uint16_t riv
){
  uint16_t l_RB;
  uint16_t start_RB;
  uint16_t tmp_RIV;

/*
 * TS 38.214 subclause 5.1.2.2 Resource allocation in frequency domain (downlink)
 * when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used
 */
  if(dlsch_config_pdu != NULL){
  /*
   * TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
   */
  /*
   * TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1
   */
    // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
    // RIV = n_RB_DLBWP * (l_RB - 1) + start_RB                                  if (l_RB - 1) <= floor (n_RB_DLBWP/2)
    // RIV = n_RB_DLBWP * (n_RB_DLBWP - l_RB + 1) + (n_RB_DLBWP - 1 - start_RB)  if (l_RB - 1)  > floor (n_RB_DLBWP/2)
    // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2)
    l_RB = floor(riv/n_RB_DLBWP) + 1;
    start_RB = riv%n_RB_DLBWP;
    // if (l_RB - 1)  > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines
    tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB;
1113
    if ((tmp_RIV != riv) || ((start_RB+l_RB)>n_RB_DLBWP)) { // then (l_RB - 1)  > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB
1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
      l_RB = n_RB_DLBWP - l_RB + 2;
      start_RB = n_RB_DLBWP - start_RB - 1;
    }
    dlsch_config_pdu->number_rbs = l_RB;
    dlsch_config_pdu->start_rb = start_RB;
  }
  if(ulsch_config_pdu != NULL){
/*
 * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink)
 */
  /*
   * TS 38.214 subclause 6.1.2.2.1 Uplink resource allocation type 0
   */
  /*
   * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1
   */
    // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
    // RIV = n_RB_ULBWP * (l_RB - 1) + start_RB                                  if (l_RB - 1) <= floor (n_RB_ULBWP/2)
    // RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB)  if (l_RB - 1)  > floor (n_RB_ULBWP/2)
    // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2)
    l_RB = floor(riv/n_RB_ULBWP) + 1;
    start_RB = riv%n_RB_ULBWP;
    // if (l_RB - 1)  > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines
    tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB;
    if (tmp_RIV != riv) { // then (l_RB - 1)  > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB
        l_RB = n_RB_ULBWP - l_RB + 2;
        start_RB = n_RB_ULBWP - start_RB - 1;
    }
    ulsch_config_pdu->number_rbs = l_RB;
    ulsch_config_pdu->start_rb = start_RB;
  }
  return 0;
}

int8_t nr_ue_process_dci_time_dom_resource_assignment(
  fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
  fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
  uint8_t time_domain_ind,
1152
  long dmrs_typeA_pos //0=pos2,1=pos3
1153
){
1154 1155 1156
  uint8_t k_offset=0;
  uint8_t sliv_S=0;
  uint8_t sliv_L=0;
1157
  uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
1158 1159 1160 1161 1162 1163 1164
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?12:11}, // row index 1
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9},  // row index 2
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8},   // row index 3
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6},   // row index 4
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4},   // row index 5
  {0,(dmrs_typeA_pos == 0)?9:10,(dmrs_typeA_pos == 0)?4:4},   // row index 6
  {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4},   // row index 7
1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
  {0,5,7},  // row index 8
  {0,5,2},  // row index 9
  {0,9,2},  // row index 10
  {0,12,2}, // row index 11
  {0,1,13}, // row index 12
  {0,1,6},  // row index 13
  {0,2,4},  // row index 14
  {0,4,7},  // row index 15
  {0,8,4}   // row index 16
  };
1175
  /*uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
1176 1177 1178 1179 1180 1181 1182
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5},   // row index 1
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9},  // row index 2
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8},   // row index 3
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6},   // row index 4
  {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4},   // row index 5
  {0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2},   // row index 6
  {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4},   // row index 7
1183 1184 1185 1186 1187 1188 1189 1190 1191
  {0,5,6},  // row index 8
  {0,5,2},  // row index 9
  {0,9,2},  // row index 10
  {0,10,2}, // row index 11
  {0,1,11}, // row index 12
  {0,1,6},  // row index 13
  {0,2,4},  // row index 14
  {0,4,6},  // row index 15
  {0,8,4}   // row index 16
1192 1193
  };*/
  /*uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206
  {0,2,2},  // row index 1
  {0,4,2},  // row index 2
  {0,6,2},  // row index 3
  {0,8,2},  // row index 4
  {0,10,2}, // row index 5
  {1,2,2},  // row index 6
  {1,4,2},  // row index 7
  {0,2,4},  // row index 8
  {0,4,4},  // row index 9
  {0,6,4},  // row index 10
  {0,8,4},  // row index 11
  {0,10,4}, // row index 12
  {0,2,7},  // row index 13
1207
  {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11},  // row index 14
1208 1209
  {1,2,4},  // row index 15
  {0,0,0}   // row index 16
1210 1211
  };*/
  /*uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224
  {0,2,2},  // row index 1
  {0,4,2},  // row index 2
  {0,6,2},  // row index 3
  {0,8,2},  // row index 4
  {0,10,2}, // row index 5
  {0,0,0},  // row index 6
  {0,0,0},  // row index 7
  {0,2,4},  // row index 8
  {0,4,4},  // row index 9
  {0,6,4},  // row index 10
  {0,8,4},  // row index 11
  {0,10,4}, // row index 12
  {0,2,7},  // row index 13
1225
  {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11},  // row index 14
1226 1227
  {0,0,6},  // row index 15
  {0,2,6}   // row index 16
1228
  };*/
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
  uint8_t mu_pusch = 1;
  // definition table j Table 6.1.2.1.1-4
  uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1;
  uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1
  {j,  0,14}, // row index 1
  {j,  0,12}, // row index 2
  {j,  0,10}, // row index 3
  {j,  2,10}, // row index 4
  {j,  4,10}, // row index 5
  {j,  4,8},  // row index 6
  {j,  4,6},  // row index 7
  {j+1,0,14}, // row index 8
  {j+1,0,12}, // row index 9
  {j+1,0,10}, // row index 10
  {j+2,0,14}, // row index 11
  {j+2,0,12}, // row index 12
  {j+2,0,10}, // row index 13
  {j,  8,6},  // row index 14
  {j+3,0,14}, // row index 15
  {j+3,0,10}  // row index 16
  };
1250
  /*uint8_t table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1
1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
  {j,  0,8},  // row index 1
  {j,  0,12}, // row index 2
  {j,  0,10}, // row index 3
  {j,  2,10}, // row index 4
  {j,  4,4},  // row index 5
  {j,  4,8},  // row index 6
  {j,  4,6},  // row index 7
  {j+1,0,8},  // row index 8
  {j+1,0,12}, // row index 9
  {j+1,0,10}, // row index 10
  {j+2,0,6},  // row index 11
  {j+2,0,12}, // row index 12
  {j+2,0,10}, // row index 13
  {j,  8,4},  // row index 14
  {j+3,0,8},  // row index 15
  {j+3,0,10}  // row index 16
1267
  };*/
1268 1269 1270 1271 1272

/*
 * TS 38.214 subclause 5.1.2.1 Resource allocation in time domain (downlink)
 */
  if(dlsch_config_pdu != NULL){
1273 1274 1275
      k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
      sliv_S   = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1];
      sliv_L   = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2];
1276 1277 1278 1279 1280 1281 1282 1283 1284
      // k_offset = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
      // sliv_S   = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
      // sliv_L   = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
      // k_offset = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][0];
      // sliv_S   = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][1];
      // sliv_L   = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][2];
      // k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0];
      // sliv_S   = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1];
      // sliv_L   = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2];
1285
      dlsch_config_pdu->frame_offset = k_offset;
1286 1287 1288 1289 1290 1291
      dlsch_config_pdu->number_symbols = sliv_L;
      dlsch_config_pdu->start_symbol = sliv_S;
  }	/*
 * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink)
 */
  if(ulsch_config_pdu != NULL){
1292 1293 1294
      k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
      sliv_S   = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1];
      sliv_L   = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2];
1295 1296 1297
      // k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
      // sliv_S   = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
      // sliv_L   = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
1298
      ulsch_config_pdu->frame_offset = k_offset;
1299 1300 1301 1302 1303 1304 1305
      ulsch_config_pdu->number_symbols = sliv_L;
      ulsch_config_pdu->start_symbol = sliv_S;
  }
  return 0;
}
//////////////

1306
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){
1307 1308

    NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
1309 1310
    fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
    fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
1311
    
1312 1313 1314
    //const uint16_t n_RB_DLBWP = dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP; //make sure this has been set
    const uint16_t n_RB_DLBWP = mac->initial_bwp_dl.N_RB;
    const uint16_t n_RB_ULBWP = mac->initial_bwp_ul.N_RB;
1315

1316
    LOG_I(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP);
1317 1318 1319

    switch(dci_format){
        case format0_0:
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
/*
 *  with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI
 *    0  IDENTIFIER_DCI_FORMATS:
 *    10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    25 NDI:
 *    26 RV:
 *    27 HARQ_PROCESS_NUMBER:
 *    32 TPC_PUSCH:
 *    49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
 *    50 SUL_IND_0_0:
 */
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Florian Kaltenberger committed
1334
            ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
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            ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
            fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
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        /* IDENTIFIER_DCI_FORMATS */
        /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
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            nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
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        /* TIME_DOM_RESOURCE_ASSIGNMENT */
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            nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
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        /* FREQ_HOPPING_FLAG */
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            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
                (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
              ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
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        /* MCS */
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            ulsch_config_pdu_0_0->mcs = dci->mcs;
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        /* NDI */
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            ulsch_config_pdu_0_0->ndi = dci->ndi;
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        /* RV */
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            ulsch_config_pdu_0_0->rv = dci->rv;
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        /* HARQ_PROCESS_NUMBER */
1353
            ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number;
1354
        /* TPC_PUSCH */
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            // according to TS 38.213 Table Table 7.1.1-1
            if (dci->tpc_pusch == 0) {
              ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1;
              ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4;
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            }
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            if (dci->tpc_pusch == 1) {
              ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0;
              ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1;
            }
            if (dci->tpc_pusch == 2) {
              ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1;
              ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1;
            }
            if (dci->tpc_pusch == 3) {
              ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3;
              ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4;
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            }
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        /* SUL_IND_0_0 */ // To be implemented, FIXME!!!
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            ul_config->number_pdus = ul_config->number_pdus + 1;
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            break;

        case format0_1:
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/*
 *  with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI
 *    0  IDENTIFIER_DCI_FORMATS:
 *    1  CARRIER_IND
 *    2  SUL_IND_0_1
 *    7  BANDWIDTH_PART_IND
 *    10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    25 NDI:
 *    26 RV:
 *    27 HARQ_PROCESS_NUMBER:
 *    29 FIRST_DAI
 *    30 SECOND_DAI
 *    32 TPC_PUSCH:
 *    36 SRS_RESOURCE_IND:
 *    37 PRECOD_NBR_LAYERS:
 *    38 ANTENNA_PORTS:
 *    40 SRS_REQUEST:
 *    42 CSI_REQUEST:
 *    43 CBGTI
 *    45 PTRS_DMRS
 *    46 BETA_OFFSET_IND
 *    47 DMRS_SEQ_INI
 *    48 UL_SCH_IND
 *    49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
 */
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Florian Kaltenberger committed
1406
            ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
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            ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
            fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
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        /* IDENTIFIER_DCI_FORMATS */
        /* CARRIER_IND */
        /* SUL_IND_0_1 */
        /* BANDWIDTH_PART_IND */
            ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind;
        /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
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            nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
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        /* TIME_DOM_RESOURCE_ASSIGNMENT */
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            nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
1418
        /* FREQ_HOPPING_FLAG */
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            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
                (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
              ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
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        /* MCS */
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            ulsch_config_pdu_0_1->mcs = dci->mcs;
1424
        /* NDI */
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            ulsch_config_pdu_0_1->ndi = dci->ndi;
1426
        /* RV */
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            ulsch_config_pdu_0_1->rv = dci->rv;
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        /* HARQ_PROCESS_NUMBER */
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            ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number;
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        /* FIRST_DAI */ //To be implemented, FIXME!!!
        /* SECOND_DAI */ //To be implemented, FIXME!!!
        /* TPC_PUSCH */
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            // according to TS 38.213 Table Table 7.1.1-1
            if (dci->tpc_pusch == 0) {
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              ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1;
              ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4;
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            }
1438
            if (dci->tpc_pusch == 1) {
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              ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0;
              ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1;
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            }
            if (dci->tpc_pusch == 2) {
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              ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1;
              ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1;
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            }
            if (dci->tpc_pusch == 3) {
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              ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3;
              ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4;
            }
        /* SRS_RESOURCE_IND */
            //FIXME!!
        /* PRECOD_NBR_LAYERS */
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_nonCodebook));
              // 0 bits if the higher layer parameter txConfig = nonCodeBook
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_codebook)){
              uint8_t n_antenna_port = 0; //FIXME!!!
              if (n_antenna_port == 1); // 1 antenna port and the higher layer parameter txConfig = codebook 0 bits
              if (n_antenna_port == 4){ // 4 antenna port and the higher layer parameter txConfig = codebook
                // Table 7.3.1.1.2-2: transformPrecoder=disabled and maxRank = 2 or 3 or 4
                if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
                     && ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2) ||
                         (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) ||
                         (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){
                    if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
                      ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0];
                      ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1];
                    }
                    if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
                      ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2];
                      ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3];
                    }
                    if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
                      ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4];
                      ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5];
                    }
                }
                // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1
                if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
                  || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
                  && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7];
                  }
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9];
                  }
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11];
                  }
                }
              }
              if (n_antenna_port == 4){ // 2 antenna port and the higher layer parameter txConfig = codebook
                // Table 7.3.1.1.2-4: transformPrecoder=disabled and maxRank = 2
                if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
                  && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13];
                  }
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15];
                  }
                }
                // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1
                if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
                  || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
                  && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17];
                  }
                  if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
                    ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18];
                    ulsch_config_pdu_0_1->tpmi     = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19];
                  }
                }
              }
            }
        /* ANTENNA_PORTS */
            uint8_t rank=0; // We need to initialize rank FIXME!!!
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6
              ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
              ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports;
            }
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7
              ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
              ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports);
              ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
1537
            }
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            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11
              if (rank == 1){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports);
              }
              if (rank == 2){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0;
                ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1;
              }
              if (rank == 3){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
                ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
                ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
              }
              if (rank == 4){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
                ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
                ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
                ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
              }
            }
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15
              if (rank == 1){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
                ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1;
              }
              if (rank == 2){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
              }
              if (rank == 3){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3];
                ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
              }
              if (rank == 4){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3];
                ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4];
                ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
              }
            }
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19
              if (rank == 1){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
              }
              if (rank == 2){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1;
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2];
              }
              if (rank == 3){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3];
              }
              if (rank == 4){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2;
                ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
                ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
                ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
                ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
              }
            }
            if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
            (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23
              if (rank == 1){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0];
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2];
              }
              if (rank == 2){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0];
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3];
              }
              if (rank == 3){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0];
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3];
                ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4];
                }
              if (rank == 4){
                ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0];
                ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1];
                ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2];
                ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3];
                ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4];
                ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5];
              }
            }
        /* SRS_REQUEST */
            // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
            ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
        /* CSI_REQUEST */
            ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request;
        /* CBGTI */
            ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti;
        /* PTRS_DMRS */
            if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
                 (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) ||
                ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
                 (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){
            } else {
              ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs;
            }
        /* BETA_OFFSET_IND */
            // Table 9.3-3 in [5, TS 38.213]
            ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind;
        /* DMRS_SEQ_INI */
            // FIXME!!
        /* UL_SCH_IND */
            // A value of "1" indicates UL-SCH shall be transmitted on the PUSCH and
            // a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH

            ul_config->number_pdus = ul_config->number_pdus + 1;
1675 1676 1677
            break;

        case format1_0: 
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727
/*
 *  with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
 *    0  IDENTIFIER_DCI_FORMATS:
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    25 NDI:
 *    26 RV:
 *    27 HARQ_PROCESS_NUMBER:
 *    28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
 *    33 TPC_PUCCH:
 *    34 PUCCH_RESOURCE_IND:
 *    35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
 *    55 RESERVED_NR_DCI
 *  with CRC scrambled by P-RNTI
 *    8  SHORT_MESSAGE_IND
 *    9  SHORT_MESSAGES
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    31 TB_SCALING
 *    55 RESERVED_NR_DCI
 *  with CRC scrambled by SI-RNTI
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    26 RV:
 *    55 RESERVED_NR_DCI
 *  with CRC scrambled by RA-RNTI
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    31 TB_SCALING
 *    55 RESERVED_NR_DCI
 *  with CRC scrambled by TC-RNTI
 *    0  IDENTIFIER_DCI_FORMATS:
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    24 MCS:
 *    25 NDI:
 *    26 RV:
 *    27 HARQ_PROCESS_NUMBER:
 *    28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
 *    33 TPC_PUCCH:
 */
1728
            dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
1729
            //fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_pdu_1_0 = dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
1730
            fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
1731 1732
        /* IDENTIFIER_DCI_FORMATS */
        /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
1733
           nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
1734
        /* TIME_DOM_RESOURCE_ASSIGNMENT */
1735
            nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
1736
        /* VRB_TO_PRB_MAPPING */
1737
            dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
1738
        /* MCS */
1739
            dlsch_config_pdu_1_0->mcs = dci->mcs;
1740
       /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
1741
            dlsch_config_pdu_1_0->ndi = dci->ndi;
1742
        /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
1743
            dlsch_config_pdu_1_0->rv = dci->rv;
1744
        /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
1745
            dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number;
1746
        /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
1747
            dlsch_config_pdu_1_0->dai = dci ->dai;
1748
        /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */
1749 1750 1751 1752 1753
            // according to TS 38.214 Table 5.1.3.2-3
            if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1;
            if (dci->tb_scaling == 1) dlsch_config_pdu_1_0->scaling_factor_S = 0.5;
            if (dci->tb_scaling == 2) dlsch_config_pdu_1_0->scaling_factor_S = 0.25;
            if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table
1754
        /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
1755 1756 1757 1758 1759
            // according to TS 38.213 Table 7.2.1-1
            if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1;
            if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0;
            if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1;
            if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3;
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
        /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
            //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
            //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
            //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
            dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind;
        /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
1771
            dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind;
1772

1773
            LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n",
1774 1775
                    dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti,
                    dl_config->number_pdus);
1776
            LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n",
1777 1778 1779
                    dci->freq_dom_resource_assignment_DL,
                    dlsch_config_pdu_1_0->number_rbs,
                    dlsch_config_pdu_1_0->start_rb);
1780
            LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n",
1781 1782 1783
                    dci->time_dom_resource_assignment,
                    dlsch_config_pdu_1_0->number_symbols,
                    dlsch_config_pdu_1_0->start_symbol);
1784
            LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n",
1785 1786 1787 1788 1789 1790 1791 1792 1793 1794
                  dlsch_config_pdu_1_0->vrb_to_prb_mapping,
                  dlsch_config_pdu_1_0->mcs,
                  dlsch_config_pdu_1_0->ndi,
                  dlsch_config_pdu_1_0->rv,
                  dlsch_config_pdu_1_0->harq_process_nbr,
                  dlsch_config_pdu_1_0->dai,
                  dlsch_config_pdu_1_0->scaling_factor_S,
                  dlsch_config_pdu_1_0->accumulated_delta_PUCCH,
                  dlsch_config_pdu_1_0->pucch_resource_id,
                  dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind);
1795 1796

            dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
1797 1798
	    dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
	    
1799
            LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
1800
            
1801
            dl_config->number_pdus = dl_config->number_pdus + 1;
1802 1803 1804
            break;

        case format1_1:        
1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836
/*
 *  with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
 *    0  IDENTIFIER_DCI_FORMATS:
 *    1  CARRIER_IND:
 *    7  BANDWIDTH_PART_IND:
 *    11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
 *    12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
 *    13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
 *    14 PRB_BUNDLING_SIZE_IND:
 *    15 RATE_MATCHING_IND:
 *    16 ZP_CSI_RS_TRIGGER:
 *    18 TB1_MCS:
 *    19 TB1_NDI:
 *    20 TB1_RV:
 *    21 TB2_MCS:
 *    22 TB2_NDI:
 *    23 TB2_RV:
 *    27 HARQ_PROCESS_NUMBER:
 *    28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
 *    33 TPC_PUCCH:
 *    34 PUCCH_RESOURCE_IND:
 *    35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
 *    38 ANTENNA_PORTS:
 *    39 TCI:
 *    40 SRS_REQUEST:
 *    43 CBGTI:
 *    44 CBGFI:
 *    47 DMRS_SEQ_INI:
 */
            dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
            dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
            fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_1 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
1837 1838 1839 1840 1841
        /* IDENTIFIER_DCI_FORMATS */
        /* CARRIER_IND */
        /* BANDWIDTH_PART_IND */
            dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind;
        /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
1842
            nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
1843
        /* TIME_DOM_RESOURCE_ASSIGNMENT */
1844
            nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
1845
        /* VRB_TO_PRB_MAPPING */
1846 1847
            if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0)
              dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
1848 1849 1850 1851 1852 1853 1854
        /* PRB_BUNDLING_SIZE_IND */
            dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind;
        /* RATE_MATCHING_IND */
            dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind;
        /* ZP_CSI_RS_TRIGGER */
            dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger;
        /* MCS (for transport block 1)*/
1855
            dlsch_config_pdu_1_1->mcs = dci->tb1_mcs;
1856
        /* NDI (for transport block 1)*/
1857
            dlsch_config_pdu_1_1->ndi = dci->tb1_ndi;
1858
        /* RV (for transport block 1)*/
1859
            dlsch_config_pdu_1_1->rv = dci->tb1_rv;
1860
        /* MCS (for transport block 2)*/
1861
            dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs;
1862
        /* NDI (for transport block 2)*/
1863
            dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi;
1864
        /* RV (for transport block 2)*/
1865
            dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv;
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        /* HARQ_PROCESS_NUMBER */
1867
            dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number;
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        /* DAI */
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            dlsch_config_pdu_1_1->dai = dci ->dai;
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        /* TPC_PUCCH */
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            // according to TS 38.213 Table 7.2.1-1
            if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1;
            if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0;
            if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1;
            if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3;
1876
        /* PUCCH_RESOURCE_IND */
1877 1878 1879 1880 1881 1882 1883 1884
            if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
            if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
            if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
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        /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */
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            // according to TS 38.213 Table 9.2.3-1
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            dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind];
        /* ANTENNA_PORTS */
            uint8_t n_codewords = 1; // FIXME!!!
            if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
                (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
            // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
              dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0];
              dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_1[dci->antenna_ports][1];
              dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_1[dci->antenna_ports][2];
              dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_1[dci->antenna_ports][3];
              dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_1[dci->antenna_ports][4];
            }
            if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
                (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
            // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2
              if (n_codewords == 1) {
                dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0];
                dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1];
                dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2];
                dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3];
                dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4];
                dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5];
              }
              if (n_codewords == 1) {
                dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0];
                dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1];
                dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2];
                dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3];
                dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4];
                dlsch_config_pdu_1_1->dmrs_ports[4]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5];
                dlsch_config_pdu_1_1->dmrs_ports[5]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6];
                dlsch_config_pdu_1_1->dmrs_ports[6]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7];
                dlsch_config_pdu_1_1->dmrs_ports[7]     = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8];
                dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9];
              }
            }
            if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
                (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
            // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1
                if (n_codewords == 1) {
                  dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0];
                  dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1];
                  dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2];
                  dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3];
                  dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4];
                }
                if (n_codewords == 1) {
                  dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0];
                  dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1];
                  dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2];
                  dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3];
                  dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4];
                  dlsch_config_pdu_1_1->dmrs_ports[4]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5];
                  dlsch_config_pdu_1_1->dmrs_ports[5]     = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6];
                }
            }
            if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
                (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
            // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2
                if (n_codewords == 1) {
                  dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0];
                  dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1];
                  dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2];
                  dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3];
                  dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4];
                  dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5];
                }
                if (n_codewords == 1) {
                  dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0];
                  dlsch_config_pdu_1_1->dmrs_ports[0]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1];
                  dlsch_config_pdu_1_1->dmrs_ports[1]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2];
                  dlsch_config_pdu_1_1->dmrs_ports[2]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3];
                  dlsch_config_pdu_1_1->dmrs_ports[3]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4];
                  dlsch_config_pdu_1_1->dmrs_ports[4]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5];
                  dlsch_config_pdu_1_1->dmrs_ports[5]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6];
                  dlsch_config_pdu_1_1->dmrs_ports[6]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7];
                  dlsch_config_pdu_1_1->dmrs_ports[7]     = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8];
                  dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9];
                }
            }
        /* TCI */
            if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){
              // 0 bit if higher layer parameter tci-PresentInDCI is not enabled
              // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214]
              dlsch_config_pdu_1_1->tci_state = dci->tci;
            }
        /* SRS_REQUEST */
            // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
            dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
        /* CBGTI */
            dlsch_config_pdu_1_1->cbgti = dci->cbgti;
        /* CBGFI */
            dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi;
        /* DMRS_SEQ_INI */
            //FIXME!!!
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	    dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
	    
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            dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
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            LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
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            dl_config->number_pdus = dl_config->number_pdus + 1;

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            break;

        case format2_0:        
            break;

        case format2_1:        
            break;

        case format2_2:        
            break;

        case format2_3:
            break;

        default: 
            break;
    }


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    if(rnti == SI_RNTI){

    }else if(rnti == mac->ra_rnti){

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    }else if(rnti == P_RNTI){

    }else{  //  c-rnti

        ///  check if this is pdcch order 
        //dci->random_access_preamble_index;
        //dci->ss_pbch_index;
        //dci->prach_mask_index;

        ///  else normal DL-SCH grant
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    }
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    return 0;
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}
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int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){
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    return 0;
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}


void nr_ue_process_mac_pdu(
    module_id_t module_idP,
    uint8_t CC_id,
    uint8_t *pduP, 
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    uint16_t mac_pdu_len, 
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    uint8_t eNB_index){

    uint8_t *pdu_ptr = pduP;
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    uint16_t pdu_len = mac_pdu_len;

    uint16_t mac_ce_len;
    uint16_t mac_subheader_len;
    uint16_t mac_sdu_len;
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    //  For both DL/UL-SCH
    //  Except:
    //   - UL/DL-SCH: fixed-size MAC CE(known by LCID)
    //   - UL/DL-SCH: padding
    //   - UL-SCH:    MSG3 48-bits
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    //  |0|1|2|3|4|5|6|7|  bit-wise
    //  |R|F|   LCID    |
    //  |       L       |
    //  |0|1|2|3|4|5|6|7|  bit-wise
    //  |R|F|   LCID    |
    //  |       L       |
    //  |       L       |

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    //  For both DL/UL-SCH
    //  For:
    //   - UL/DL-SCH: fixed-size MAC CE(known by LCID)
    //   - UL/DL-SCH: padding, for single/multiple 1-oct padding CE(s)
    //   - UL-SCH:    MSG3 48-bits
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    //  |0|1|2|3|4|5|6|7|  bit-wise
    //  |R|R|   LCID    |
    //  LCID: The Logical Channel ID field identifies the logical channel instance of the corresponding MAC SDU or the type of the corresponding MAC CE or padding as described in Tables 6.2.1-1 and 6.2.1-2 for the DL-SCH and UL-SCH respectively. There is one LCID field per MAC subheader. The LCID field size is 6 bits;
    //  L: The Length field indicates the length of the corresponding MAC SDU or variable-sized MAC CE in bytes. There is one L field per MAC subheader except for subheaders corresponding to fixed-sized MAC CEs and padding. The size of the L field is indicated by the F field;
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    //  F: lenght of L is 0:8 or 1:16 bits wide
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    //  R: Reserved bit, set to zero.
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    uint8_t done = 0;
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    while (!done || pdu_len <= 0){
        mac_ce_len = 0x0000;
        mac_subheader_len = 0x0001; //  default to fixed-length subheader = 1-oct
        mac_sdu_len = 0x0000;
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        switch(((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID){
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            //  MAC CE
            case DL_SCH_LCID_CCCH:
                //  MSG4 RRC Connection Setup 38.331
                //  varialbe length
                mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                break;
            case DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH:
                //  38.321 Ch6.1.3.14
                //  varialbe length
                mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                break;
            case DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL:
                //  38.321 Ch6.1.3.13
                //  varialbe length
                mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                break;
            case DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT:
                //  38.321 Ch6.1.3.12
                //  varialbe length
                mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                break;
            case DL_SCH_LCID_SP_SRS_ACTIVATION:
                //  38.321 Ch6.1.3.17
                //  varialbe length
                mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                break;
            
            case DL_SCH_LCID_RECOMMENDED_BITRATE:
                //  38.321 Ch6.1.3.20
                mac_ce_len = 2;
                break;
            case DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT:
                //  38.321 Ch6.1.3.19
                mac_ce_len = 2;
                break;
            case DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT:
                //  38.321 Ch6.1.3.18
                mac_ce_len = 3;
                break;
            case DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT:
                //  38.321 Ch6.1.3.16
                mac_ce_len = 2;
                break;
            case DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH:
                //  38.321 Ch6.1.3.15
                mac_ce_len = 2;
                break;
            case DL_SCH_LCID_DUPLICATION_ACT:
                //  38.321 Ch6.1.3.11
                mac_ce_len = 1;
                break;
            case DL_SCH_LCID_SCell_ACT_4_OCT:
                //  38.321 Ch6.1.3.10
                mac_ce_len = 4;
                break;
            case DL_SCH_LCID_SCell_ACT_1_OCT:
                //  38.321 Ch6.1.3.10
                mac_ce_len = 1;
                break;
            case DL_SCH_LCID_L_DRX:
                //  38.321 Ch6.1.3.6
                //  fixed length but not yet specify.
                mac_ce_len = 0;
                break;
            case DL_SCH_LCID_DRX:
                //  38.321 Ch6.1.3.5
                //  fixed length but not yet specify.
                mac_ce_len = 0;
                break;
            case DL_SCH_LCID_TA_COMMAND:
                //  38.321 Ch6.1.3.4
                mac_ce_len = 1;
                break;
            case DL_SCH_LCID_CON_RES_ID:
                //  38.321 Ch6.1.3.3
                mac_ce_len = 6;
                break;
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            case DL_SCH_LCID_PADDING:
                done = 1;
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                //  end of MAC PDU, can ignore the rest.
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                break;

            //  MAC SDU
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            case DL_SCH_LCID_SRB1:
                //  check if LCID is valid at current time.
            case UL_SCH_LCID_SRB2:
                //  check if LCID is valid at current time.
            case UL_SCH_LCID_SRB3:
                //  check if LCID is valid at current time.
2193
            default:
2194 2195 2196 2197 2198 2199 2200 2201
                //  check if LCID is valid at current time.
                mac_sdu_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
                mac_subheader_len = 2;
                if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
                    mac_sdu_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
                    mac_subheader_len = 3;
                }
                //  DRB LCID by RRC
2202 2203
                break;
        }
2204 2205 2206
        pdu_ptr += ( mac_subheader_len + mac_ce_len + mac_sdu_len );
        pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len );
        AssertFatal(pdu_len >= 0, "[MAC] nr_ue_process_mac_pdu, residual mac pdu length < 0!\n");
2207 2208
    }
}
2209 2210 2211 2212

//---------------------------------------------------------------------------------


2213
unsigned char *nr_parse_header(unsigned char *mac_header,
2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320
			    unsigned char *num_ce,
			    unsigned char *num_sdu,
			    unsigned char *rx_ces,
			    unsigned char *rx_lcids,
			    unsigned short *rx_lengths,
			    unsigned short tb_length)
{

    unsigned char not_done = 1, num_ces = 0, num_cont_res =
	0, num_padding = 0, num_sdus = 0, lcid, num_sdu_cnt;
    unsigned char *mac_header_ptr = mac_header;
    unsigned short length, ce_len = 0;

    while (not_done == 1) {

	if (((SCH_SUBHEADER_FIXED *) mac_header_ptr)->E == 0) {
	    //      printf("E=0\n");
	    not_done = 0;
	}

	lcid = ((SCH_SUBHEADER_FIXED *) mac_header_ptr)->LCID;

	if (lcid < UE_CONT_RES) {
	    //printf("[MAC][UE] header %x.%x.%x\n",mac_header_ptr[0],mac_header_ptr[1],mac_header_ptr[2]);
	    if (not_done == 0) {	// last MAC SDU, length is implicit
		mac_header_ptr++;
		length =
		    tb_length - (mac_header_ptr - mac_header) - ce_len;

		for (num_sdu_cnt = 0; num_sdu_cnt < num_sdus;
		     num_sdu_cnt++) {
		    length -= rx_lengths[num_sdu_cnt];
		}
	    } else {
		if (((SCH_SUBHEADER_LONG *) mac_header_ptr)->F == 1) {
		    length =
			((((SCH_SUBHEADER_LONG *) mac_header_ptr)->
			  L_MSB & 0x7f)
			 << 8) | (((SCH_SUBHEADER_LONG *) mac_header_ptr)->
				  L_LSB & 0xff);
		    mac_header_ptr += 3;
#ifdef DEBUG_HEADER_PARSING
		    LOG_D(MAC, "[UE] parse long sdu, size %x \n", length);
#endif

		} else {	//if (((SCH_SUBHEADER_SHORT *)mac_header_ptr)->F == 0) {
		    length = ((SCH_SUBHEADER_SHORT *) mac_header_ptr)->L;
		    mac_header_ptr += 2;
		}
	    }

#ifdef DEBUG_HEADER_PARSING
	    LOG_D(MAC, "[UE] sdu %d lcid %d length %d (offset now %ld)\n",
		  num_sdus, lcid, length, mac_header_ptr - mac_header);
#endif
	    rx_lcids[num_sdus] = lcid;
	    rx_lengths[num_sdus] = length;
	    num_sdus++;
	} else {		// This is a control element subheader
	    if (lcid == SHORT_PADDING) {
		num_padding++;
		mac_header_ptr++;
	    } else {
		rx_ces[num_ces] = lcid;
		num_ces++;
		mac_header_ptr++;

		if (lcid == TIMING_ADV_CMD) {
		    ce_len++;
		} else if (lcid == UE_CONT_RES) {

		    // FNA: check MAC Header is one of thoses defined in Annex B of 36.321
		    // Check there is only 1 Contention Resolution
		    if (num_cont_res) {
			LOG_W(MAC,
			      "[UE] Msg4 Wrong received format: More than 1 Contention Resolution\n");
			// exit parsing
			return NULL;

		    }
		    // UE_CONT_RES shall never be the last subheader unless this is the only MAC subheader
		    if ((not_done == 0)
			&& ((num_sdus) || (num_ces > 1) || (num_padding))) {
			LOG_W(MAC,
			      "[UE] Msg4 Wrong received format: Contention Resolution after num_ces=%d num_sdus=%d num_padding=%d\n",
			      num_ces, num_sdus, num_padding);
			// exit parsing
			return NULL;
		    }
		    num_cont_res++;
		    ce_len += 6;
		}
	    }

#ifdef DEBUG_HEADER_PARSING
	    LOG_D(MAC, "[UE] ce %d lcid %d (offset now %ld)\n", num_ces,
		  lcid, mac_header_ptr - mac_header);
#endif
	}
    }

    *num_ce = num_ces;
    *num_sdu = num_sdus;

    return (mac_header_ptr);
}

2321
unsigned char
2322 2323
nr_generate_ulsch_pdu(uint8_t *mac_pdu,
					  uint8_t *sdus_payload,
2324 2325 2326 2327
                      uint8_t num_sdus,
                      uint16_t *sdu_lengths,
                      uint8_t *sdu_lcids,
                      uint16_t *crnti,
2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354
                      uint16_t buflen) {

	NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu;
	unsigned char * ulsch_buffer_ptr = sdus_payload;
	uint8_t last_size=0;
	uint16_t sdu_length_total;
	int i;
	int offset=0;

	  // 2) Generation of ULSCH MAC SDU subheaders
	  for (i = 0; i < num_sdus; i++) {
	    LOG_D(MAC, "[gNB] Generate ULSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);

	    if (sdu_lengths[i] < 128) {
	      ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
	      ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
	      ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i];
	      ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i];
	      last_size = 2;
	    } else {
	      ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0;
	      ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1;
	      ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i];
	      ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f;
	      ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff;
	      last_size = 3;
	    }
2355

2356
	    mac_pdu_ptr += last_size;
2357

2358 2359 2360 2361 2362
	    // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
	    memcpy((void *) mac_pdu_ptr, (void *) ulsch_buffer_ptr, sdu_lengths[i]);
	    ulsch_buffer_ptr+= sdu_lengths[i];
	    mac_pdu_ptr += sdu_lengths[i];
	  }
2363

2364 2365 2366 2367 2368 2369
	  // 4) Compute final offset for padding
	  uint16_t padding_bytes = buflen - sdu_length_total;
	  if (padding_bytes > 0) {
	    ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
	    ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING;
	    mac_pdu_ptr++;
2370

2371 2372 2373
	  } else {
	    // no MAC subPDU with padding
	  }
2374

2375
	  offset = ((unsigned char *) mac_pdu_ptr - mac_pdu);
2376 2377


2378
  return offset;
2379 2380 2381 2382
}


/* LTE based function to be substituted once NR version is ready */
2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
//------------------------------------------------------------------------------
void
nr_ue_send_sdu(module_id_t module_idP,
	    uint8_t CC_id,
	    frame_t frameP,
	    sub_frame_t subframeP,
	    uint8_t * sdu, uint16_t sdu_len, uint8_t eNB_index)
//------------------------------------------------------------------------------
{

    unsigned char rx_ces[MAX_NUM_CE], num_ce, num_sdu, i, *payload_ptr;
    unsigned char rx_lcids[NB_RB_MAX];
    unsigned short rx_lengths[NB_RB_MAX];


  //LOG_D(MAC,"sdu: %x.%x.%x\n",sdu[0],sdu[1],sdu[2]);


    payload_ptr =
2402
	nr_parse_header(sdu, &num_ce, &num_sdu, rx_ces, rx_lcids, rx_lengths,
2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446
		     sdu_len);

#ifdef DEBUG_HEADER_PARSING
    LOG_D(MAC,
	  "[UE %d] ue_send_sdu : Frame %d eNB_index %d : num_ce %d num_sdu %d\n",
	  module_idP, frameP, eNB_index, num_ce, num_sdu);
#endif

#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
    LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP);

    for (i = 0; i < 32; i++) {
	LOG_T(MAC, "%x.", sdu[i]);
    }

    LOG_T(MAC, "\n");
#endif

    if (payload_ptr != NULL) {

	for (i = 0; i < num_ce; i++) {
	    //    printf("ce %d : %d\n",i,rx_ces[i]);
	    switch (rx_ces[i]) {
	    case UE_CONT_RES:

		break;

	    case TIMING_ADV_CMD:

        break;

	    case DRX_CMD:

		break;
	    }
	}

	for (i = 0; i < num_sdu; i++) {
#ifdef DEBUG_HEADER_PARSING
	    LOG_I(MAC, "[UE] SDU %d : LCID %d, length %d\n", i,
		  rx_lcids[i], rx_lengths[i]);
#endif
	    if ((rx_lcids[i] < NB_RB_MAX) && (rx_lcids[i] > DCCH1)) {

2447
		LOG_D(MAC,
2448 2449 2450 2451 2452
		      "[UE %d] Frame %d : DLSCH -> DL-DTCH%d (eNB %d, %d bytes)\n",
		      module_idP, frameP, rx_lcids[i], eNB_index,
		      rx_lengths[i]);

#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
2453
		LOG_I(MAC, "Printing MAC PDU contents at slot: %d \n", subframeP);
2454
		int j;
2455
		for (j = 0; j < 20; j++) //rx_lengths[i]
2456 2457
			LOG_I(MAC, "%x.", (unsigned char) payload_ptr[j]);
		LOG_I(MAC, "\n");
2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477
#endif
		mac_rlc_data_ind(module_idP,
				 4660, //UE_mac_inst[module_idP].crnti //hardcode value corresponding to the one from the eNB
				 eNB_index,
				 frameP,
				 ENB_FLAG_NO,
				 MBMS_FLAG_NO,
				 rx_lcids[i],
				 (char *) payload_ptr, rx_lengths[i], 1,
				 NULL);
	    } else {
		LOG_E(MAC, "[UE %d] Frame %d : unknown LCID %d (eNB %d)\n",
		      module_idP, frameP, rx_lcids[i], eNB_index);
	    }
	    payload_ptr += rx_lengths[i];
	}
    }				// end if (payload_ptr != NULL)

}

2478

2479 2480 2481
uint8_t
nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
           sub_frame_t subframe, uint8_t eNB_index,
2482
           uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode) {
2483 2484
  uint8_t total_rlc_pdu_header_len = 0, rlc_pdu_header_len_last = 0;
  uint16_t buflen_remain = 0;
2485
  uint8_t lcid = 0;
2486 2487 2488
  uint16_t sdu_lengths[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
  uint8_t sdu_lcids[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
  uint8_t payload_offset = 0, num_sdus = 0;
2489
  uint8_t ulsch_sdus[MAX_ULSCH_PAYLOAD_BYTES];
2490
  uint16_t sdu_length_total = 0;
2491
  unsigned short post_padding = 0, padding_len = 0;
2492
  int j;      // used for padding
2493

2494 2495 2496 2497 2498 2499 2500
  rlc_buffer_occupancy_t lcid_buffer_occupancy_old =
    0, lcid_buffer_occupancy_new = 0;
  LOG_D(MAC,
        "[UE %d] MAC PROCESS UL TRANSPORT BLOCK at frame%d subframe %d TBS=%d\n",
        module_idP, frameP, subframe, buflen);
  AssertFatal(CC_id == 0,
              "Transmission on secondary CCs is not supported yet\n");
2501 2502 2503
#if UE_TIMING_TRACE
  start_meas(&UE_mac_inst[module_idP].tx_ulsch_sdu);
#endif
2504

2505
  NR_UE_MAC_INST_t *nr_ue_mac_inst = get_mac_inst(0);
2506 2507 2508

  // Check for DCCH first
  // TO DO: Multiplex in the order defined by the logical channel prioritization
2509 2510 2511 2512 2513 2514 2515 2516 2517
  for (lcid = DCCH;
       lcid < MAX_NUM_LCID; lcid++) {

      lcid_buffer_occupancy_old =
    		  //TODO: Replace static value with CRNTI
        mac_rlc_get_buffer_occupancy_ind(module_idP,
        								 0x1234, eNB_index, frameP, //nr_ue_mac_inst->crnti
                                         subframe, ENB_FLAG_NO,
                                         lcid);
2518 2519
      lcid_buffer_occupancy_new = lcid_buffer_occupancy_old;

2520
      if(lcid_buffer_occupancy_new){
2521 2522

        buflen_remain =
2523 2524
          buflen - (total_rlc_pdu_header_len + sdu_length_total + MIN_MAC_HDR_RLC_SIZE);
        LOG_D(MAC,
2525
              "[UE %d] Frame %d : UL-DXCH -> ULSCH, RLC %d has %d bytes to "
2526
              "send (Transport Block size %d SDU Length Total %d , mac header len %d )\n", //BSR byte before Tx=%d
2527
              module_idP, frameP, lcid, lcid_buffer_occupancy_new,
2528 2529
              buflen, sdu_length_total,
              total_rlc_pdu_header_len); // ,nr_ue_mac_inst->scheduling_info.BSR_bytes[nr_ue_mac_inst->scheduling_info.LCGID[lcid]]
2530

2531
        //TODO: Replace static value with CRNTI
2532
        sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP,
2533
        						0x1234, eNB_index, //nr_ue_mac_inst->crnti
2534 2535 2536 2537 2538
                                frameP,
                                ENB_FLAG_NO,
                                MBMS_FLAG_NO,
                                lcid,
                                buflen_remain,
2539
                                (char *)&ulsch_sdus[sdu_length_total],0,
2540 2541 2542 2543 2544 2545 2546 2547 2548
                                0
                                                );
        AssertFatal(buflen_remain >= sdu_lengths[num_sdus],
                    "LCID=%d RLC has segmented %d bytes but MAC has max=%d\n",
                    lcid, sdu_lengths[num_sdus], buflen_remain);

        if (sdu_lengths[num_sdus]) {
          sdu_length_total += sdu_lengths[num_sdus];
          sdu_lcids[num_sdus] = lcid;
2549 2550 2551
          //LOG_I(MAC,
          //      "[UE %d] TX Multiplex RLC PDU TX Got %d bytes for LcId%d\n",
          //      module_idP, sdu_lengths[num_sdus], lcid);
2552 2553 2554 2555 2556 2557 2558 2559

          //Update number of SDU
          num_sdus++;
          //Update total MAC Header size for RLC PDUs and save last one
          total_rlc_pdu_header_len += rlc_pdu_header_len_last;
        }

        /* Get updated BO after multiplexing this PDU */
2560 2561 2562 2563 2564 2565 2566 2567
        //TODO: Replace static value with CRNTI

        /*lcid_buffer_occupancy_new =
          mac_rlc_get_buffer_occupancy_ind(module_idP,
                                           0x1234, //nr_ue_mac_inst->crnti
                                           eNB_index, frameP,
                                           subframe, ENB_FLAG_NO,
                                           lcid);
2568
        is_lcid_processed = (is_lcid_processed)
2569
                            || (lcid_buffer_occupancy_new <= 0);*/
2570 2571
  }

2572
}
2573

2574 2575 2576 2577
  // Generate ULSCH PDU
  if (num_sdus>0) {
  payload_offset = nr_generate_ulsch_pdu(ulsch_buffer,  // mac header
		  	  	  	  	  	  	  	  	 ulsch_sdus,
2578 2579 2580 2581
                                         num_sdus,  // num sdus
                                         sdu_lengths, // sdu length
                                         sdu_lcids, // sdu lcid
                                         NULL,  // crnti
2582 2583 2584 2585
                                         buflen);  // long_bsr
  }
  else
	  return 0;
2586
  LOG_D(MAC,
2587
        "[UE %d] Generate header :bufflen %d  sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,  total_rlc_pdu_header_len %d, post_padding %d, remainder %d \n",
2588 2589
        module_idP, buflen, sdu_length_total, num_sdus, sdu_lengths[0],
        sdu_lcids[0], payload_offset, total_rlc_pdu_header_len,
2590
        post_padding, buflen - sdu_length_total - payload_offset);
2591

2592 2593 2594 2595
  // Padding: fill remainder of ULSCH with 0
  if (buflen - payload_offset > 0){
	  for (int j = 0; j < (buflen - payload_offset); j++)
		  ulsch_buffer[payload_offset + j] = 0;
2596 2597
  }

2598
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
2599 2600
  LOG_I(MAC, "Printing UL MAC payload without the header UE side, payload_offset: %d \n", payload_offset);
  for (int i = 0; i < sdu_length_total ; i++) {
2601 2602 2603 2604 2605 2606 2607
	  //harq_process_ul_ue->a[i] = (unsigned char) rand();
	  //printf("a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]);
	  printf("%02x ",(unsigned char)ulsch_buffer[i]);
  }
  printf("\n");
#endif

2608 2609
  return 1;
}