Commit 0a2e0332 authored by Francesco Mani's avatar Francesco Mani

max ack bits in mac_proto.h

parent 57a612c5
dev 1 128-ues 256_QAM_demod Fix_SA_SIB1 NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_PDCP NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_SA NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_multiplexing_HARQ_CSI_PUCCH NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_ue_dlsch_dmrs_cdm PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed UE_DL_DCI_hotfix add-dmrs-test bch-fixes-bitmap benetel_5g_prach_fix benetel_config_file_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes benetel_phase_rotation benetel_phase_rotation_old bsr-fix bugfix-free-ra-process bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-new-docker-pipeline ci-rd-july-improvements ci-reduce-nb-vms ci-test ci-ul-iperf-from-trf-container ci_benetel_test ci_phytest ci_quectel_support ci_test_nsa_fix_quectel_nic ci_test_ra_fr2 ci_vm_resource_fix clean-5G-scope-round2 cleanup_softmodem_main constant_power detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-v3 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts 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...@@ -1350,7 +1350,7 @@ void nr_update_pucch_scheduling(int Mod_idP, ...@@ -1350,7 +1350,7 @@ void nr_update_pucch_scheduling(int Mod_idP,
} }
else { // to be tested else { // to be tested
curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
if (curr_pucch->dai_c<11) { // we are scheduling at most 11 harq-ack in the same pucch if (curr_pucch->dai_c<MAX_ACK_BITS) { // we are scheduling at most MAX_UCI_BITS harq-ack in the same pucch
while (i<8 && found == 0) { // look if timing indicator is among allowed values for current pucch while (i<8 && found == 0) { // look if timing indicator is among allowed values for current pucch
if (pdsch_to_harq_feedback[i]==(curr_pucch->ul_slot % slots_per_tdd)-(slotP % slots_per_tdd)) if (pdsch_to_harq_feedback[i]==(curr_pucch->ul_slot % slots_per_tdd)-(slotP % slots_per_tdd))
found = 1; found = 1;
...@@ -1362,7 +1362,7 @@ void nr_update_pucch_scheduling(int Mod_idP, ...@@ -1362,7 +1362,7 @@ void nr_update_pucch_scheduling(int Mod_idP,
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
} }
} }
if (curr_pucch->dai_c==11 || found == 0) { // if current pucch is full or no timing indicator allowed if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed
// look for pucch occasions in other UL of mixed slots // look for pucch occasions in other UL of mixed slots
for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; k<slots_per_tdd; k++) { // for each possible UL or mixed slot for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; k<slots_per_tdd; k++) { // for each possible UL or mixed slot
if (k!=(curr_pucch->ul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked) if (k!=(curr_pucch->ul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked)
...@@ -1396,7 +1396,7 @@ void nr_update_pucch_scheduling(int Mod_idP, ...@@ -1396,7 +1396,7 @@ void nr_update_pucch_scheduling(int Mod_idP,
curr_pucch->next_sched_pucch = sched_pucch; curr_pucch->next_sched_pucch = sched_pucch;
} }
else { else {
if (curr_pucch->dai_c==11) if (curr_pucch->dai_c==MAX_ACK_BITS)
found = 0; // if pucch at index k is already full we have to find a new one in a following occasion found = 0; // if pucch at index k is already full we have to find a new one in a following occasion
else { // scheduling this harq-ack in current pucch else { // scheduling this harq-ack in current pucch
sched_pucch = curr_pucch; sched_pucch = curr_pucch;
......
...@@ -34,6 +34,8 @@ ...@@ -34,6 +34,8 @@
#include "nr_mac_gNB.h" #include "nr_mac_gNB.h"
#include "PHY/defs_gNB.h" #include "PHY/defs_gNB.h"
#define MAX_ACK_BITS 2 //only format 0 is available for now
void set_cset_offset(uint16_t); void set_cset_offset(uint16_t);
void mac_top_init_gNB(void); void mac_top_init_gNB(void);
......
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