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ZhouShuya
OpenXG-RAN
Commits
5a9329d1
Commit
5a9329d1
authored
Feb 26, 2020
by
Francesco Mani
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bugfix in filling dci for rar
parent
63cf2ffa
Changes
2
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Showing
2 changed files
with
9 additions
and
10 deletions
+9
-10
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+3
-4
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+6
-6
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
5a9329d1
...
@@ -584,7 +584,7 @@ void nr_generate_Msg2(module_id_t module_idP,
...
@@ -584,7 +584,7 @@ void nr_generate_Msg2(module_id_t module_idP,
dci_pdu_rel15
[
0
].
time_domain_assignment
=
time_domain_assignment
;
dci_pdu_rel15
[
0
].
time_domain_assignment
=
time_domain_assignment
;
dci_pdu_rel15
[
0
].
vrb_to_prb_mapping
=
0
;
dci_pdu_rel15
[
0
].
vrb_to_prb_mapping
=
0
;
dci_pdu_rel15
[
0
].
mcs
=
pdsch_pdu_rel15
->
mcsIndex
[
0
];
dci_pdu_rel15
[
0
].
mcs
=
pdsch_pdu_rel15
->
mcsIndex
[
0
];
dci_pdu_rel15
[
0
].
tb_scaling
=
1
;
dci_pdu_rel15
[
0
].
tb_scaling
=
0
;
LOG_D
(
MAC
,
"[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d
\n
"
,
LOG_D
(
MAC
,
"[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d
\n
"
,
dci_pdu_rel15
[
0
].
frequency_domain_assignment
,
dci_pdu_rel15
[
0
].
frequency_domain_assignment
,
...
@@ -598,7 +598,7 @@ void nr_generate_Msg2(module_id_t module_idP,
...
@@ -598,7 +598,7 @@ void nr_generate_Msg2(module_id_t module_idP,
nr_configure_pdcch
(
pdcch_pdu_rel15
,
0
,
ss
,
scc
,
bwp
);
nr_configure_pdcch
(
pdcch_pdu_rel15
,
0
,
ss
,
scc
,
bwp
);
LOG_
D
(
MAC
,
"Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d
\n
"
,
frameP
,
slotP
,
RA_rnti
,
CCEIndex
);
LOG_
I
(
MAC
,
"Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d
\n
"
,
frameP
,
slotP
,
RA_rnti
,
CCEIndex
);
dci_pdu
->
RNTI
[
numDlDci
]
=
RA_rnti
;
dci_pdu
->
RNTI
[
numDlDci
]
=
RA_rnti
;
dci_pdu
->
ScramblingId
[
numDlDci
]
=
*
scc
->
physCellId
;
dci_pdu
->
ScramblingId
[
numDlDci
]
=
*
scc
->
physCellId
;
...
@@ -608,7 +608,6 @@ void nr_generate_Msg2(module_id_t module_idP,
...
@@ -608,7 +608,6 @@ void nr_generate_Msg2(module_id_t module_idP,
dci_pdu
->
CceIndex
[
numDlDci
]
=
CCEIndex
;
dci_pdu
->
CceIndex
[
numDlDci
]
=
CCEIndex
;
dci_pdu
->
beta_PDCCH_1_0
[
numDlDci
]
=
0
;
dci_pdu
->
beta_PDCCH_1_0
[
numDlDci
]
=
0
;
dci_pdu
->
powerControlOffsetSS
[
numDlDci
]
=
1
;
dci_pdu
->
powerControlOffsetSS
[
numDlDci
]
=
1
;
dci_formats
[
0
]
=
NR_DL_DCI_FORMAT_1_0
;
dci_formats
[
0
]
=
NR_DL_DCI_FORMAT_1_0
;
rnti_types
[
0
]
=
NR_RNTI_RA
;
rnti_types
[
0
]
=
NR_RNTI_RA
;
...
@@ -620,9 +619,9 @@ void nr_generate_Msg2(module_id_t module_idP,
...
@@ -620,9 +619,9 @@ void nr_generate_Msg2(module_id_t module_idP,
pdcch_pdu_rel15
->
StartSymbolIndex
,
pdcch_pdu_rel15
->
StartSymbolIndex
,
pdcch_pdu_rel15
->
DurationSymbols
);
pdcch_pdu_rel15
->
DurationSymbols
);
pdcch_pdu_rel15
->
numDlDci
++
;
dci_pdu
->
PayloadSizeBits
[
0
]
=
nr_dci_size
(
dci_formats
[
0
],
rnti_types
[
0
],
dci10_bw
);
dci_pdu
->
PayloadSizeBits
[
0
]
=
nr_dci_size
(
dci_formats
[
0
],
rnti_types
[
0
],
dci10_bw
);
fill_dci_pdu_rel15
(
pdcch_pdu_rel15
,
&
dci_pdu_rel15
[
0
],
dci_formats
,
rnti_types
,
dci10_bw
);
fill_dci_pdu_rel15
(
pdcch_pdu_rel15
,
&
dci_pdu_rel15
[
0
],
dci_formats
,
rnti_types
,
dci10_bw
);
pdcch_pdu_rel15
->
numDlDci
++
;
dl_req
->
nPDUs
+=
2
;
dl_req
->
nPDUs
+=
2
;
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
5a9329d1
...
@@ -558,34 +558,34 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
...
@@ -558,34 +558,34 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment
// Freq domain assignment
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
pos
=
fsize
;
pos
=
fsize
;
*
dci_pdu
|=
((
dci_pdu_rel15
->
frequency_domain_assignment
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_size
-
pos
));
*
dci_pdu
|=
((
(
uint64_t
)
dci_pdu_rel15
->
frequency_domain_assignment
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_size
-
pos
));
#ifdef DEBUG_FILL_DCI
#ifdef DEBUG_FILL_DCI
LOG_
D
(
MAC
,
"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
frequency_domain_assignment
,
fsize
,
N_RB
,
dci_size
-
pos
,
*
dci_pdu
);
LOG_
I
(
MAC
,
"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
frequency_domain_assignment
,
fsize
,
N_RB
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
#endif
// Time domain assignment
// Time domain assignment
pos
+=
4
;
pos
+=
4
;
*
dci_pdu
|=
(((
uint64_t
)
dci_pdu_rel15
->
time_domain_assignment
&
0xf
)
<<
(
dci_size
-
pos
));
*
dci_pdu
|=
(((
uint64_t
)
dci_pdu_rel15
->
time_domain_assignment
&
0xf
)
<<
(
dci_size
-
pos
));
#ifdef DEBUG_FILL_DCI
#ifdef DEBUG_FILL_DCI
LOG_
D
(
MAC
,
"time-domain assignment %d (4 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
time_domain_assignment
,
dci_size
-
pos
,
*
dci_pdu
);
LOG_
I
(
MAC
,
"time-domain assignment %d (4 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
time_domain_assignment
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
#endif
// VRB to PRB mapping
// VRB to PRB mapping
pos
++
;
pos
++
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
vrb_to_prb_mapping
&
0x1
)
<<
(
dci_size
-
pos
);
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
vrb_to_prb_mapping
&
0x1
)
<<
(
dci_size
-
pos
);
#ifdef DEBUG_FILL_DCI
#ifdef DEBUG_FILL_DCI
LOG_
D
(
MAC
,
"vrb to prb mapping %d (1 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
vrb_to_prb_mapping
,
dci_size
-
pos
,
*
dci_pdu
);
LOG_
I
(
MAC
,
"vrb to prb mapping %d (1 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
vrb_to_prb_mapping
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
#endif
// MCS
// MCS
pos
+=
5
;
pos
+=
5
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
mcs
&
0x1f
)
<<
(
dci_size
-
pos
);
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
mcs
&
0x1f
)
<<
(
dci_size
-
pos
);
#ifdef DEBUG_FILL_DCI
#ifdef DEBUG_FILL_DCI
LOG_
D
(
MAC
,
"mcs %d (5 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
mcs
,
dci_size
-
pos
,
*
dci_pdu
);
LOG_
I
(
MAC
,
"mcs %d (5 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
mcs
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
#endif
// TB scaling
// TB scaling
pos
+=
2
;
pos
+=
2
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
tb_scaling
&
0x3
)
<<
(
dci_size
-
pos
);
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
tb_scaling
&
0x3
)
<<
(
dci_size
-
pos
);
#ifdef DEBUG_FILL_DCI
#ifdef DEBUG_FILL_DCI
LOG_
D
(
MAC
,
"tb_scaling %d (2 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
tb_scaling
,
dci_size
-
pos
,
*
dci_pdu
);
LOG_
I
(
MAC
,
"tb_scaling %d (2 bits)=> %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
tb_scaling
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
#endif
break
;
break
;
...
...
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