Commit c3aa248f authored by Robert Schmidt's avatar Robert Schmidt

Fix Msg.2 TDA to be 1, revert DL TDA configs to two entries

parent 8613aeb9
......@@ -58,27 +58,14 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=2,L=3
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 261;
......
......@@ -879,7 +879,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
uint8_t time_domain_assignment = 3;
uint8_t time_domain_assignment = 1;
uint8_t mcsIndex = 0;
int rbStart = 0;
int rbSize = 8;
......
......@@ -817,7 +817,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
harq->is_waiting = true;
UE_info->mac_stats[UE_id].dlsch_rounds[harq->round]++;
LOG_D(MAC,
LOG_I(MAC,
"%4d.%2d RNTI %04x start %3d RBs %3d startSymbol %2d nb_symbol %2d MCS %2d TBS %4d HARQ PID %2d round %d NDI %d\n",
frame,
slot,
......
......@@ -1282,7 +1282,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
}
UE_info->mac_stats[UE_id].ulsch_current_bytes = sched_pusch->tb_size;
LOG_D(MAC,
LOG_I(MAC,
"%4d.%2d RNTI %04x UL sched %4d.%2d start %2d RBS %3d startSymbol %2d nb_symbol %2d MCS %2d TBS %4d HARQ PID %2d round %d NDI %d est %6d sched %6d est BSR %6d\n",
frame,
slot,
......
......@@ -58,27 +58,14 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=2,L=3
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 261;
......
......@@ -56,27 +56,13 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=4
initialDLBWPstartSymbolAndLength_3 = 57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
......@@ -56,27 +56,14 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=5
initialDLBWPstartSymbolAndLength_3 = 57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
......@@ -56,27 +56,14 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=5
initialDLBWPstartSymbolAndLength_3 = 57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
......@@ -56,27 +56,14 @@ gNBs =
initialDLBWPsearchSpaceZero = 0;
#pdsch-ConfigCommon
#pdschTimeDomainAllocationList (up to 16 entries)
initialDLBWPk0_0 = 0;
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
#this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
initialDLBWPmappingType_1 = 0;
#this is SS=2,L=12
initialDLBWPstartSymbolAndLength_1 = 53;
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
#this is SS=1,L=5
initialDLBWPstartSymbolAndLength_3 = 57;
initialDLBWPk0_0 = 0; #for DL slot
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13
initialDLBWPk0_3 = 0; #for mixed slot
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
......@@ -67,15 +67,7 @@ gNBs =
initialDLBWPk0_1 = 0; #for mixed slot
initialDLBWPmappingType_1 = 0;
initialDLBWPstartSymbolAndLength_1 = 53; #this is SS=2,L=12
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
initialDLBWPstartSymbolAndLength_2 = 54; #this is SS=1,L=12
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
initialDLBWPstartSymbolAndLength_1 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
......@@ -67,15 +67,7 @@ gNBs =
initialDLBWPk0_1 = 0; #for mixed slot
initialDLBWPmappingType_1 = 0;
initialDLBWPstartSymbolAndLength_1 = 53; #this is SS=2,L=12
initialDLBWPk0_2 = 0;
initialDLBWPmappingType_2 = 0;
initialDLBWPstartSymbolAndLength_2 = 54; #this is SS=1,L=12
initialDLBWPk0_3 = 0;
initialDLBWPmappingType_3 = 0;
initialDLBWPstartSymbolAndLength_3 = 57; #this is SS=1,L=5
initialDLBWPstartSymbolAndLength_1 = 57; #this is SS=1,L=5
#uplinkConfigCommon
#frequencyInfoUL
......
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