1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/LTE_TRANSPORT/dci.h
* \brief typedefs for LTE DCI structures from 36-212, V8.6 2009-03. Limited to 5 MHz formats for the moment.Current LTE compliance V8.6 2009-03.
* \author R. Knopp
* \date 2011
* \version 0.1
* \company Eurecom
* \email: knopp@eurecom.fr
* \note
* \warning
*/
#ifndef USER_MODE
#include "PHY/types.h"
#else
#include <stdint.h>
#endif
typedef enum DCI_format_NB
{
DCIFormatN0 = 0,
DCIFormatN1,
DCIFormatN1_RA,
DCIFormatN1_RAR,
DCIFormatN2_Ind,
DCIFormatN2_Pag,
}e_DCI_format_NB;
/// DCI Format Type 0 (180 kHz, 23 bits)
struct DCIFormatN0{
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type;
/// Subcarrier indication, 6 bits
uint8_t scind;
/// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign;
/// Modulation and Coding Scheme, 4 bits
uint8_t mcs;
/// New Data Indicator, 1 bits
uint8_t ndi;
/// Scheduling Delay, 2 bits
uint8_t Scheddly;
/// Repetition Number, 3 bits
uint8_t RepNum;
/// Redundancy version for HARQ (only use 0 and 2), 1 bits
uint8_t rv;
/// DCI subframe repetition Number, 2 bits
uint8_t DCIRep;
};
typedef struct DCIFormatN0 DCIFormatN0_t;
#define sizeof_DDCIFormatN0_t 23
/// DCI Format Type N1 for User data
struct DCIFormatN1{
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1,1bits
uint8_t type;
//NPDCCH order indicator (set to 0), 1 bits
uint8_t orderIndicator;
// Scheduling Delay,3 bits
uint8_t Scheddly;
// Resourse Assignment (RU Assignment),3 bits
uint8_t ResAssign;
// Modulation and Coding Scheme,4 bits
uint8_t mcs;
// Repetition Number,4 bits
uint8_t RepNum;
// New Data Indicator,1 bits
uint8_t ndi;
// HARQ-ACK resource,4 bits
uint8_t HARQackRes;
// DCI subframe repetition Number,2 bits
uint8_t DCIRep;
};
typedef struct DCIFormatN1 DCIFormatN1_t;
#define sizeof_DCIFormatN1_t 23
/// DCI Format Type N1 for initial RA
struct DCIFormatN1_RA{
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type;
//NPDCCH order indicator (set to 0),1 bits
uint8_t orderIndicator;
// Start number of NPRACH repetiiton, 2 bits
uint8_t Scheddly;
// Subcarrier indication of NPRACH, 6 bits
uint8_t scind;
// All the remainging bits, 13 bits
uint8_t remaingingBits;
};
typedef struct DCIFormatN1_RA DCIFormatN1_RA_t;
#define sizeof_DCIFormatN1_RA_t 23
/// DCI Format Type N1 for RAR
struct DCIFormatN1_RAR{
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type;
//NPDCCH order indicator (set to 0),1 bits
uint8_t orderIndicator;
// Scheduling Delay, 3 bits
uint8_t Scheddly;
// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign;
// Modulation and Coding Scheme, 4 bits
uint8_t mcs;
// Repetition Number, 4 bits
uint8_t RepNum;
// Reserved 5 bits
uint8_t Reserved;
// DCI subframe repetition Number, 2 bits
uint8_t DCIRep;
};
typedef struct DCIFormatN1_RAR DCIFormatN1_RAR_t;
#define sizeof_DCIFormatN1_RAR_t 23
// DCI Format Type N2 for direct indication, 15 bits
struct DCIFormatN2_Ind{
//Flag for paging(1)/direct indication(0), set to 0,1 bits
uint8_t type;
//Direct indication information, 8 bits
uint8_t directIndInf;
// Reserved information bits, 6 bits
uint8_t resInfoBits;
};
typedef struct DCIFormatN2_Ind DCIFormatN2_Ind_t;
#define sizeof_DCIFormatN2_Ind_t 15
// DCI Format Type N2 for Paging, 15 bits
struct DCIFormatN2_Pag{
//Flag for paging(1)/direct indication(0), set to 1,1 bits
uint8_t type;
// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign;
// Modulation and Coding Scheme, 4 bits
uint8_t mcs;
// Repetition Number, 4 bits
uint8_t RepNum;
// Reserved 3 bits
uint8_t DCIRep;
};
typedef struct DCIFormatN2_Pag DCIFormatN2_Pag_t;
#define sizeof_DCIFormatN2_Pag_t 15
typedef union DCI_CONTENT {
//
DCIFormatN0_t DCIN0;
//
DCIFormatN1_t DCIN1;
//
DCIFormatN1_RA_t DCIN1_RA;
//
DCIFormatN1_RAR_t DCIN1_RAR;
//
DCIFormatN2_Ind_t DCIN2_Ind;
//
DCIFormatN2_Pag_t DCIN2_Pag;
}DCI_CONTENT;