Commit c90c2bf3 authored by lfarizav's avatar lfarizav

enabling multiple RRUS

parent dff70f52
......@@ -38,7 +38,7 @@ void lte_adjust_synch(LTE_DL_FRAME_PARMS *frame_parms,
unsigned char clear,
short coef)
{
printf("lte_adjust_synch: eNB %d, UE %d\n",eNB_id,ue->Mod_id);
static int max_pos_fil = 0;
static int count_max_pos_ok = 0;
static int first_time = 1;
......
......@@ -475,7 +475,7 @@ int lte_sync_time(int **rxdata, ///rx data in time domain
}
}
*eNB_id = sync_source;
//*eNB_id = sync_source;
LOG_D(PHY,"[UE] lte_sync_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n",sync_source,peak_pos,peak_val,dB_fixed(peak_val)/2);
......@@ -635,7 +635,7 @@ int lte_sync_freq(int **rxdataF, ///rx data in frequency domain
*eNB_id = sync_source;
LOG_D(PHY,"[UE] lte_sync_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n",sync_source,peak_pos,peak_val,dB_fixed(peak_val)/2);
LOG_D(PHY,"[UE%d] lte_sync_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n",sync_source,peak_pos,peak_val,dB_fixed(peak_val)/2);
#ifdef DEBUG_PHY
......
......@@ -46,7 +46,7 @@ const uint16_t alaw2lin_if4p5[256] = {60032, 60288, 59520, 59776, 61056, 61312,
void send_IF4p5(PHY_VARS_eNB *eNB, int frame, int subframe, uint16_t packet_type, int k) {
LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
int32_t **txdataF = (eNB->CC_id==0) ? eNB->common_vars.txdataF[0] : PHY_vars_eNB_g[0][0]->common_vars.txdataF[0];
int32_t **txdataF = (eNB->CC_id==0) ? eNB->common_vars.txdataF[0] : PHY_vars_eNB_g[eNB->Mod_id][0]->common_vars.txdataF[0];
int32_t **rxdataF = eNB->common_vars.rxdataF[0];
int16_t **rxsigF = eNB->prach_vars.rxsigF;
void *tx_buffer = eNB->ifbuffer.tx[subframe&1];
......@@ -144,10 +144,10 @@ void send_IF4p5(PHY_VARS_eNB *eNB, int frame, int subframe, uint16_t packet_type
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_COMPR_IF, 1 );
LOG_D(PHY,"IF4p5_PULFFT: frame %d, subframe %d, symbol %d\n",frame,subframe,symbol_id);
for (element_id=0; element_id<db_halflength; element_id++) {
i = (uint16_t*) &rxdataF[0][blockoffsetF+element_id];
i = (uint16_t*) &rxdataF[eNB->CC_id][blockoffsetF+element_id];
data_block[element_id] = ((uint16_t) lin2alaw_if4p5[*i]) | ((uint16_t)(lin2alaw_if4p5[*(i+1)]<<8));
i = (uint16_t*) &rxdataF[0][slotoffsetF+element_id];
i = (uint16_t*) &rxdataF[eNB->CC_id][slotoffsetF+element_id];
data_block[element_id+db_halflength] = ((uint16_t) lin2alaw_if4p5[*i]) | ((uint16_t)(lin2alaw_if4p5[*(i+1)]<<8));
//if (element_id==0) LOG_I(PHY,"send_if4p5: symbol %d rxdata0 = (%d,%d)\n",symbol_id,*i,*(i+1));
......
This diff is collapsed.
......@@ -37,7 +37,7 @@ int slot_fep(PHY_VARS_UE *ue,
LTE_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
LTE_UE_COMMON *common_vars = &ue->common_vars;
uint8_t eNB_id = 0;//ue_common_vars->eNb_id;
uint8_t eNB_id = common_vars->eNb_id;
unsigned char aa;
unsigned char symbol = l+((7-frame_parms->Ncp)*(Ns&1)); ///symbol within sub-frame
unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples);
......@@ -253,7 +253,7 @@ int slot_fep_freq(PHY_VARS_UE *ue,
LTE_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
LTE_UE_COMMON *common_vars = &ue->common_vars;
uint8_t eNB_id = 0;//ue_common_vars->eNb_id;
uint8_t eNB_id = common_vars->eNb_id;
unsigned char aa;
unsigned char symbol = l+((7-frame_parms->Ncp)*(Ns&1)); ///symbol within sub-frame
//unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples);
......
......@@ -2982,6 +2982,7 @@ void ue_pbch_procedures(uint8_t eNB_id,PHY_VARS_UE *ue,UE_rxtx_proc_t *proc, uin
frame_tx += pbch_phase;
if (ue->mac_enabled==1) {
printf("[UE%d] if mac_enabled? then dl_phy_sync_success. UE_mode %s\n",ue->Mod_id,ue->UE_mode[eNB_id]==NOT_SYNCHED?"NOT_SYNCHED":ue->UE_mode[eNB_id]==NOT_SYNCHED?"SYNCHED":"OTHER CHOICE");
mac_xface->dl_phy_sync_success(ue->Mod_id,frame_rx,eNB_id,
ue->UE_mode[eNB_id]==NOT_SYNCHED ? 1 : 0);
}
......
......@@ -87,7 +87,7 @@
#endif
#include "SIMULATION/TOOLS/defs.h" // for taus
#include "PHY/extern.h"
#ifdef PHY_EMUL
extern EMULATION_VARS *Emul_vars;
......@@ -4317,6 +4317,8 @@ NAS_KENB_REFRESH_REQ,NAS_CELL_SELECTION_REQ,RRC_STATE_INACTIVE,RRC_STATE_IDLE,RR
break;
case RRC_MAC_BCCH_DATA_IND:
printf("rrc_ue_task:[UE %d] Received %s: frameP %d, eNB %d\n", ue_mod_id, msg_name,
RRC_MAC_BCCH_DATA_IND (msg_p).frame, RRC_MAC_BCCH_DATA_IND (msg_p).enb_index);
LOG_D(RRC, "[UE %d] Received %s: frameP %d, eNB %d\n", ue_mod_id, msg_name,
RRC_MAC_BCCH_DATA_IND (msg_p).frame, RRC_MAC_BCCH_DATA_IND (msg_p).enb_index);
......@@ -4441,7 +4443,8 @@ NAS_KENB_REFRESH_REQ,NAS_CELL_SELECTION_REQ,RRC_STATE_INACTIVE,RRC_STATE_IDLE,RR
if (rrc_get_state(ue_mod_id) == RRC_STATE_INACTIVE) {
// have a look at MAC/main.c void dl_phy_sync_success(...)
openair_rrc_ue_init(ue_mod_id,0);
printf("openair_rrc_ue_init: UE %d\n",ue_mod_id);
openair_rrc_ue_init(ue_mod_id,PHY_vars_UE_g[ue_mod_id][0]->common_vars.eNb_id);
}
/* Save cell selection criterion */
......
......@@ -149,18 +149,18 @@ eNBs =
NETWORK_INTERFACES :
{
ENB_INTERFACE_NAME_FOR_S1_MME = "lo";
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.170/24";
ENB_INTERFACE_NAME_FOR_S1U = "lo";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.170/24";
ENB_INTERFACE_NAME_FOR_S1_MME = "enx58ef68b419df";
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.14.170/24";
ENB_INTERFACE_NAME_FOR_S1U = "enx58ef68b419df";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.14.170/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152
};
rrh_gw_config = (
{
local_if_name = "lo";
remote_address = "192.168.12.171";
local_address = "192.168.12.170";
local_if_name = "enx58ef68b419df";
remote_address = "192.168.14.171";
local_address = "192.168.14.170";
local_port = 50000; #for raw option local port must be the same to remote
remote_port = 50000;
rrh_gw_active = "yes";
......
......@@ -312,9 +312,9 @@ static void *UE_thread_synch(void *arg) {
case pbch:
#if DISABLE_LOG_X
printf("[UE thread Synch] Running Initial Synch (mode %d)\n",UE->mode);
printf("[UE%d thread Synch] Running Initial Synch (mode %d)\n",UE->Mod_id,UE->mode);
#else
LOG_I(PHY, "[UE thread Synch] Running Initial Synch (mode %d)\n",UE->mode);
LOG_I(PHY, "[UE%d thread Synch] Running Initial Synch (mode %d)\n",UE->Mod_id,UE->mode);
#endif
if (initial_sync( UE, UE->mode ) == 0) {
......
......@@ -1456,7 +1456,7 @@ void init_openair1(void)
// change the nb_connected_eNB
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
for (eNB_id=0;eNB_id<enb_properties->number;eNB_id++) {
init_lte_vars (&frame_parms[CC_id],
oai_emulation.info.frame_type[CC_id],
oai_emulation.info.tdd_config[CC_id],
......@@ -1471,7 +1471,7 @@ void init_openair1(void)
enb_properties->properties[eNB_id]->nb_antennas_tx[CC_id],
nb_antennas_rx_ue,
oai_emulation.info.eMBMS_active_state);
for (eNB_id=0;eNB_id<enb_properties->number;eNB_id++) {
// This is for IF4p5 RRU, gets done by RRC configuration of eNB
PHY_vars_eNB_g[eNB_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = enb_properties->properties[eNB_id]->prach_config_index[CC_id];
PHY_vars_eNB_g[eNB_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = enb_properties->properties[eNB_id]->prach_freq_offset[CC_id];
......@@ -1571,28 +1571,30 @@ void init_openair1(void)
PHY_vars_UE_g[UE_id][CC_id]->rx_total_gain_dB=100;
// update UE_mode for each eNB_id not just 0
if (abstraction_flag == 0) {
if (phy_test==0) PHY_vars_UE_g[UE_id][CC_id]->UE_mode[0] = NOT_SYNCHED;
else PHY_vars_UE_g[UE_id][CC_id]->UE_mode[0] = PUSCH;
} else {
// 0 is the index of the connected eNB
PHY_vars_UE_g[UE_id][CC_id]->UE_mode[0] = PRACH;
for (eNB_id=0; eNB_id<NB_eNB_INST; eNB_id++){
if (abstraction_flag == 0) {
if (phy_test==0) PHY_vars_UE_g[UE_id][CC_id]->UE_mode[eNB_id] = NOT_SYNCHED;
else PHY_vars_UE_g[UE_id][CC_id]->UE_mode[eNB_id] = PUSCH;
} else {
// 0 is the index of the connected eNB
PHY_vars_UE_g[UE_id][CC_id]->UE_mode[eNB_id] = PRACH;
}
}
if (phy_test==1)
PHY_vars_UE_g[UE_id][CC_id]->mac_enabled=0;
else
PHY_vars_UE_g[UE_id][CC_id]->mac_enabled=1;
for (eNB_id=0; eNB_id<NB_eNB_INST; eNB_id++){
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[0][eNB_id]->crnti = 0x1235 + UE_id;
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[0][0]->crnti = 0x1235 + UE_id;
for (uint8_t i=0; i<RX_NB_TH_MAX; i++) {
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[i][eNB_id]->dciFormat = 0;
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[i][eNB_id]->agregationLevel = 0xFF;
}
PHY_vars_UE_g[UE_id][CC_id]->current_dlsch_cqi[eNB_id] = 10;
for (uint8_t i=0; i<RX_NB_TH_MAX; i++) {
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[i][0]->dciFormat = 0;
PHY_vars_UE_g[UE_id][CC_id]->pdcch_vars[i][0]->agregationLevel = 0xFF;
LOG_I(EMU, "UE %d mode is initialized to %d\n", UE_id, PHY_vars_UE_g[UE_id][CC_id]->UE_mode[eNB_id] );
}
PHY_vars_UE_g[UE_id][CC_id]->current_dlsch_cqi[0] = 10;
LOG_I(EMU, "UE %d mode is initialized to %d\n", UE_id, PHY_vars_UE_g[UE_id][CC_id]->UE_mode[0] );
#if ENABLE_RAL
PHY_vars_UE_g[UE_id][CC_id]->ral_thresholds_timed = hashtable_create (64, NULL, NULL);
......
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