changed threading (acqusition is slot based). removal of eNB_thread. timing all based on received timestamp.

bugfixing for UL. Remaining problems: CCE allocations in subframe 5 lead to occasional illegal DCI allocations (affects UL DCI which is missed by UE). waveform compliance with CQI in ULSCH.

added hotfix for DCCH bad size limitation (to be checked after merge with develop).  Changed UL idle scheduling to improve 5MHz performance, changed DCI aggregation for ue-specific DCIs (reduces contention with SI and RA in subframe 5 for 5 MHz). Added RRC timer for UE release which cleans L1.  Still issues in 10 MHz throughput with TCP. 5 MHz seems almost fine.

it was at the wrong place
it was also wrong (< instead of <=)

added Timing advance tracing to .vcd output. Increase maximum UL RB count to 45. Measured UL throughput @ 15 Mbit/s (40 PRBs).

changes in BSR handling in eNodeB. UL throughput on 5 MHz is 8 Mbit/s (mcs 19, 20 PRB). MCS 20 is not working for an unknown reason.

increase maximum users in eNodeB to 16

some changes in logging for XFORMS and UL scheduling (activation in all subframes and retransmissions only via PHICH)

handling of timing advance is improved. MAC retrieves timing advance from phy once prior to DL scheduling and clears the statistic in PHY. A timer for controlling the timing advance periodicity was introduced.

Limitation of non SI DLSCH allocations in subframe 0/5 to PRBS not around DC (avoid puncturing from PBCH). Placement of SI around DC instead of randomized allocations. Placement of RA allocations at PRB 0-3.  Tested DL throughput on 5 MHz to 16 Mbit/s in TM1.

Added DLSCH scheduling for subframes 0 and 5. Changes in MAC scheduling data structure to keep track of VRB allocations from SI,RA when scheduling regular DLSCH

CCE Allocation in MAC, rebase from develop. Frame number limitation to 1024 for non-real time targets (caused bad bug in oaisim).