Commit 060281ec authored by Rakesh's avatar Rakesh

setting tdd single port flag

parent 38ffe291
......@@ -628,6 +628,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) {
unsigned int rxs, siglen;
int i;
uint32_t samples_per_slot = fp->get_samples_per_slot(*slot,fp);
int slot_type = nr_slot_select(cfg,*frame,*slot%fp->slots_per_frame);
openair0_timestamp ts;
AssertFatal(*slot<fp->slots_per_frame && *slot>=0, "slot %d is illegal (%d)\n",*slot,fp->slots_per_frame);
......@@ -647,7 +648,6 @@ void rx_rf(RU_t *ru,int *frame,int *slot) {
proc->timestamp_rx += fp->get_samples_per_slot(*slot%fp->slots_per_frame,fp);
}
int slot_type = nr_slot_select(cfg,*frame,*slot%fp->slots_per_frame);
if (slot_type == NR_UPLINK_SLOT || slot_type == NR_MIXED_SLOT || IS_SOFTMODEM_RFSIM) {
......@@ -767,13 +767,11 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
// the beam index is written in bits 8-10 of the flags
// bit 11 enables the gpio programming
int beam=0;
if (slot==0) beam = 11; //3 for boresight & 8 to enable
/*
//if (slot==0) beam = 11; //3 for boresight & 8 to enable
if (slot==0 || slot==40) beam=0&8;
if (slot==10 || slot==50) beam=1&8;
if (slot==20 || slot==60) beam=2&8;
if (slot==30 || slot==70) beam=3&8;
*/
flags |= beam<<8;
}
......
......@@ -647,7 +647,6 @@ void rx_rf(RU_t *ru,
openair0_timestamp ts=0,old_ts=0;
lte_subframe_t SF_type = subframe_select(fp,*subframe%10);
lte_subframe_t SubFrame_type;
lte_subframe_t prevSF_type = subframe_select(fp,(*subframe+9)%10);
for (i=0; i<ru->nb_rx; i++)
rxp[i] = (void *)&ru->common.rxdata[i][*subframe*fp->samples_per_tti];
......@@ -900,7 +899,7 @@ void rx_rf(RU_t *ru,
}
//printf("timestamp_rx %lu, frame %d(%d), subframe %d(%d),ts %lu \n",proc->timestamp_rx,proc->frame_rx,frame,proc->tti_rx,subframe,ts);
//printf("timestamp_rx %lu, frame %d(%d), subframe %d(%d),ts %lu,diff %lu \n",proc->timestamp_rx,proc->frame_rx,frame,proc->tti_rx,subframe,ts,proc->timestamp_rx - old_ts);
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TS, proc->timestamp_rx&0xffffffff );
}
}
......@@ -1531,9 +1530,10 @@ void fill_rf_config(RU_t *ru,
cfg->rx_bw = 1.5e6;
} else AssertFatal(1==0,"Unknown N_RB_DL %d\n",fp->N_RB_DL);
if (fp->frame_type==TDD)
if (fp->frame_type==TDD) {
cfg->duplex_mode = duplex_mode_TDD;
else //FDD
cfg->use_single_antenna_port_for_tdd=1;
} else //FDD
cfg->duplex_mode = duplex_mode_FDD;
cfg->Mod_id = 0;
......
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