Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
O
OpenXG-RAN
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
canghaiwuhen
OpenXG-RAN
Commits
b4d273d6
Commit
b4d273d6
authored
Apr 01, 2020
by
Sakthivel Velumani
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added remaining fields in 1_1 DCI pdu fill
parent
bb3883bf
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
50 additions
and
2 deletions
+50
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+50
-2
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
b4d273d6
...
...
@@ -544,7 +544,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
}
}
// TODO: Move the following
2
functions somewhere that UE can also use
// TODO: Move the following
3
functions somewhere that UE can also use
// Table 5.1.2.2.1-1 38.214
uint8_t
getRBGSize
(
uint16_t
bwp_size
,
long
rbg_size_config
)
{
...
...
@@ -563,6 +563,16 @@ uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
return
(
uint8_t
)
ceil
((
bwp_size
+
(
bwp_start
%
rbg_size
))
/
rbg_size
);
}
uint8_t
getAntPortBitWidth
(
NR_SetupRelease_DMRS_DownlinkConfig_t
*
typeA
,
NR_SetupRelease_DMRS_DownlinkConfig_t
*
typeB
)
{
uint8_t
nbitsA
,
nbitsB
,
nbits
=
0
;
if
(
typeA
!=
NULL
)
nbitsA
=
(
typeA
->
choise
.
setup
->
maxLength
[
0
]
==
0
)
?
4
:
5
;
if
(
typeB
!=
NULL
)
nbitsB
=
(
typeB
->
choise
.
setup
->
maxLength
[
0
]
==
0
)
?
5
:
6
;
if
((
typeA
!=
NULL
)
&&
(
typeB
!=
NULL
))
nbits
=
(
nbitsA
>
nbitsB
)
?
nbitsA
:
nbitsB
;
return
nbits
;
}
void
fill_dci_pdu_rel15
(
NR_CellGroupConfig_t
*
secondaryCellGroup
,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t
*
pdsch_pdu_rel15
,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu_rel15
,
...
...
@@ -1003,7 +1013,45 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
pos
+=
nbits
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
&
((
1
<<
nbits
)
-
1
))
<<
(
dci_size
-
pos
);
// Antenna ports
NR_SetupRelease_DMRS_DownlinkConfig_t
*
typeA
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
initialDownlinkBWP
->
pdsch_Config
->
choice
.
setup
->
dmrs_DownlinkForPDSCH_MappingTypeA
;
NR_SetupRelease_DMRS_DownlinkConfig_t
*
typeB
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
initialDownlinkBWP
->
pdsch_Config
->
choice
.
setup
->
dmrs_DownlinkForPDSCH_MappingTypeB
;
nbits
=
getAntPortBitWidth
(
typeA
,
typeB
);
pos
+=
nbits
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
antenna_ports
&
((
1
<<
nbits
)
-
1
))
<<
(
dci_size
-
pos
);
// TCI
long
*
isTciEnable
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
downlinkBWP_ToAddModList
->
list
.
array
[
0
]
->
bwp_Dedicated
->
pdcch_Config
->
choice
.
setup
->
controlResourceSetToAddModList
->
list
.
array
[
0
]
->
tci_PresentInDCI
;
if
(
isTciEnable
!=
NULL
)
{
pos
+=
3
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
transmission_configuration_indication
&
0x7
)
<<
(
dci_size
-
pos
);
}
// SRS request
if
(
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
crossCarrierSchedulingConfig
==
NULL
)
nbits
=
2
;
else
nbits
=
3
;
pos
+=
nbits
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
srs_request
&
((
1
<<
nbits
)
-
1
))
<<
(
dci_size
-
pos
);
// CBG transmission information
uint8_t
maxCBGperTB
=
(
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
initialDownlinkBWP
->
pdsch_ServingCellConfig
->
choise
.
setup
->
codeBlockGroupTransmission
->
choise
.
setup
->
maxCodeBlockGroupsPerTransportBlock
+
1
)
*
2
;
long
*
maxCWperDCI_rrc
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
initialDownlinkBWP
->
pdsch_Config
->
choice
.
setup
->
maxNrofCodeWordsScheduledByDCI
;
uint8_t
maxCWperDCI
=
(
maxCWperDCI_rrc
==
NULL
)
?
1
:
*
maxCWperDCI_rrc
;
nbits
=
maxCBGperTB
*
maxCWperDCI
;
pos
+=
nbits
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
cbgti
&
((
1
<<
nbits
)
-
1
))
<<
(
dci_size
-
pos
);
// CBG flushing out information
if
(
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
initialDownlinkBWP
->
pdsch_ServingCellConfig
->
choise
.
setup
->
codeBlockGroupTransmission
->
choise
.
setup
->
codeBlockGroupFlushIndicator
)
{
pos
+=
1
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
cbgfi
&
0x1
)
<<
(
dci_size
-
pos
);
}
// DMRS sequence init
pos
+=
1
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
dmrs_sequence_initialization
&
0x1
)
<<
(
dci_size
-
pos
);
}
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment