Commit dfd943aa authored by Robert Schmidt's avatar Robert Schmidt

Enable DL slots in both TDD periods

But we cannot really do it, because the OAI-UE does not seem to support
it
parent da2883e1
...@@ -359,8 +359,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -359,8 +359,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing); nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
} }
const uint64_t dlsch_in_slot_bitmap = (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4); #define BIT(x) (1 << (x))
const uint64_t ulsch_in_slot_bitmap = (1 << 8); const uint64_t dlsch_in_slot_bitmap = BIT(1) | BIT(2) | BIT(3) | BIT(4);
const uint64_t ulsch_in_slot_bitmap = BIT(8);
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1 memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
...@@ -420,7 +421,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -420,7 +421,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} }
// This schedules the DCI for Downlink and PDSCH // This schedules the DCI for Downlink and PDSCH
if (is_xlsch_in_slot(dlsch_in_slot_bitmap, slot) && slot < 10) if (is_xlsch_in_slot(dlsch_in_slot_bitmap, slot))
nr_schedule_ue_spec(module_idP, frame, slot); nr_schedule_ue_spec(module_idP, frame, slot);
......
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