nr_dci.c 12.8 KB
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/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
 * the OAI Public License, Version 1.1  (the "License"); you may not use this file
 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */

/*! \file PHY/NR_TRANSPORT/nr_dci.c
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* \brief Implements DCI encoding and PDCCH TX procedures (38.212/38.213/38.214). V15.4.0 2019-01.
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* \author Guy De Souza
* \date 2018
* \version 0.1
* \company Eurecom
* \email: desouza@eurecom.fr
* \note
* \warning
*/

#include "nr_dci.h"
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#include "nr_dlsch.h"
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#include "nr_sch_dmrs.h"
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#include "PHY/MODULATION/nr_modulation.h"
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//#define DEBUG_PDCCH_DMRS
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//#define DEBUG_DCI
//#define DEBUG_CHANNEL_CODING
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uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format,
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                         nfapi_nr_rnti_type_e rnti_type,
                         uint16_t N_RB,
                         nfapi_nr_config_request_t *config) {
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  uint16_t size = 0;
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  switch(format) {
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    /*Only sizes for 0_0 and 1_0 are correct at the moment*/
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    case NFAPI_NR_UL_DCI_FORMAT_0_0:
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      /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
      size += 20;
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      size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
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      size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, config) - size; // Padding to match 1_0 size
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      // UL/SUL indicator assumed to be 0
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      break;

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    case NFAPI_NR_UL_DCI_FORMAT_0_1:
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      /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, SRS request 2 --17
      size += 17;
      // Carrier indicator
      // UL/SUL indicator
      // BWP Indicator
      // Freq domain assignment
      // Time domain assignment
      // VRB to PRB mapping
      // Frequency Hopping flag
      // 1st DAI
      // 2nd DAI
      // SRS resource indicator
      // Precoding info and number of layers
      // Antenna ports
      // CSI request
      // CBGTI
      // PTRS - DMRS association
      // beta offset indicator
      // DMRS sequence init
      break;

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    case NFAPI_NR_DL_DCI_FORMAT_1_0:
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      /// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28
      size += 28;
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      size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment
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      break;

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    case NFAPI_NR_DL_DCI_FORMAT_1_1:
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      // Carrier indicator
      size += 1; // Format identifier
      // BWP Indicator
      // Freq domain assignment
      // Time domain assignment
      // VRB to PRB mapping
      // PRB bundling size indicator
      // Rate matching indicator
      // ZP CSI-RS trigger
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      /// TB1- MCS 5, NDI 1, RV 2
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      size += 8;
      // TB2
      size += 4 ;  // HARQ PID
      // DAI
      size += 2; // TPC PUCCH
      size += 3; // PUCCH resource indicator
      size += 3; // PDSCH to HARQ timing indicator
      // Antenna ports
      // Tx Config Indication
      size += 2; // SRS request
      // CBGTI
      // CBGFI
      size += 1; // DMRS sequence init
      break;

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    case NFAPI_NR_DL_DCI_FORMAT_2_0:
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      break;

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    case NFAPI_NR_DL_DCI_FORMAT_2_1:
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      break;

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    case NFAPI_NR_DL_DCI_FORMAT_2_2:
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      break;

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    case NFAPI_NR_DL_DCI_FORMAT_2_3:
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      break;

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    default:
      AssertFatal(1==0, "Invalid NR DCI format %d\n", format);
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  }

  return size;
}

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void nr_pdcch_scrambling(uint32_t *in,
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                         uint32_t size,
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                         uint32_t Nid,
                         uint32_t n_RNTI,
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                         uint32_t *out) {
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  uint8_t reset;
  uint32_t x1, x2, s=0;
  reset = 1;
  x2 = (n_RNTI<<16) + Nid;

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  for (int i=0; i<size; i++) {
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    if ((i&0x1f)==0) {
      s = lte_gold_generic(&x1, &x2, reset);
      reset = 0;
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      if (i) {
        in++;
        out++;
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      }
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    }
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    (*out) ^= ((((*in)>>(i&0x1f))&1) ^ ((s>>(i&0x1f))&1))<<(i&0x1f);
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    //printf("nr_pdcch_scrambling: in %d seq 0x%08x => out %d\n",((*in)>>(i&0x1f))&1,s,((*out)>>(i&0x1f))&1);
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  }
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}

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uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
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                            uint32_t **gold_pdcch_dmrs,
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                            int32_t *txdataF,
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                            int16_t amp,
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                            NR_DL_FRAME_PARMS frame_parms,
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                            nfapi_nr_config_request_t config) {
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  int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1]; // 3 for the max coreset duration
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  uint16_t cset_start_sc;
  uint8_t cset_start_symb, cset_nsymb;
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  int k,l,k_prime,dci_idx, dmrs_idx;
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  nr_cce_t cce;
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  nr_reg_t reg;
  nr_reg_t reg_mapping_list[NR_MAX_PDCCH_AGG_LEVEL*NR_NB_REG_PER_CCE];
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  nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params = dci_alloc.pdcch_params;
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  /*The coreset is initialised
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  * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0
  * or the rb_offset for other coresets
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  * in time: by its first slot and its first symbol*/
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  if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1) {
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    cset_start_sc = frame_parms.first_carrier_offset + (frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB +
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                    pdcch_params.rb_offset)*NR_NB_SC_PER_RB;
  } else
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    cset_start_sc = frame_parms.first_carrier_offset + pdcch_params.rb_offset*NR_NB_SC_PER_RB;

  cset_start_symb = pdcch_params.first_symbol;
  cset_nsymb = pdcch_params.n_symb;
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  dci_idx = 0;
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  LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
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  // DMRS length is per OFDM symbol
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  uint32_t dmrs_length = (pdcch_params.precoder_granularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS)?
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                         (pdcch_params.n_rb*6) : (dci_alloc.L*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
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  uint32_t encoded_length = dci_alloc.L*108; //2(QPSK)*9(per RB)*6(REG per CCE)
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  LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d\n", dmrs_length, encoded_length);
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  dmrs_length += pdcch_params.rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
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  /// DMRS QPSK modulation
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  for (int symb=cset_start_symb; symb<cset_start_symb + pdcch_params.n_symb; symb++) {
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    nr_modulation(gold_pdcch_dmrs[symb], dmrs_length, DMRS_MOD_ORDER, mod_dmrs[symb]); //Qm = 2 as DMRS is QPSK modulated
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#ifdef DEBUG_PDCCH_DMRS

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    for (int i=0; i<dmrs_length>>1; i++)
        printf("symb %d i %d gold seq 0x%08x mod_dmrs %d %d\n", symb, i,
               gold_pdcch_dmrs[symb][i>>5], mod_dmrs[symb][i<<1], mod_dmrs[symb][(i<<1)+1] );
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#endif
  }
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  /// DCI payload processing
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  // CRC attachment + Scrambling + Channel coding + Rate matching
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  uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
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  uint16_t n_RNTI = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.rnti:0;
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  uint16_t Nid = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)?
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                 pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value;
  t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_alloc.size, dci_alloc.L);
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  polar_encoder_fast(dci_alloc.dci_pdu, encoder_output, pdcch_params.rnti, 1, currentPtr);
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#ifdef DEBUG_CHANNEL_CODING
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  printf("polar rnti %d\n",pdcch_params.rnti);
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  printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
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         dci_alloc.dci_pdu[0], dci_alloc.dci_pdu[1]);
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  printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
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  for (int i=0; i<encoded_length>>5; i++)
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    printf("[%d]->0x%08x \t", i,encoder_output[i]);
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  printf("\n");
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#endif
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  /// Scrambling
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  uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0};
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  nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output);
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#ifdef DEBUG_CHANNEL_CODING
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  printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \
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[6]->0x%08x \t [7]->0x%08x \t [8]->0x%08x \t [9]->0x%08x\t [10]->0x%08x\t [11]->0x%08x\n",
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         scrambled_output[0], scrambled_output[1], scrambled_output[2], scrambled_output[3], scrambled_output[4],scrambled_output[5],
         scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] );
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#endif
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  /// QPSK modulation
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  int16_t mod_dci[NR_MAX_DCI_SIZE>>1];
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  nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated
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#ifdef DEBUG_DCI
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  for (int i=0; i<encoded_length>>1; i++)
    printf("i %d mod_dci %d %d\n", i, mod_dci[i<<1], mod_dci[(i<<1)+1] );
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#endif
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  /// Resource mapping

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  if (cset_start_sc >= frame_parms.ofdm_symbol_size)
    cset_start_sc -= frame_parms.ofdm_symbol_size;
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  /*Reorder REG list for a freq first mapping*/
  uint8_t nb_regs = dci_alloc.L*NR_NB_REG_PER_CCE;
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  for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++) {
    cce = dci_alloc.cce_list[cce_idx];

    for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
      reg = cce.reg_list[reg_idx];
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      reg_mapping_list[reg_idx+cce_idx*NR_NB_REG_PER_CCE] = reg;
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    }
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  }


  if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS) {
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    /*in this case the DMRS are mapped on all the coreset*/
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    for (l=cset_start_symb; l<cset_start_symb+ cset_nsymb; l++) {
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      // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
      if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
        dmrs_idx = 0;
      else
        dmrs_idx = pdcch_params.rb_offset*3;

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      k = cset_start_sc + 1;

      while (dmrs_idx<3*pdcch_params.n_rb) {
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        ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1]       = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
        ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
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#ifdef DEBUG_PDCCH_DMRS
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        printf("symbol %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
               ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
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#endif
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        k+=4;
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        if (k >= frame_parms.ofdm_symbol_size)
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          k -= frame_parms.ofdm_symbol_size;
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        dmrs_idx++;
      }
    }
  }

  /*Now mapping the encoded DCI based on newly constructed REG list
   * and the DMRS for the precoder granularity same as REG bundle*/
  for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
    reg = reg_mapping_list[reg_idx];
    k = cset_start_sc + reg.start_sc_idx;

    if (k >= frame_parms.ofdm_symbol_size)
      k -= frame_parms.ofdm_symbol_size;

    l = cset_start_symb + reg.symb_idx;
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    // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
    if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
      dmrs_idx = (reg.reg_idx/cset_nsymb)*3;
    else
      dmrs_idx = ((reg.reg_idx/cset_nsymb)+pdcch_params.rb_offset)*3;

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    k_prime = 0;

    for (int m=0; m<NR_NB_SC_PER_RB; m++) {
      if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
        if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
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          ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1]       = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
          ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
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#ifdef DEBUG_PDCCH_DMRS
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          printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
                 ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
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#endif
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          dmrs_idx++;
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        }
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        k_prime++;
      } else { // DCI payload
        ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1]       = (amp * mod_dci[dci_idx<<1]) >> 15;
        ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15;
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#ifdef DEBUG_DCI
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        printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
               ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
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#endif
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        dci_idx++;
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      }
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      k++;

      if (k >= frame_parms.ofdm_symbol_size)
        k -= frame_parms.ofdm_symbol_size;
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    }
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  }
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  return 0;
}