Commit 8b21d521 authored by Robert Schmidt's avatar Robert Schmidt

Schedule UL according to bitmap

parent 260ee38f
...@@ -346,13 +346,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -346,13 +346,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
const uint64_t dlsch_in_slot_bitmap = BIT( 1) | BIT( 2) | BIT( 3) | BIT( 4) | BIT( 5) | BIT( 6) const uint64_t dlsch_in_slot_bitmap = BIT( 1) | BIT( 2) | BIT( 3) | BIT( 4) | BIT( 5) | BIT( 6)
| BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16); | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16);
uint8_t prach_config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex;
uint64_t ulsch_in_slot_bitmap;
if (prach_config_index==4) //this is the PRACH config used in the Benetel RRU. TODO: make this generic for any PRACH config.
ulsch_in_slot_bitmap = BIT( 8) | BIT( 9);
else
ulsch_in_slot_bitmap = BIT( 8) | BIT(18);
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1 memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info; NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
...@@ -413,9 +406,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -413,9 +406,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} }
// This schedules the DCI for Uplink and subsequently PUSCH // This schedules the DCI for Uplink and subsequently PUSCH
{ nr_schedule_ulsch(module_idP, frame, slot);
nr_schedule_ulsch(module_idP, frame, slot, ulsch_in_slot_bitmap);
}
// This schedules the DCI for Downlink and PDSCH // This schedules the DCI for Downlink and PDSCH
if (is_xlsch_in_slot(dlsch_in_slot_bitmap, slot)) if (is_xlsch_in_slot(dlsch_in_slot_bitmap, slot))
......
...@@ -388,10 +388,8 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -388,10 +388,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
uint32_t target_ul_mcs = 9; uint32_t target_ul_mcs = 9;
uint32_t target_ul_bw = 50; uint32_t target_ul_bw = 50;
uint64_t ulsch_slot_bitmap = (1<<8); uint64_t ulsch_slot_bitmap = (1<<8);
bool nr_ul_preprocessor_phytest(module_id_t module_id, bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot)
frame_t frame, {
sub_frame_t slot,
uint64_t ulsch_in_slot_bitmap) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_id]; gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
...@@ -425,7 +423,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, ...@@ -425,7 +423,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id,
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE /* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below * limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */ * conditions might exclude each other and never be true */
if (!is_xlsch_in_slot(ulsch_slot_bitmap, sched_slot)) if (!is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[slot / 64], sched_slot) || (sched_slot != 8 && sched_slot != 18))
return false; return false;
uint16_t rbStart = 0; uint16_t rbStart = 0;
......
...@@ -986,7 +986,7 @@ void pf_ul(module_id_t module_id, ...@@ -986,7 +986,7 @@ void pf_ul(module_id_t module_id,
} }
} }
bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t slot, uint64_t ulsch_in_slot_bitmap) bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t slot)
{ {
gNB_MAC_INST *nr_mac = RC.nrmac[module_id]; gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_COMMON_channels_t *cc = nr_mac->common_channels;
...@@ -1011,7 +1011,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t ...@@ -1011,7 +1011,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu); int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]); const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]);
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu]; const int sched_slot = (slot + K2) % nr_slots_per_frame[mu];
if (!is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)) if (!is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[slot / 64], sched_slot))
return false; return false;
sched_ctrl->sched_pusch.slot = sched_slot; sched_ctrl->sched_pusch.slot = sched_slot;
...@@ -1087,18 +1087,16 @@ nr_pp_impl_ul nr_init_fr1_ulsch_preprocessor(module_id_t module_id, int CC_id) ...@@ -1087,18 +1087,16 @@ nr_pp_impl_ul nr_init_fr1_ulsch_preprocessor(module_id_t module_id, int CC_id)
return nr_fr1_ulsch_preprocessor; return nr_fr1_ulsch_preprocessor;
} }
void nr_schedule_ulsch(module_id_t module_id, void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
frame_t frame, {
sub_frame_t slot, gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
uint64_t ulsch_in_slot_bitmap) {
/* Uplink data ONLY can be scheduled when the current slot is downlink slot, /* Uplink data ONLY can be scheduled when the current slot is downlink slot,
* because we have to schedule the DCI0 first before schedule uplink data */ * because we have to schedule the DCI0 first before schedule uplink data */
if (is_xlsch_in_slot(ulsch_in_slot_bitmap, slot)) { if (!is_xlsch_in_slot(nr_mac->dlsch_slot_bitmap[slot / 64], slot)) {
LOG_D(MAC, "Current slot %d is NOT DL slot, cannot schedule DCI0 for UL data\n", slot); LOG_D(MAC, "Current slot %d is NOT DL slot, cannot schedule DCI0 for UL data\n", slot);
return; return;
} }
bool do_sched = RC.nrmac[module_id]->pre_processor_ul( bool do_sched = RC.nrmac[module_id]->pre_processor_ul(module_id, frame, slot);
module_id, frame, slot, ulsch_in_slot_bitmap);
if (!do_sched) if (!do_sched)
return; return;
......
...@@ -89,10 +89,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subfram ...@@ -89,10 +89,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subfram
/* \brief main UL scheduler function. Calls a preprocessor to decide on /* \brief main UL scheduler function. Calls a preprocessor to decide on
* resource allocation, then "post-processes" resource allocation (nFAPI * resource allocation, then "post-processes" resource allocation (nFAPI
* messages, statistics, HARQ handling, ... */ * messages, statistics, HARQ handling, ... */
void nr_schedule_ulsch(module_id_t module_id, void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot);
frame_t frame,
sub_frame_t slot,
uint64_t ulsch_in_slot_bitmap);
/* \brief default FR1 UL preprocessor init routine, returns preprocessor to call */ /* \brief default FR1 UL preprocessor init routine, returns preprocessor to call */
nr_pp_impl_ul nr_init_fr1_ulsch_preprocessor(module_id_t module_id, int CC_id); nr_pp_impl_ul nr_init_fr1_ulsch_preprocessor(module_id_t module_id, int CC_id);
...@@ -148,10 +145,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -148,10 +145,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
sub_frame_t slot); sub_frame_t slot);
/* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a /* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a
* fixed set of resources */ * fixed set of resources */
bool nr_ul_preprocessor_phytest(module_id_t module_id, bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
frame_t frame,
sub_frame_t slot,
uint64_t ulsch_in_slot_bitmap);
void nr_schedule_css_dlsch_phytest(module_id_t module_idP, void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
frame_t frameP, frame_t frameP,
......
...@@ -630,8 +630,7 @@ typedef void (*nr_pp_impl_dl)(module_id_t mod_id, ...@@ -630,8 +630,7 @@ typedef void (*nr_pp_impl_dl)(module_id_t mod_id,
sub_frame_t slot); sub_frame_t slot);
typedef bool (*nr_pp_impl_ul)(module_id_t mod_id, typedef bool (*nr_pp_impl_ul)(module_id_t mod_id,
frame_t frame, frame_t frame,
sub_frame_t slot, sub_frame_t slot);
uint64_t ulsch_in_slot_bitmap);
/*! \brief top level eNB MAC structure */ /*! \brief top level eNB MAC structure */
typedef struct gNB_MAC_INST_s { typedef struct gNB_MAC_INST_s {
......
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