Commit aca57eb9 authored by Robert Schmidt's avatar Robert Schmidt

DL scheduler: correctly calculate mixed slot TDA, check TDA before scheduling

parent 7f774d5f
x2_handle_sctp_shutdown 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA NRUE_usedlschparallel NR_2port_CSIRS NR_CSIRS_tomerge NR_F1C_F1U_extensions NR_FR2_initsync_fixes NR_MCS_BLER NR_RRCReconfiguration_BWP NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_SSB_meas NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_new_ul_antennaports NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request RFquality Test_SA_5GREC add-ru-docker-image avxllr bandwidth-testing benetel_config_file_fix benetel_dpdk20 bugfix-nr-t-reordering bugfix_gnb_rt_stats_html ci-add-sabox-support ci-fix-module-ul-iperf ci_benetel_longrun_limits ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_2x2_implem ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_2x2 ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_testinfra_as_code ci_update_build_nasmesh code-cleanup-20210716 debug-UL-5GRECORDS debug_UL_signal develop develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-NSA_SA_fixes develop-aw2sori develop-wf-du develop_fpga_ldpc dongzhanyi-zte-develop1 episys-merge fedora-gen-kernel-fix fix-check fix-compile fix-lte-ue-modem-in-docker-container fix-physim-deploy fix-physim-run-script-on-cluster fix-realtime fix-retransmission-rbg fix_coreset_dmrs_idx fix_nr_ulsim flexran-rtc-repo-is-public hack-bch-no-sched-sf-0 integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_2021_wk28 integration_2021_wk30 integration_2021_wk30_b ldpc_offload_t1 migrate-vm-pipeline-to-bionic multiple_ssb_sib1_bugfix nfapi_nr_arch_mod nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-small-bugfixes nr_improve_chanest nr_ue_remove_high_speed_flag oairu phy-asan-fixes physim-deploy-handle-error-cases prb_based_dl_channel_estimation rh_ci_phy_test_improve rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa scs_60_iisc test-5GREC test-nsa-benetel test-panos usrp_stop_cleanly wf_testc 2021.w30 2021.w29 2021.w28 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b benetel_gnb_rel_2.0 benetel_enb_rel_2.0
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......@@ -100,7 +100,7 @@ void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *
*tdaP_Mi->k0);
int start, len;
SLIV2SL(tdaP_Mi->startSymbolAndLength, &start, &len);
const uint16_t symb_tda = ((1 << start) - 1) << start;
const uint16_t symb_tda = ((1 << len) - 1) << start;
// check whether coreset and TDA overlap: then, we cannot use it. Also,
// check whether TDA is entirely within mixed slot DL. Note that
// here we assume that the coreset is scheduled every slot (which it
......@@ -685,6 +685,11 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
/* Get bwpSize from the first UE */
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
if (tda < 0)
return;
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
......
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