Commit d4a746ac authored by francescomani's avatar francescomani

fix for 2 layers dlsim using layers in NR_pdsch_semi_static_t

parent fab6ec45
......@@ -263,6 +263,8 @@ void nr_dlsim_preprocessor(module_id_t module_id,
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
ps->nrOfLayers = g_nrOfLayers;
nr_set_pdsch_semi_static(scc,
UE_info->CellGroup[0],
sched_ctrl->active_bwp,
......@@ -278,7 +280,6 @@ void nr_dlsim_preprocessor(module_id_t module_id,
* configuration */
ps->mcsTableIdx = g_mcsTableIdx;
sched_pdsch->nrOfLayers = g_nrOfLayers;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm,
......@@ -288,7 +289,7 @@ void nr_dlsim_preprocessor(module_id_t module_id,
ps->N_PRB_DMRS * ps->N_DMRS_SLOT,
0 /* N_PRB_oh, 0 for initialBWP */,
0 /* tb_scaling */,
sched_pdsch->nrOfLayers)
ps->nrOfLayers)
>> 3;
/* the simulator assumes the HARQ PID is equal to the slot number */
......
......@@ -603,7 +603,7 @@ void pf_dl(module_id_t module_id,
/* Calculate coeff */
sched_pdsch->mcs = 9;
sched_pdsch->nrOfLayers = 1;
ps->nrOfLayers = 1;
uint32_t tbs = pf_tbs[ps->mcsTableIdx][sched_pdsch->mcs];
coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id];
LOG_D(NR_MAC,"b %d, thr_ue[%d] %f, tbs %d, coeff_ue[%d] %f\n",
......@@ -820,17 +820,17 @@ void nr_schedule_ue_spec(module_id_t module_id,
const rnti_t rnti = UE_info->rnti[UE_id];
/* POST processing */
const uint8_t nrOfLayers = sched_pdsch->nrOfLayers;
const uint16_t R = sched_pdsch->R;
const uint8_t Qm = sched_pdsch->Qm;
const uint32_t TBS = sched_pdsch->tb_size;
/* pre-computed PDSCH values that only change if time domain
* allocation/DMRS parameters change. Updated in the preprocessor through
* nr_set_pdsch_semi_static() */
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
/* POST processing */
const uint8_t nrOfLayers = ps->nrOfLayers;
const uint16_t R = sched_pdsch->R;
const uint8_t Qm = sched_pdsch->Qm;
const uint32_t TBS = sched_pdsch->tb_size;
int8_t current_harq_pid = sched_pdsch->dl_harq_pid;
if (current_harq_pid < 0) {
/* PP has not selected a specific HARQ Process, get a new one */
......@@ -940,7 +940,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
pdsch_pdu->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu->SCID = 0;
pdsch_pdu->numDmrsCdmGrpsNoData = ps->numDmrsCdmGrpsNoData;
pdsch_pdu->dmrsPorts = 1;
pdsch_pdu->dmrsPorts = (1<<nrOfLayers)-1; // FIXME with a better implementation
// Pdsch Allocation in frequency domain
pdsch_pdu->resourceAlloc = 1;
......@@ -1022,7 +1022,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
dci_payload.tpc = sched_ctrl->tpc1; // TPC for PUCCH: table 7.2.1-1 in 38.213
dci_payload.pucch_resource_indicator = pucch->resource_indicator;
dci_payload.pdsch_to_harq_feedback_timing_indicator.val = pucch->timing_indicator; // PDSCH to HARQ TI
dci_payload.antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0
dci_payload.antenna_ports.val = ps->dmrs_ports_id;
dci_payload.dmrs_sequence_initialization.val = pdsch_pdu->SCID;
LOG_D(NR_MAC,
"%4d.%2d DCI type 1 payload: freq_alloc %d (%d,%d,%d), "
......
......@@ -373,7 +373,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
nr_set_pdsch_semi_static(
scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, tda, num_dmrs_cdm_grps_no_data, ps);
sched_pdsch->nrOfLayers = target_dl_Nl;
ps->nrOfLayers = target_dl_Nl;
sched_pdsch->mcs = target_dl_mcs;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
......@@ -384,7 +384,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
ps->N_PRB_DMRS * ps->N_DMRS_SLOT,
0 /* N_PRB_oh, 0 for initialBWP */,
0 /* tb_scaling */,
sched_pdsch->nrOfLayers)
ps->nrOfLayers)
>> 3;
/* get the PID of a HARQ process awaiting retransmission, or -1 otherwise */
......
......@@ -122,6 +122,36 @@ static inline uint8_t get_max_cces(uint8_t scs) {
return (nr_max_number_of_cces_per_slot[scs]);
}
void set_dl_dmrs_ports(NR_pdsch_semi_static_t *ps) {
//TODO first basic implementation of dmrs port selection
// only vaild for a single codeword
// for now it assumes a selection of Nl consecutive dmrs ports
// and a single front loaded symbol
// dmrs_ports_id is the index of Tables 7.3.1.2.2-1/2/3/4
switch (ps->nrOfLayers) {
case 1:
ps->dmrs_ports_id = 0;
ps->numDmrsCdmGrpsNoData = 1;
break;
case 2:
ps->dmrs_ports_id = 2;
ps->numDmrsCdmGrpsNoData = 1;
break;
case 3:
ps->dmrs_ports_id = 9;
ps->numDmrsCdmGrpsNoData = 2;
break;
case 4:
ps->dmrs_ports_id = 10;
ps->numDmrsCdmGrpsNoData = 2;
break;
default:
AssertFatal(1==0,"Number of layers %d\n not supported or not valid\n",ps->nrOfLayers);
}
}
NR_ControlResourceSet_t *get_coreset(NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp,
NR_SearchSpace_t *ss,
......@@ -295,7 +325,7 @@ void nr_set_pdsch_semi_static(const NR_ServingCellConfigCommon_t *scc,
}
else ps->mcsTableIdx = 0;
ps->numDmrsCdmGrpsNoData = num_dmrs_cdm_grps_no_data;
set_dl_dmrs_ports(ps);
ps->dmrsConfigType = bwp!=NULL ? (bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1) : 0;
// if no data in dmrs cdm group is 1 only even REs have no data
......
......@@ -415,6 +415,8 @@ int16_t ssb_index_from_prach(module_id_t module_idP,
void find_SSB_and_RO_available(module_id_t module_idP);
void set_dl_dmrs_ports(NR_pdsch_semi_static_t *ps);
void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *bwp);
void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ubwp);
......
......@@ -365,9 +365,9 @@ typedef struct NR_pdsch_semi_static {
int startSymbolIndex;
int nrOfSymbols;
uint8_t nrOfLayers;
uint8_t mcsTableIdx;
uint8_t dmrs_ports_id;
uint8_t N_PRB_DMRS;
uint8_t N_DMRS_SLOT;
uint16_t dl_dmrs_symb_pos;
......@@ -383,7 +383,6 @@ typedef struct NR_sched_pdsch {
uint8_t mcs;
/// TBS-related info
uint8_t nrOfLayers;
uint16_t R;
uint8_t Qm;
uint32_t tb_size;
......
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