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wangjie
OpenXG-RAN
Commits
ec98cd2f
Commit
ec98cd2f
authored
Jan 19, 2021
by
imad
Committed by
Robert Schmidt
Jan 20, 2021
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Limit to 1 DL/1 UL slot
parent
9fd49e04
Changes
1
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1 changed file
with
2 additions
and
3 deletions
+2
-3
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+2
-3
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
ec98cd2f
...
...
@@ -368,9 +368,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
#define BIT(x) (1 << (x))
const
uint64_t
dlsch_in_slot_bitmap
=
BIT
(
1
)
|
BIT
(
2
)
|
BIT
(
3
)
|
BIT
(
4
)
|
BIT
(
5
)
|
BIT
(
6
)
|
BIT
(
11
)
|
BIT
(
12
)
|
BIT
(
13
)
|
BIT
(
14
)
|
BIT
(
15
)
|
BIT
(
16
);
const
uint64_t
ulsch_in_slot_bitmap
=
BIT
(
8
)
|
BIT
(
18
);
const
uint64_t
dlsch_in_slot_bitmap
=
BIT
(
1
);
const
uint64_t
ulsch_in_slot_bitmap
=
BIT
(
8
);
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coreset0
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coresetid 1
...
...
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