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Commit ee45cf21 authored by yihongzheng's avatar yihongzheng
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FPGA decode just test, not all

parent 2ee68a92
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Showing with 242 additions and 40 deletions
openair1/PHY/CODING/nrLDPC_defs.h
View file @ ee45cf21
...@@ -50,6 +50,7 @@ typedef int(*nrLDPC_encoderfunc_t)(unsigned char **,unsigned char **,int,int,sho ...@@ -50,6 +50,7 @@ typedef int(*nrLDPC_encoderfunc_t)(unsigned char **,unsigned char **,int,int,sho
// typedef int(*LDPC_FPGA_EnTx_Test)(int , int); // typedef int(*LDPC_FPGA_EnTx_Test)(int , int);
typedef int(*LDPC_FPGA_HugePage_Init)(int); typedef int(*LDPC_FPGA_HugePage_Init)(int);
typedef int(*LDPC_FPGA_EnTx)( EncodeInHeaderStruct *pHeader, unsigned char * pSrc, unsigned char * pDst ); typedef int(*LDPC_FPGA_EnTx)( EncodeInHeaderStruct *pHeader, unsigned char * pSrc, unsigned char * pDst );
typedef int(*LDPC_FPGA_DeTx)( DecodeInHeaderStruct *pHeader, unsigned char * pSrc, unsigned char * pDst );
//============================================================================================================================ //============================================================================================================================
// decoder interface // decoder interface
/** /**
......
openair1/PHY/CODING/nrLDPC_extern.h
View file @ ee45cf21
...@@ -26,6 +26,7 @@ nrLDPC_encoderfunc_t nrLDPC_encoder; ...@@ -26,6 +26,7 @@ nrLDPC_encoderfunc_t nrLDPC_encoder;
// LDPC_FPGA_EnTx_Test add; // LDPC_FPGA_EnTx_Test add;
LDPC_FPGA_HugePage_Init HugePage_Init; LDPC_FPGA_HugePage_Init HugePage_Init;
LDPC_FPGA_EnTx encoder_load; LDPC_FPGA_EnTx encoder_load;
LDPC_FPGA_DeTx decoder_load;
#else #else
/* functions to load the LDPC shared lib, implemented in openair1/PHY/CODING/nrLDPC_load.c */ /* functions to load the LDPC shared lib, implemented in openair1/PHY/CODING/nrLDPC_load.c */
extern int load_nrLDPClib(void) ; extern int load_nrLDPClib(void) ;
...@@ -36,6 +37,7 @@ extern nrLDPC_encoderfunc_t nrLDPC_encoder; ...@@ -36,6 +37,7 @@ extern nrLDPC_encoderfunc_t nrLDPC_encoder;
// extern LDPC_FPGA_EnTx_Test add; // extern LDPC_FPGA_EnTx_Test add;
extern LDPC_FPGA_HugePage_Init HugePage_Init; extern LDPC_FPGA_HugePage_Init HugePage_Init;
extern LDPC_FPGA_EnTx encoder_load; extern LDPC_FPGA_EnTx encoder_load;
extern LDPC_FPGA_DeTx decoder_load;
// inline functions: // inline functions:
#include "openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h" #include "openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h"
#endif #endif
\ No newline at end of file
openair1/PHY/CODING/nrLDPC_load.c
View file @ ee45cf21
...@@ -102,6 +102,12 @@ int load_nrLDPClib(void) { ...@@ -102,6 +102,12 @@ int load_nrLDPClib(void) {
dlclose(handle); dlclose(handle);
return -1; return -1;
} }
decoder_load = (LDPC_FPGA_DeTx) dlsym(handle, "decoder_load");
if(!decoder_load){
printf("FPGA loading decoder_load error!\n");
dlclose(handle);
return -1;
}
#endif #endif
// int sum = add(7, 8); // int sum = add(7, 8);
// printf("7+8 = %d\n", sum); // printf("7+8 = %d\n", sum);
......
openair1/PHY/NR_TRANSPORT/ldpc_fpga_entx.h
View file @ ee45cf21
...@@ -30,7 +30,7 @@ typedef struct{ ...@@ -30,7 +30,7 @@ typedef struct{
uint32_t rev8 :1; uint32_t rev8 :1;
uint32_t fillbit :14; uint32_t fillbit :14;
uint32_t rev9 :2; uint32_t rev9 :2;
uint32_t kpInByte :11; uint32_t kpInByte :11; //encode的单位是Byte
uint32_t rev10 :1; uint32_t rev10 :1;
/*Word 6*/ /*Word 6*/
uint32_t gamma :8; uint32_t gamma :8;
...@@ -47,3 +47,103 @@ typedef struct{ ...@@ -47,3 +47,103 @@ typedef struct{
uint32_t e0 :16; uint32_t e0 :16;
}EncodeInHeaderStruct; }EncodeInHeaderStruct;
typedef struct
{
/*Word 0*/
uint32_t pktType :8;
uint32_t rsv0 :8;
uint32_t chkCode :16;
/*Word 1*/
uint32_t pktLen :21; /*包含header + DDRheader + CB DATA的长度,单位是byte*/
uint32_t rsv1 :11;
/*Word 2*/
uint32_t pktTpTmp :4;
uint32_t pduSize :24; /*包含header + DDRheader + CB DATA的长度,单位是Word*/
uint32_t sectorId :2;
uint32_t rsv2 :2;
/*Word 3*/
uint32_t sfn :10;
uint32_t rsv3 :2;
uint32_t subfn :4;
uint32_t slotNum :5;
uint32_t pduIdx :9;
uint32_t rev4 :2;
/*Word 4*/
uint32_t tbSizeB :18; /*tbsize的大小，单位byte*/
uint32_t rev5 :2;
uint32_t lastTb :1;
uint32_t firstTb :1;
uint32_t rev6 :2;
uint32_t cbNum :8; /*码块数*/
/*Word 5*/
uint32_t qm :3;
uint32_t rev7 :1;
uint32_t fillbit :14;
uint32_t kpInByte :14; /* 被均分后每个cb块的长度，单位bit */
/*Word 6*/
uint32_t gamma :8;
uint32_t maxRowNm :6; //填成46
uint32_t maxRvIdx :2;
uint32_t rvIdx :2;
uint32_t ndi :1;
uint32_t flush :1;
uint32_t maxIter :4;
uint32_t lfSizeIx :3;
uint32_t rev10 :1;
uint32_t iLs :3;
uint32_t bg :1;
/*Word 7*/
uint32_t e1 :16;
uint32_t e0 :16;
}DecodeInHeaderStruct;
typedef struct
{
/*word 0*/
uint32_t pktType :8; /* FEC RX 类型： 0x11*/
uint32_t rsv0 :8;
uint32_t chkCode :16; /* 数据校验 ：0xFAFA*/
/*word 1*/
uint32_t pktLen :21; /* 包括 FPGA_ALIGN(header+ FPGA_ALIGN4B(tbsizeB)+4byte) */
uint32_t rsv1 :11;
/*word 2*/
uint32_t pktTpTmp :4;
uint32_t pduSize :20; /* pktLen长度除以4 单位 word*/
uint32_t rsv2 :4;
uint32_t sectorId :2;
uint32_t rsv3 :2;
/*word 3*/
uint32_t sfn :10; /* 帧号 */
uint32_t rsv4 :2;
uint32_t subfn :4; /* 子帧号 */
uint32_t slotNum :5; /* 时隙号 */
uint32_t pduIdx :9;
uint32_t rsv5 :2;
/*Word 4*/
uint32_t tbSizeB :18; /* tbsize 的大小，单位byte*/
uint32_t rsv6 :2;
uint32_t lastTb :1;
uint32_t firstTb :1;
uint32_t rsv7 :2;
uint32_t cbNum :8;
/*Word 5*/
uint32_t rsv8 :32;
/*Word 6*/
uint32_t rsv9 :32;
/*Word 7*/
uint32_t rsv10 :32;
}DecodeOutHeaderStruct;
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
View file @ ee45cf21
...@@ -77,7 +77,7 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in, ...@@ -77,7 +77,7 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in,
uint32_t* out) { uint32_t* out) {
uint32_t x1, x2, s=0; uint32_t x1, x2, s=0;
// uint32_t in32 = 0; uint32_t in32 = 0;
// static uint32_t count_data = 0; // static uint32_t count_data = 0;
// uint8_t *u8data; // uint8_t *u8data;
uint32_t *pin32; uint32_t *pin32;
...@@ -90,7 +90,7 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in, ...@@ -90,7 +90,7 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in,
#if defined(__AVX2__) #if defined(__AVX2__)
#if 0 //OAI自己的加扰代码 #if 1 //OAI自己的加扰代码
for (int i=0; i<((size>>5)+((size&0x1f) > 0 ? 1 : 0)); i++) { for (int i=0; i<((size>>5)+((size&0x1f) > 0 ? 1 : 0)); i++) {
in32=_mm256_movemask_epi8(_mm256_slli_epi16(((__m256i*)in)[i],7)); in32=_mm256_movemask_epi8(_mm256_slli_epi16(((__m256i*)in)[i],7));
out[i]=(in32^s); out[i]=(in32^s);
...@@ -102,13 +102,13 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in, ...@@ -102,13 +102,13 @@ void nr_pdsch_codeword_scrambling_optim(uint8_t *in,
//printf("in[%d] %x => %x\n",i,in32,out[i]); //printf("in[%d] %x => %x\n",i,in32,out[i]);
s=lte_gold_generic(&x1, &x2, 0); s=lte_gold_generic(&x1, &x2, 0);
} }
if(count_data == 9) // if(count_data == 9)
{ // {
LOG_M("out1.m","out1", out, (byteSize+3)/4, 1, 9); // LOG_M("out1.m","out1", out, (byteSize+3)/4, 1, 9);
} // }
count_data++; // count_data++;
#endif #endif
#if 1 #if 0
//让FPGA输出的每个BYTE中的高低位bit翻转 //让FPGA输出的每个BYTE中的高低位bit翻转
//LOG_I(PHY, "in = %02x, %02x, %02x, %02x, %02x, %02x, %02x, %02x\n",in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]); //LOG_I(PHY, "in = %02x, %02x, %02x, %02x, %02x, %02x, %02x, %02x\n",in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]);
Byte_Reverse_11(in, in, byteSize); Byte_Reverse_11(in, in, byteSize);
...@@ -222,16 +222,16 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB, ...@@ -222,16 +222,16 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB,
/// CRC, coding, interleaving and rate matching /// CRC, coding, interleaving and rate matching
AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n");
start_meas(dlsch_encoding_stats); start_meas(dlsch_encoding_stats);
// nr_dlsch_encoding(gNB, nr_dlsch_encoding(gNB,
// harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput,
// dlsch_rate_matching_stats,
// dlsch_interleaving_stats,
// dlsch_segmentation_stats);
nr_dlsch_encoding_fpga_ldpc(gNB,
harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput, harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput,
dlsch_rate_matching_stats, dlsch_rate_matching_stats,
dlsch_interleaving_stats, dlsch_interleaving_stats,
dlsch_segmentation_stats); dlsch_segmentation_stats);
// nr_dlsch_encoding_fpga_ldpc(gNB,
// harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput,
// dlsch_rate_matching_stats,
// dlsch_interleaving_stats,
// dlsch_segmentation_stats);
stop_meas(dlsch_encoding_stats); stop_meas(dlsch_encoding_stats);
#ifdef DEBUG_DLSCH #ifdef DEBUG_DLSCH
printf("PDSCH encoding:\nPayload:\n"); printf("PDSCH encoding:\nPayload:\n");
......
openair1/PHY/NR_TRANSPORT/nr_dlsch.h
View file @ ee45cf21
...@@ -82,20 +82,7 @@ int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type); ...@@ -82,20 +82,7 @@ int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type);
NR_gNB_SCH_STATS_t *find_nr_dlsch_stats(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type); NR_gNB_SCH_STATS_t *find_nr_dlsch_stats(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type);
// int nr_dlsch_encoding(PHY_VARS_gNB *gNB, int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
// unsigned char *a,int frame,
// uint8_t slot,
// NR_gNB_DLSCH_t *dlsch,
// NR_DL_FRAME_PARMS* frame_parms,
// time_stats_t *tinput,
// time_stats_t *tprep,
// time_stats_t *tparity,
// time_stats_t *toutput,
// time_stats_t *dlsch_rate_matching_stats,
// time_stats_t *dlsch_interleaving_stats,
// time_stats_t *dlsch_segmentation_stats);
int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB,
unsigned char *a,int frame, unsigned char *a,int frame,
uint8_t slot, uint8_t slot,
NR_gNB_DLSCH_t *dlsch, NR_gNB_DLSCH_t *dlsch,
...@@ -106,7 +93,20 @@ int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB, ...@@ -106,7 +93,20 @@ int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB,
time_stats_t *toutput, time_stats_t *toutput,
time_stats_t *dlsch_rate_matching_stats, time_stats_t *dlsch_rate_matching_stats,
time_stats_t *dlsch_interleaving_stats, time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats); time_stats_t *dlsch_segmentation_stats);
// int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB,
// unsigned char *a,int frame,
// uint8_t slot,
// NR_gNB_DLSCH_t *dlsch,
// NR_DL_FRAME_PARMS* frame_parms,
// time_stats_t *tinput,
// time_stats_t *tprep,
// time_stats_t *tparity,
// time_stats_t *toutput,
// time_stats_t *dlsch_rate_matching_stats,
// time_stats_t *dlsch_interleaving_stats,
// time_stats_t *dlsch_segmentation_stats);
void init_dlsch_tpool(uint8_t nun_dlsch_threads); void init_dlsch_tpool(uint8_t nun_dlsch_threads);
void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size); void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size);
......
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
View file @ ee45cf21
...@@ -241,7 +241,7 @@ void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch) ...@@ -241,7 +241,7 @@ void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
} }
} }
#if 0 #if 1
// unsigned char EnDataOut[0x20000]={0}; // unsigned char EnDataOut[0x20000]={0};
int nr_dlsch_encoding(PHY_VARS_gNB *gNB, int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
unsigned char *a, unsigned char *a,
...@@ -323,7 +323,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB, ...@@ -323,7 +323,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
} }
G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,rel15->nrOfLayers); G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,rel15->nrOfLayers);
LOG_I(PHY,"dlsch coding A %d G %d (nb_rb %d, nb_symb_sch %d, nb_re_dmrs %d, length_dmrs %d, mod_order %d)\n", A,G, nb_rb,nb_symb_sch,nb_re_dmrs,length_dmrs,mod_order); LOG_D(PHY,"dlsch coding A %d G %d (nb_rb %d, nb_symb_sch %d, nb_re_dmrs %d, length_dmrs %d, mod_order %d)\n", A,G, nb_rb,nb_symb_sch,nb_re_dmrs,length_dmrs,mod_order);
if (A > 3824) { if (A > 3824) {
// Add 24-bit crc (polynomial A) to payload // Add 24-bit crc (polynomial A) to payload
...@@ -491,7 +491,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB, ...@@ -491,7 +491,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
r_offset += E; r_offset += E;
} }
#if 1 #if 0
LOG_I(PHY, "dl_encode_count = %d\n", dl_encode_count); LOG_I(PHY, "dl_encode_count = %d\n", dl_encode_count);
// if(dl_encode_count == dl_encode_count_set2) // if(dl_encode_count == dl_encode_count_set2)
{ {
...@@ -657,7 +657,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB, ...@@ -657,7 +657,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
} }
#endif #endif
#if 1 #if 0
//FPGA加速，删除了部分OAI中的encode函数 //FPGA加速，删除了部分OAI中的encode函数
int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB, int nr_dlsch_encoding_fpga_ldpc(PHY_VARS_gNB *gNB,
unsigned char *a, unsigned char *a,
......
openair1/PHY/NR_TRANSPORT/nr_ulsch.h
View file @ ee45cf21
...@@ -94,3 +94,5 @@ void dump_pusch_stats(FILE *fd,PHY_VARS_gNB *gNB); ...@@ -94,3 +94,5 @@ void dump_pusch_stats(FILE *fd,PHY_VARS_gNB *gNB);
void clear_pusch_stats(PHY_VARS_gNB *gNB); void clear_pusch_stats(PHY_VARS_gNB *gNB);
NR_gNB_SCH_STATS_t *get_ulsch_stats(PHY_VARS_gNB *gNB,NR_gNB_ULSCH_t *ulsch); NR_gNB_SCH_STATS_t *get_ulsch_stats(PHY_VARS_gNB *gNB,NR_gNB_ULSCH_t *ulsch);
void ul_find_iLS_lsIndex(unsigned int *LDPC_lifting_size, uint32_t *iLS_out, uint32_t *lsIndex_out);
\ No newline at end of file
openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
View file @ ee45cf21
...@@ -499,6 +499,14 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ...@@ -499,6 +499,14 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
uint8_t n_layers = pusch_pdu->nrOfLayers; uint8_t n_layers = pusch_pdu->nrOfLayers;
// ------------------------------------------------------------------ // ------------------------------------------------------------------
static uint32_t ul_decode_count = 0;
uint32_t ul_decode_count_set2 = 8;
uint32_t iLS, lsIndex = 0;
uint32_t E0, E1 = 0;
DecodeInHeaderStruct DecodeHead;
// uint8_t *pEnDataIn = NULL;
// uint8_t *pEnDataOut = NULL;
if (!ulsch_llr) { if (!ulsch_llr) {
LOG_E(PHY,"ulsch_decoding.c: NULL ulsch_llr pointer\n"); LOG_E(PHY,"ulsch_decoding.c: NULL ulsch_llr pointer\n");
return 1; return 1;
...@@ -650,5 +658,79 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ...@@ -650,5 +658,79 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0)); offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0));
////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////
} }
if(ul_decode_count == ul_decode_count_set2){
DecodeHead.cbNum = harq_process->C;
DecodeHead.tbSizeB = A>>3;
DecodeHead.pktLen = 32+(DecodeHead.cbNum-1)*32+((DecodeHead.tbSizeB+32-1)/32)*32;//Byte，pktLen=decoder header(32byte)+ DDR Header + tbszie (byte)，并且32Byte对齐，是32的整数倍
DecodeHead.pduSize = DecodeHead.pktLen/4; //word
DecodeHead.qm = Qm/2;//规定是BPSK qm=0,QPSK qm=1,其他floor(调制阶数/2)；OAI的Qm为2/4/6/8
DecodeHead.sfn = frame;
DecodeHead.slotNum = nr_tti_rx;
DecodeHead.subfn = DecodeHead.slotNum/2;
DecodeHead.fillbit = harq_process->F;
DecodeHead.bg = p_decParams->BG-1; //规定选择协议base grape1 bg=0; base grape2 bg=1；OAI的BG大了1
ul_find_iLS_lsIndex(&harq_process->Z, &iLS, &lsIndex);
DecodeHead.iLs = iLS;
DecodeHead.lfSizeIx = lsIndex;
if(DecodeHead.bg == 0){
DecodeHead.maxRowNm = 46;
}
else{
DecodeHead.maxRowNm = 42;
}
if(DecodeHead.cbNum == 1){
DecodeHead.kpInByte = ((harq_process->B)/DecodeHead.cbNum); //decode的kpInByte应该用bit，encode用的Byte
}
else{
DecodeHead.kpInByte = ((harq_process->B+((DecodeHead.cbNum)*24))/DecodeHead.cbNum);
}
nr_get_E0_E1(G, harq_process->C, Qm, n_layers, r, &E0, &E1);
DecodeHead.e0 = E0;
DecodeHead.e1 = E1;
DecodeHead.rvIdx = pusch_pdu->pusch_data.rv_index;
DecodeHead.ndi = 1; //1表示新传，0表示重传
DecodeHead.flush = 0;
DecodeHead.maxIter = 4; //最大迭代次数
DecodeHead.maxRvIdx = 0;
DecodeHead.pktType = 0x10;
DecodeHead.chkCode = 0xFAFA;
DecodeHead.pktTpTmp = 0;
DecodeHead.sectorId = 0; //=0表示单小区
DecodeHead.pduIdx = 0; //=0表示第一个码字，总共一个码字
DecodeHead.lastTb = 1;
DecodeHead.firstTb = 1; //=1表示本slot只有一个TB
DecodeHead.gamma = DecodeHead.cbNum - (G/(n_layers*(2*DecodeHead.qm)))%DecodeHead.cbNum; //=1表示本slot只有一个TB
// LOG_M("ul_decode_before.m","before", ulsch_llr, G, 1, 4);
}
ul_decode_count++; //count +1 after encoding
LOG_I(PHY,"ul_decode_count = %d\n", ul_decode_count);
return 1; return 1;
} }
void ul_find_iLS_lsIndex(unsigned int *LDPC_lifting_size, uint32_t *iLS_out, uint32_t *lsIndex_out)
{
unsigned int Set_of_LDPC_lifting_size[8][8] = {
{2,4,8,16,32,64,128,256},
{3,6,12,24,48,96,192,384},
{5,10,20,40,80,160,320},
{7,14,28,56,112,224},
{9,18,36,72,144,288},
{11,22,44,88,176,352},
{13,26,52,104,208},
{15,30,60,120,240}};
uint32_t iLS,lsIndex;
for(iLS = 0; iLS < 8; iLS++) {
for(lsIndex = 0; lsIndex < 8; lsIndex++){
if(*LDPC_lifting_size == Set_of_LDPC_lifting_size[iLS][lsIndex]){
*iLS_out = iLS;
*lsIndex_out = lsIndex;
}
}
}
}
\ No newline at end of file
openair1/SIMULATION/NR_PHY/dlschsim.c
View file @ ee45cf21
...@@ -502,8 +502,8 @@ int main(int argc, char **argv) ...@@ -502,8 +502,8 @@ int main(int argc, char **argv)
//printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32)); //printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32));
// generate signal // generate signal
if (input_fd == NULL) { if (input_fd == NULL) {
// nr_dlsch_encoding(gNB, test_input, frame, slot, dlsch, frame_parms,NULL,NULL,NULL,NULL,NULL,NULL,NULL); nr_dlsch_encoding(gNB, test_input, frame, slot, dlsch, frame_parms,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
nr_dlsch_encoding_fpga_ldpc(gNB, test_input, frame, slot, dlsch, frame_parms,NULL,NULL,NULL,NULL,NULL,NULL,NULL); // nr_dlsch_encoding_fpga_ldpc(gNB, test_input, frame, slot, dlsch, frame_parms,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
} }
for (SNR = snr0; SNR < snr1; SNR += snr_step) { for (SNR = snr0; SNR < snr1; SNR += snr_step) {
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ ee45cf21
...@@ -358,6 +358,7 @@ void nr_store_dlsch_buffer(module_id_t module_id, ...@@ -358,6 +358,7 @@ void nr_store_dlsch_buffer(module_id_t module_id,
0, 0,
0); 0);
sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer; sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
// sched_ctrl->num_total_bytes = 8000;
LOG_D(NR_MAC, LOG_D(NR_MAC,
"%d.%d, LCID%d:->DLSCH, RLC status %d bytes. \n", "%d.%d, LCID%d:->DLSCH, RLC status %d bytes. \n",
frame, frame,
...@@ -519,6 +520,7 @@ void pf_dl(module_id_t module_id, ...@@ -519,6 +520,7 @@ void pf_dl(module_id_t module_id,
sched_ctrl->time_domain_allocation = 2; sched_ctrl->time_domain_allocation = 2;
sched_ctrl->mcsTableIdx = 0; sched_ctrl->mcsTableIdx = 0;
sched_ctrl->mcs = 9; sched_ctrl->mcs = 9;
// sched_ctrl->mcs = 22;
sched_ctrl->numDmrsCdmGrpsNoData = sched_ctrl->active_bwp ? 2 : 1; sched_ctrl->numDmrsCdmGrpsNoData = sched_ctrl->active_bwp ? 2 : 1;
uint8_t N_PRB_DMRS = uint8_t N_PRB_DMRS =
getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData); getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
...@@ -611,6 +613,7 @@ void pf_dl(module_id_t module_id, ...@@ -611,6 +613,7 @@ void pf_dl(module_id_t module_id,
// modulation scheme // modulation scheme
sched_ctrl->mcsTableIdx = 0; sched_ctrl->mcsTableIdx = 0;
sched_ctrl->mcs = 9; sched_ctrl->mcs = 9;
// sched_ctrl->mcs = 22;
sched_ctrl->numDmrsCdmGrpsNoData = sched_ctrl->active_bwp ? 1 : 2; sched_ctrl->numDmrsCdmGrpsNoData = sched_ctrl->active_bwp ? 1 : 2;
// Freq-demain allocation // Freq-demain allocation
...@@ -650,6 +653,8 @@ void pf_dl(module_id_t module_id, ...@@ -650,6 +653,8 @@ void pf_dl(module_id_t module_id,
sched_ctrl->rbSize = rbSize; sched_ctrl->rbSize = rbSize;
sched_ctrl->rbStart = rbStart; sched_ctrl->rbStart = rbStart;
// LOG_I(MAC,"dlsch : rbSize %d, TBS %d, slot %d, symbols %d, frame %d, ta_frame %d, mcs %d sched_dl bytes %d\n",
// rbSize, TBS, slot, nrOfSymbols, frame , sched_ctrl->ta_frame, sched_ctrl->mcs, sched_ctrl->num_total_bytes);
/* transmissions: directly allocate */ /* transmissions: directly allocate */
n_rb_sched -= sched_ctrl->rbSize; n_rb_sched -= sched_ctrl->rbSize;
for (int rb = 0; rb < sched_ctrl->rbSize; rb++) for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ ee45cf21
...@@ -661,6 +661,7 @@ void pf_ul(module_id_t module_id, ...@@ -661,6 +661,7 @@ void pf_ul(module_id_t module_id,
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[CC_id].ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[CC_id].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info; NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
const int min_rb = 5; const int min_rb = 5;
// const int min_rb = 100;
float coeff_ue[MAX_MOBILES_PER_GNB]; float coeff_ue[MAX_MOBILES_PER_GNB];
// UEs that could be scheduled // UEs that could be scheduled
int ue_array[MAX_MOBILES_PER_GNB]; int ue_array[MAX_MOBILES_PER_GNB];
...@@ -765,6 +766,7 @@ void pf_ul(module_id_t module_id, ...@@ -765,6 +766,7 @@ void pf_ul(module_id_t module_id,
/* Calculate TBS from MCS */ /* Calculate TBS from MCS */
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch; NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
const int mcs = 9; const int mcs = 9;
// const int mcs = 16;
sched_pusch->mcs = mcs; sched_pusch->mcs = mcs;
sched_pusch->R = nr_get_code_rate_ul(mcs, ps->mcs_table); sched_pusch->R = nr_get_code_rate_ul(mcs, ps->mcs_table);
sched_pusch->Qm = nr_get_Qm_ul(mcs, ps->mcs_table); sched_pusch->Qm = nr_get_Qm_ul(mcs, ps->mcs_table);
...@@ -808,6 +810,8 @@ void pf_ul(module_id_t module_id, ...@@ -808,6 +810,8 @@ void pf_ul(module_id_t module_id,
0, 0,
1 /* NrOfLayers */) 1 /* NrOfLayers */)
>> 3; >> 3;
// LOG_I(NR_MAC,"rbSize %d, TBS %d, est buf %d, sched_ul %d, frame %d, slot %d, nrOfSymbols %d, num_dmrs_symb %d\n",
// sched_pusch->rbSize, sched_pusch->tb_size, sched_ctrl->estimated_ul_buffer, sched_ctrl->sched_ul_bytes, frame, slot, ps->nrOfSymbols, ps->num_dmrs_symb);
/* Mark the corresponding RBs as used */ /* Mark the corresponding RBs as used */
n_rb_sched -= sched_pusch->rbSize; n_rb_sched -= sched_pusch->rbSize;
...@@ -898,8 +902,8 @@ void pf_ul(module_id_t module_id, ...@@ -898,8 +902,8 @@ void pf_ul(module_id_t module_id,
>> 3; >> 3;
} while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart+rbSize] && } while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart+rbSize] &&
sched_pusch->tb_size < B); sched_pusch->tb_size < B);
LOG_D(NR_MAC,"rbSize %d, TBS %d, est buf %d, sched_ul %d, B %d\n", // LOG_I(NR_MAC,"rbSize %d, TBS %d, est buf %d, sched_ul %d, B %d, frame %d, slot %d\n",
rbSize, sched_pusch->tb_size, sched_ctrl->estimated_ul_buffer, sched_ctrl->sched_ul_bytes, B); // rbSize, sched_pusch->tb_size, sched_ctrl->estimated_ul_buffer, sched_ctrl->sched_ul_bytes, B, frame, slot);
/* Mark the corresponding RBs as used */ /* Mark the corresponding RBs as used */
n_rb_sched -= sched_pusch->rbSize; n_rb_sched -= sched_pusch->rbSize;
......
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
View file @ ee45cf21
...@@ -67,7 +67,7 @@ gNBs = ...@@ -67,7 +67,7 @@ gNBs =
#initialDownlinkBWP #initialDownlinkBWP
#genericParameters #genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart # this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 12952; # 6366 12925 12956 28875 12952 initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing # subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1; initialDLBWPsubcarrierSpacing = 1;
...@@ -110,7 +110,7 @@ gNBs = ...@@ -110,7 +110,7 @@ gNBs =
pMax = 20; pMax = 20;
#initialUplinkBWP #initialUplinkBWP
#genericParameters #genericParameters
initialULBWPlocationAndBandwidth = 12952; initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing # subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1; initialULBWPsubcarrierSpacing = 1;
......
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