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wangjie
OpenXG-RAN
Commits
f67cc264
Commit
f67cc264
authored
Nov 23, 2020
by
Robert Schmidt
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Rename NR_sched_pusch_t and use for Freq Alloc + MCS
parent
9c0ef2e5
Changes
3
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3 changed files
with
21 additions
and
15 deletions
+21
-15
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+1
-5
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+11
-8
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+9
-2
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
f67cc264
...
@@ -1788,17 +1788,13 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
...
@@ -1788,17 +1788,13 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
=
(
NR_sched_pucch
**
)
malloc
(
num_slots_ul
*
sizeof
(
NR_sched_pucch
*
));
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
=
(
NR_sched_pucch
**
)
malloc
(
num_slots_ul
*
sizeof
(
NR_sched_pucch
*
));
for
(
int
s
=
0
;
s
<
num_slots_ul
;
s
++
)
for
(
int
s
=
0
;
s
<
num_slots_ul
;
s
++
)
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
s
]
=
(
NR_sched_pucch
*
)
malloc
(
2
*
sizeof
(
NR_sched_pucch
));
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
s
]
=
(
NR_sched_pucch
*
)
malloc
(
2
*
sizeof
(
NR_sched_pucch
));
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pusch
=
(
NR_sched_pusch
*
)
malloc
(
num_slots_ul
*
sizeof
(
NR_sched_pusch
));
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pusch
=
calloc
(
num_slots_ul
,
sizeof
(
NR_sched_pusch_t
));
for
(
int
k
=
0
;
k
<
num_slots_ul
;
k
++
)
{
for
(
int
k
=
0
;
k
<
num_slots_ul
;
k
++
)
{
for
(
int
l
=
0
;
l
<
2
;
l
++
)
for
(
int
l
=
0
;
l
<
2
;
l
++
)
memset
((
void
*
)
&
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
k
][
l
],
memset
((
void
*
)
&
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
k
][
l
],
0
,
0
,
sizeof
(
NR_sched_pucch
));
sizeof
(
NR_sched_pucch
));
memset
((
void
*
)
&
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pusch
[
k
],
0
,
sizeof
(
NR_sched_pusch
));
}
}
LOG_I
(
MAC
,
"gNB %d] Add NR UE_id %d : rnti %x
\n
"
,
LOG_I
(
MAC
,
"gNB %d] Add NR UE_id %d : rnti %x
\n
"
,
mod_idP
,
mod_idP
,
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
f67cc264
...
@@ -501,6 +501,11 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
...
@@ -501,6 +501,11 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
return
;
return
;
}
}
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
]
++
;
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
]
++
;
sched_ctrl
->
sched_pusch
->
mcs
=
9
;
sched_ctrl
->
sched_pusch
->
rbStart
=
0
;
sched_ctrl
->
sched_pusch
->
rbSize
=
get_softmodem_params
()
->
phy_test
?
50
:
NRRIV2BW
(
sched_ctrl
->
active_ubwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
}
}
void
nr_schedule_ulsch
(
module_id_t
module_id
,
void
nr_schedule_ulsch
(
module_id_t
module_id
,
...
@@ -539,11 +544,6 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -539,11 +544,6 @@ void nr_schedule_ulsch(module_id_t module_id,
if
(
is_xlsch_in_slot
(
ulsch_in_slot_bitmap
,
sched_slot
)
if
(
is_xlsch_in_slot
(
ulsch_in_slot_bitmap
,
sched_slot
)
&&
(
!
get_softmodem_params
()
->
phy_test
||
sched_slot
==
8
))
{
&&
(
!
get_softmodem_params
()
->
phy_test
||
sched_slot
==
8
))
{
const
uint8_t
mcs
=
9
;
const
uint16_t
rbStart
=
0
;
const
uint16_t
rbSize
=
get_softmodem_params
()
->
phy_test
?
50
:
NRRIV2BW
(
sched_ctrl
->
active_ubwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
nfapi_nr_ul_dci_request_t
*
UL_dci_req
=
&
RC
.
nrmac
[
module_id
]
->
UL_dci_req
[
0
];
nfapi_nr_ul_dci_request_t
*
UL_dci_req
=
&
RC
.
nrmac
[
module_id
]
->
UL_dci_req
[
0
];
UL_dci_req
->
SFN
=
frame
;
UL_dci_req
->
SFN
=
frame
;
UL_dci_req
->
Slot
=
slot
;
UL_dci_req
->
Slot
=
slot
;
...
@@ -607,7 +607,7 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -607,7 +607,7 @@ void nr_schedule_ulsch(module_id_t module_id,
else
else
pusch_pdu
->
data_scrambling_id
=
*
scc
->
physCellId
;
pusch_pdu
->
data_scrambling_id
=
*
scc
->
physCellId
;
pusch_pdu
->
mcs_index
=
mcs
;
pusch_pdu
->
mcs_index
=
sched_ctrl
->
sched_pusch
->
mcs
;
const
int
target_ss
=
NR_SearchSpace__searchSpaceType_PR_ue_Specific
;
const
int
target_ss
=
NR_SearchSpace__searchSpaceType_PR_ue_Specific
;
if
(
pusch_pdu
->
transform_precoding
)
if
(
pusch_pdu
->
transform_precoding
)
pusch_pdu
->
mcs_table
=
get_pusch_mcs_table
(
pusch_Config
->
mcs_Table
,
pusch_pdu
->
mcs_table
=
get_pusch_mcs_table
(
pusch_Config
->
mcs_Table
,
...
@@ -640,8 +640,8 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -640,8 +640,8 @@ void nr_schedule_ulsch(module_id_t module_id,
AssertFatal
(
pusch_Config
->
resourceAllocation
==
NR_PUSCH_Config__resourceAllocation_resourceAllocationType1
,
AssertFatal
(
pusch_Config
->
resourceAllocation
==
NR_PUSCH_Config__resourceAllocation_resourceAllocationType1
,
"Only frequency resource allocation type 1 is currently supported
\n
"
);
"Only frequency resource allocation type 1 is currently supported
\n
"
);
pusch_pdu
->
resource_alloc
=
1
;
//type 1
pusch_pdu
->
resource_alloc
=
1
;
//type 1
pusch_pdu
->
rb_start
=
rbStart
;
pusch_pdu
->
rb_start
=
sched_ctrl
->
sched_pusch
->
rbStart
;
pusch_pdu
->
rb_size
=
rbSize
;
pusch_pdu
->
rb_size
=
sched_ctrl
->
sched_pusch
->
rbSize
;
pusch_pdu
->
vrb_to_prb_mapping
=
0
;
pusch_pdu
->
vrb_to_prb_mapping
=
0
;
if
(
pusch_Config
->
frequencyHopping
==
NULL
)
if
(
pusch_Config
->
frequencyHopping
==
NULL
)
...
@@ -786,5 +786,8 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -786,5 +786,8 @@ void nr_schedule_ulsch(module_id_t module_id,
const
int
n_ubwp
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
uplinkBWP_ToAddModList
->
list
.
count
;
const
int
n_ubwp
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
uplinkBWP_ToAddModList
->
list
.
count
;
config_uldci
(
sched_ctrl
->
active_ubwp
,
pusch_pdu
,
pdcch_pdu_rel15
,
&
dci_pdu_rel15
[
0
],
dci_formats
,
rnti_types
,
tda
,
UE_info
->
UE_sched_ctrl
[
UE_id
].
tpc0
,
n_ubwp
,
sched_ctrl
->
active_bwp
->
bwp_Id
);
config_uldci
(
sched_ctrl
->
active_ubwp
,
pusch_pdu
,
pdcch_pdu_rel15
,
&
dci_pdu_rel15
[
0
],
dci_formats
,
rnti_types
,
tda
,
UE_info
->
UE_sched_ctrl
[
UE_id
].
tpc0
,
n_ubwp
,
sched_ctrl
->
active_bwp
->
bwp_Id
);
fill_dci_pdu_rel15
(
scc
,
secondaryCellGroup
,
pdcch_pdu_rel15
,
dci_pdu_rel15
,
dci_formats
,
rnti_types
,
pusch_pdu
->
bwp_size
,
sched_ctrl
->
active_bwp
->
bwp_Id
);
fill_dci_pdu_rel15
(
scc
,
secondaryCellGroup
,
pdcch_pdu_rel15
,
dci_pdu_rel15
,
dci_formats
,
rnti_types
,
pusch_pdu
->
bwp_size
,
sched_ctrl
->
active_bwp
->
bwp_Id
);
sched_ctrl
->
sched_pusch
->
rbSize
=
0
;
}
}
}
}
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @
f67cc264
...
@@ -290,7 +290,14 @@ typedef struct NR_sched_pusch {
...
@@ -290,7 +290,14 @@ typedef struct NR_sched_pusch {
int
slot
;
int
slot
;
bool
active
;
bool
active
;
nfapi_nr_pusch_pdu_t
pusch_pdu
;
nfapi_nr_pusch_pdu_t
pusch_pdu
;
}
NR_sched_pusch
;
/// RB allocation within active uBWP
uint16_t
rbSize
;
uint16_t
rbStart
;
/// MCS
uint8_t
mcs
;
}
NR_sched_pusch_t
;
typedef
struct
NR_UE_harq
{
typedef
struct
NR_UE_harq
{
uint8_t
is_waiting
;
uint8_t
is_waiting
;
...
@@ -355,7 +362,7 @@ typedef struct {
...
@@ -355,7 +362,7 @@ typedef struct {
/// selected PUCCH index, if scheduled
/// selected PUCCH index, if scheduled
int
pucch_sched_idx
;
int
pucch_sched_idx
;
int
pucch_occ_idx
;
int
pucch_occ_idx
;
NR_sched_pusch
*
sched_pusch
;
NR_sched_pusch
_t
*
sched_pusch
;
/// CCE index and aggregation, should be coherent with cce_list
/// CCE index and aggregation, should be coherent with cce_list
NR_SearchSpace_t
*
search_space
;
NR_SearchSpace_t
*
search_space
;
...
...
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