Linux and DPDK Drivers 2020.1 Patch Release

Resolved HW errors observed with QDMA4.0 MM only design

QDMA/DPDK/RELEASE

-RELEASE: 2020.1
-===============
+RELEASE: 2020.1 Patch
+=====================
 
-This release is based on DPDK v19.11 in IOVA=PA mode and contains QDMA poll mode driver and
-QDMA test application. This release is validated on QDMA4.0 2020.1 based example design
-and QDMA3.1 2019.2 patch based example design.
+This release is based on DPDK v19.11 and contains QDMA poll mode driver and
+QDMA test application. This release is validated on QDMA4.0 2020.1 Patch based
+example design.
 
 This release includes a patch file for dpdk-pktgen v19.12.0 that extends
 dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes
@@ -60,7 +60,7 @@ SUPPORTED FEATURES:
 	- Fix memory offset calculation in dma_from_device and dma_to_device command in qdma_testapp application for MM mode
 
 2020.1 Updates
----------------
+--------------
 - Support DPDK v19.11 LTS
 - Support QDMA4.0 context and register changes
 - Common driver to support QDMA3.1 and QDMA4.0 designs
@@ -69,14 +69,18 @@ SUPPORTED FEATURES:
 - Support multiple bus numbers on single card
 - CPU resource optimization in Tx and Rx data path
 
+2020.1 Patch Updates
+--------------------
+- Resolved HW errors observed with QDMA4.0 MM only design
+- Verified QDMA DPDK software with IOVA=VA mode by enabling hugepage allocation matching support in DPDK
+  (i.e. by specifying the --match-allocations command-line switch to the EAL).
+
 KNOWN ISSUES:
 =============
-- On QDMA3.1 2019.2 design, sometimes completions are not received when C2H PIDX updates are held for 64 descriptors
-- On QDMA4.0 2020.1 design, HW errors are observed in dmesg console while validating the MM only design.
 - Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
+- DPDK C2H and Forwarding performance values for 8 queue is lesser compared to 4 queue case for both PF and VF.
 
 DRIVER LIMITATIONS:
 ===================
 - Big endian systems are not supported
-- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
-- QDMA DPDK 2020.1 software is verified with IOVA=PA mode only
\ No newline at end of file
+- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
\ No newline at end of file

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_access_common.h"
@@ -4372,6 +4384,25 @@ int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf,
 	return QDMA_SUCCESS;
 }
 
+/*****************************************************************************/
+/**
+ * eqdma_hw_get_error_name() - Function to get the error in string format
+ *
+ * @err_idx: error index
+ *
+ * Return: string - success and NULL on failure
+ *****************************************************************************/
+const char *eqdma_hw_get_error_name(uint32_t err_idx)
+{
+	if (err_idx >= EQDMA_ERRS_ALL) {
+		qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n",
+				__func__, (enum eqdma_error_idx)err_idx);
+		return NULL;
+	}
+
+	return eqdma_err_info[(enum eqdma_error_idx)err_idx].err_name;
+}
+
 /*****************************************************************************/
 /**
  * eqdma_hw_error_process() - Function to find the error that got
@@ -4444,21 +4475,85 @@ int eqdma_hw_error_process(void *dev_hndl)
 
 /*****************************************************************************/
 /**
- * eqdma_hw_get_error_name() - Function to get the error in string format
+ * qdma_hw_error_enable() - Function to enable all or a specific error
  *
+ * @dev_hndl: device handle
  * @err_idx: error index
  *
- * Return: string - success and NULL on failure
+ * Return:	0   - success and < 0 - failure
  *****************************************************************************/
-const char *eqdma_hw_get_error_name(enum qdma_error_idx err_idx)
+int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx)
 {
-	if ((enum eqdma_error_idx)err_idx >= EQDMA_ERRS_ALL) {
-		qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n",
-				__func__, (enum eqdma_error_idx)err_idx);
-		return NULL;
+	uint32_t idx = 0, i = 0;
+	uint32_t reg_val = 0;
+	struct qdma_dev_attributes *dev_cap;
+
+	if (!dev_hndl) {
+		qdma_log_error("%s: dev_handle is NULL, err:%d\n",
+				__func__, -QDMA_ERR_INV_PARAM);
+		return -QDMA_ERR_INV_PARAM;
 	}
 
-	return eqdma_err_info[(enum eqdma_error_idx)err_idx].err_name;
+	if (err_idx > EQDMA_ERRS_ALL) {
+		qdma_log_error("%s: err_idx=%d is invalid, err:%d\n",
+				__func__, (enum eqdma_error_idx)err_idx,
+				-QDMA_ERR_INV_PARAM);
+		return -QDMA_ERR_INV_PARAM;
+	}
+
+	qdma_get_device_attr(dev_hndl, &dev_cap);
+
+	if (err_idx == EQDMA_ERRS_ALL) {
+		for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) {
+
+			idx = all_eqdma_hw_errs[i];
+
+			/* Don't access streaming registers in
+			 * MM only bitstreams
+			 */
+			if (!dev_cap->st_en) {
+				if (idx == EQDMA_ST_C2H_ERR_ALL ||
+					idx == EQDMA_ST_FATAL_ERR_ALL ||
+					idx == EQDMA_ST_H2C_ERR_ALL)
+					continue;
+			}
+
+			reg_val = eqdma_err_info[idx].leaf_err_mask;
+			qdma_reg_write(dev_hndl,
+				eqdma_err_info[idx].mask_reg_addr, reg_val);
+
+			reg_val = qdma_reg_read(dev_hndl,
+					EQDMA_OFFSET_GLBL_ERR_MASK);
+			reg_val |= FIELD_SET(
+				eqdma_err_info[idx].global_err_mask, 1);
+			qdma_reg_write(dev_hndl, EQDMA_OFFSET_GLBL_ERR_MASK,
+					reg_val);
+		}
+
+	} else {
+		/* Don't access streaming registers in MM only bitstreams
+		 *  QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all
+		 *  ST errors
+		 */
+		if (!dev_cap->st_en) {
+			if (err_idx >= EQDMA_ST_C2H_ERR_MTY_MISMATCH &&
+					err_idx <= EQDMA_ST_H2C_ERR_ALL)
+				return QDMA_SUCCESS;
+		}
+
+		reg_val = qdma_reg_read(dev_hndl,
+				eqdma_err_info[err_idx].mask_reg_addr);
+		reg_val |= FIELD_SET(eqdma_err_info[err_idx].leaf_err_mask, 1);
+		qdma_reg_write(dev_hndl,
+				eqdma_err_info[err_idx].mask_reg_addr, reg_val);
+
+		reg_val = qdma_reg_read(dev_hndl, EQDMA_OFFSET_GLBL_ERR_MASK);
+		reg_val |=
+			FIELD_SET(eqdma_err_info[err_idx].global_err_mask, 1);
+		qdma_reg_write(dev_hndl, EQDMA_OFFSET_GLBL_ERR_MASK, reg_val);
+	}
+
+	return QDMA_SUCCESS;
 }
 
 /*****************************************************************************/

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef EQDMA_ACCESS_H_
@@ -231,7 +243,8 @@ int eqdma_context_buf_len(uint8_t st,
 		enum qdma_dev_q_type q_type, uint32_t *buflen);
 
 int eqdma_hw_error_process(void *dev_hndl);
-const char *eqdma_hw_get_error_name(enum qdma_error_idx err_idx);
+const char *eqdma_hw_get_error_name(uint32_t err_idx);
+int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx);
 
 int eqdma_read_dump_queue_context(void *dev_hndl,
 		uint16_t qid_hw,

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef EQDMA_SOFT_REG_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_access_common.h"
@@ -1691,6 +1703,7 @@ int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf,
 				&eqdma_indirect_intr_ctx_conf;
 		hw_access->qdma_dump_config_regs = &eqdma_dump_config_regs;
 		hw_access->qdma_dump_intr_context = &eqdma_dump_intr_context;
+		hw_access->qdma_hw_error_enable = &eqdma_hw_error_enable;
 		hw_access->qdma_hw_error_process = &eqdma_hw_error_process;
 		hw_access->qdma_hw_get_error_name = &eqdma_hw_get_error_name;
 		hw_access->qdma_hw_ctx_conf = &eqdma_hw_ctx_conf;

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_ACCESS_COMMON_H_
@@ -575,8 +587,8 @@ struct qdma_hw_access {
 					uint8_t err_intr_index);
 	int (*qdma_hw_error_intr_rearm)(void *dev_hndl);
 	int (*qdma_hw_error_enable)(void *dev_hndl,
-					enum qdma_error_idx err_idx);
-	const char *(*qdma_hw_get_error_name)(enum qdma_error_idx err_idx);
+			uint32_t err_idx);
+	const char *(*qdma_hw_get_error_name)(uint32_t err_idx);
 	int (*qdma_hw_error_process)(void *dev_hndl);
 	int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf,
 					uint32_t buflen);

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_ACCESS_ERRORS_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_ACCESS_EXPORT_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_VERSION_H_
@@ -8,7 +20,7 @@
 
 #define QDMA_VERSION_MAJOR	2020
 #define QDMA_VERSION_MINOR	1
-#define QDMA_VERSION_PATCH	0
+#define QDMA_VERSION_PATCH	1
 
 #define QDMA_VERSION_STR	\
 	__stringify(QDMA_VERSION_MAJOR) "." \

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm_access.h

-/*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef QDMA_CPM_ACCESS_H_
-#define QDMA_CPM_ACCESS_H_
-
-#include "qdma_access.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int qdma_cpm_init_ctxt_memory(void *dev_hndl);
-
-int qdma_cpm_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
-			 struct qdma_qid2vec *ctxt,
-			 enum qdma_hw_access_type access_type);
-
-int qdma_cpm_fmap_conf(void *dev_hndl, uint16_t func_id,
-			struct qdma_fmap_cfg *config,
-			enum qdma_hw_access_type access_type);
-
-int qdma_cpm_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
-				struct qdma_descq_sw_ctxt *ctxt,
-				enum qdma_hw_access_type access_type);
-
-int qdma_cpm_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid,
-				struct qdma_descq_prefetch_ctxt *ctxt,
-				enum qdma_hw_access_type access_type);
-
-int qdma_cpm_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid,
-			struct qdma_descq_cmpt_ctxt *ctxt,
-			enum qdma_hw_access_type access_type);
-
-int qdma_cpm_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
-				struct qdma_descq_hw_ctxt *ctxt,
-				enum qdma_hw_access_type access_type);
-
-int qdma_cpm_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
-			struct qdma_descq_credit_ctxt *ctxt,
-			enum qdma_hw_access_type access_type);
-
-int qdma_cpm_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index,
-				struct qdma_indirect_intr_ctxt *ctxt,
-				enum qdma_hw_access_type access_type);
-
-int qdma_cpm_set_default_global_csr(void *dev_hndl);
-
-int qdma_cpm_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
-		uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info);
-
-int qdma_cpm_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
-		const struct qdma_q_cmpt_cidx_reg_info *reg_info);
-
-int qdma_cpm_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
-		const struct qdma_intr_cidx_reg_info *reg_info);
-
-int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, uint8_t *user_bar);
-
-int qdma_cpm_get_device_attributes(void *dev_hndl,
-		struct qdma_dev_attributes *dev_info);
-
-int qdma_cpm_dump_config_regs(void *dev_hndl, uint8_t is_vf,
-		char *buf, uint32_t buflen);
-
-int qdma_cpm_dump_queue_context(void *dev_hndl, uint16_t hw_qid, uint8_t st,
-	uint8_t c2h, char *buf, uint32_t buflen);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* QDMA_CPM_ACCESS_H_ */

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm_reg.h

-/*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef QDMA_CPM_REG_H_
-#define QDMA_CPM_REG_H_
-
-#include "qdma_reg.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* ------------------------- QDMA_TRQ_SEL_IND (0x00800) ----------------*/
-#define QDMA_CPM_OFFSET_IND_CTXT_MASK				0x814
-#define QDMA_CPM_OFFSET_IND_CTXT_CMD				0x824
-
-
-/* ------------------------ indirect register context fields -----------*/
-
-#define QDMA_CPM_IND_CTXT_DATA_NUM_REGS				4
-/** QDMA_IND_REG_SEL_FMAP */
-#define QDMA_CPM_FMAP_CTXT_W0_QID_MAX_MASK			GENMASK(22, 11)
-
-/** QDMA_IND_REG_SEL_SW_C2H */
-/** QDMA_IND_REG_SEL_SW_H2C */
-#define QDMA_CPM_SW_CTXT_W1_FUNC_ID_MASK			GENMASK(11, 4)
-
-/** QDMA_IND_REG_SEL_CMPT */
-#define QDMA_CPM_COMPL_CTXT_BADDR_GET_H_MASK		GENMASK_ULL(63, 42)
-#define QDMA_CPM_COMPL_CTXT_BADDR_GET_M_MASK		GENMASK_ULL(41, 10)
-#define QDMA_CPM_COMPL_CTXT_BADDR_GET_L_MASK		GENMASK_ULL(9, 6)
-
-#define QDMA_CPM_COMPL_CTXT_W3_FULL_UPDT_MASK                   BIT(29)
-#define QDMA_CPM_COMPL_CTXT_W3_TMR_RUN_MASK                     BIT(28)
-#define QDMA_CPM_COMPL_CTXT_W3_USR_TRG_PND_MASK                 BIT(27)
-#define QDMA_CPM_COMPL_CTXT_W3_ERR_MASK                         GENMASK(26, 25)
-#define QDMA_CPM_COMPL_CTXT_W3_VALID_MASK                       BIT(24)
-#define QDMA_CPM_COMPL_CTXT_W3_CIDX_MASK                        GENMASK(23, 8)
-#define QDMA_CPM_COMPL_CTXT_W3_PIDX_H_MASK                      GENMASK(7, 0)
-#define QDMA_CPM_COMPL_CTXT_W2_PIDX_L_MASK                      GENMASK(31, 24)
-#define QDMA_CPM_COMPL_CTXT_W2_DESC_SIZE_MASK                   GENMASK(23, 22)
-#define QDMA_CPM_COMPL_CTXT_W2_BADDR_64_H_MASK                  GENMASK(21, 0)
-#define QDMA_CPM_COMPL_CTXT_W1_BADDR_64_M_MASK                  GENMASK(31, 0)
-#define QDMA_CPM_COMPL_CTXT_W0_BADDR_64_L_MASK                  GENMASK(31, 28)
-#define QDMA_CPM_COMPL_CTXT_W0_RING_SZ_MASK                     GENMASK(27, 24)
-#define QDMA_CPM_COMPL_CTXT_W0_COLOR_MASK                       BIT(23)
-#define QDMA_CPM_COMPL_CTXT_W0_INT_ST_MASK                      GENMASK(22, 21)
-#define QDMA_CPM_COMPL_CTXT_W0_TIMER_IDX_MASK                   GENMASK(20, 17)
-#define QDMA_CPM_COMPL_CTXT_W0_COUNTER_IDX_MASK                 GENMASK(16, 13)
-
-/** QDMA_IND_REG_SEL_HW_C2H */
-/** QDMA_IND_REG_SEL_HW_H2C */
-#define QDMA_CPM_HW_CTXT_W1_FETCH_PEND_MASK                     BIT(10)
-
-/** QDMA_IND_REG_SEL_CR_C2H */
-/** QDMA_IND_REG_SEL_CR_H2C */
-#define QDMA_CPM_CR_CTXT_W0_CREDT_MASK                          GENMASK(15, 0)
-
-/** QDMA_IND_REG_SEL_INTR */
-#define QDMA_CPM_INTR_CTXT_BADDR_GET_H_MASK		GENMASK_ULL(63, 35)
-#define QDMA_CPM_INTR_CTXT_BADDR_GET_L_MASK		GENMASK_ULL(34, 12)
-
-#define QDMA_CPM_INTR_CTXT_W2_PIDX_MASK			GENMASK(11, 0)
-#define QDMA_CPM_INTR_CTXT_W1_PAGE_SIZE_MASK	GENMASK(31, 29)
-#define QDMA_CPM_INTR_CTXT_W1_BADDR_64_MASK		GENMASK(28, 0)
-#define QDMA_CPM_INTR_CTXT_W0_BADDR_64_MASK		GENMASK(31, 9)
-#define QDMA_CPM_INTR_CTXT_W0_COLOR_MASK		BIT(8)
-#define QDMA_CPM_INTR_CTXT_W0_INT_ST_MASK		BIT(7)
-#define QDMA_CPM_INTR_CTXT_W0_VEC_ID_MASK		GENMASK(5, 1)
-
-
-/*---------------------------------------------------------------------*/
-/*
- * Function registers
- */
-
-#define		QDMA_CPM_REG_TRQ_SEL_FMAP_BASE		0x400
-#define		QDMA_CPM_REG_TRQ_SEL_FMAP_STEP		4
-#define		QDMA_CPM_REG_TRQ_SEL_FMAP_COUNT		256
-
-#define		SEL_FMAP_QID_BASE_SHIFT			0
-#define		SEL_FMAP_QID_BASE_MASK			0x7FFU
-#define		SEL_FMAP_QID_MAX_SHIFT			11
-#define		SEL_FMAP_QID_MAX_MASK			0xFFFU
-
-#define		QDMA_CPM_REG_C2H_QID2VEC_MAP_QID	0xa80
-#define		QDMA_CPM_QID2VEC_C2H_VECTOR		GENMASK(7, 0)
-#define		QDMA_CPM_QID2VEC_C2H_COAL_EN		BIT(8)
-#define		QDMA_CPM_QID2VEC_H2C_VECTOR		GENMASK(16, 9)
-#define		QDMA_CPM_QID2VEC_H2C_COAL_EN		BIT(17)
-
-#define QDMA_CPM_REG_C2H_QID2VEC_MAP			0xa84
-/*---------------------------------------------------------------------*/
-
-
-
-
-/* ------------------------- QDMA_TRQ_SEL_QUEUE_PF (0x18000) ----------------*/
-
-#define QDMA_CPM_OFFSET_DMAP_SEL_INT_CIDX                       0x6400
-#define QDMA_CPM_OFFSET_DMAP_SEL_H2C_DSC_PIDX                   0x6404
-#define QDMA_CPM_OFFSET_DMAP_SEL_C2H_DSC_PIDX                   0x6408
-#define QDMA_CPM_OFFSET_DMAP_SEL_CMPT_CIDX                      0x640C
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* QDMA_CPM_REG_H_ */

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_list.h"

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_LIST_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_mbox_protocol.h"

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_MBOX_PROTOCOL_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef LIBQDMA_QDMA_PLATFORM_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef __QDMA_REG_DUMP_H__

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_resource_mgmt.h"

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_RESOURCE_MGMT_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #include "qdma_access_common.h"

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_S80_HARD_ACCESS_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h

 /*
  * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
  */
 
 #ifndef QDMA_S80_HARD_REG_H_