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Commit a532a12c authored by Ruhung's avatar Ruhung Committed by GitHub
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riscv64: Fallback to autovec without mrvv-vector-bits flag. (#1282)

parent 85632ca8
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Showing with 2 additions and 2 deletions
simde-common.h
View file @ a532a12c
...@@ -1200,7 +1200,7 @@ HEDLEY_DIAGNOSTIC_POP ...@@ -1200,7 +1200,7 @@ HEDLEY_DIAGNOSTIC_POP
#endif #endif
/* Initial support for RISCV V extensions based on ZVE64D. */ /* Initial support for RISCV V extensions based on ZVE64D. */
#if defined(SIMDE_ARCH_RISCV_ZVE64D) && SIMDE_NATURAL_VECTOR_SIZE >= 64 #if defined(SIMDE_ARCH_RISCV_ZVE64D) && SIMDE_NATURAL_VECTOR_SIZE >= 64 && defined(__riscv_v_fixed_vlen)
#define RVV_FIXED_TYPE_DEF(name, lmul) \ #define RVV_FIXED_TYPE_DEF(name, lmul) \
typedef vint8##name##_t fixed_vint8##name##_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul))); \ typedef vint8##name##_t fixed_vint8##name##_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul))); \
typedef vint16##name##_t fixed_vint16##name##_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul))); \ typedef vint16##name##_t fixed_vint16##name##_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul))); \
......
simde-features.h
View file @ a532a12c
...@@ -380,7 +380,7 @@ ...@@ -380,7 +380,7 @@
#endif #endif
#if !defined(SIMDE_RISCV_V_NATIVE) && !defined(SIMDE_RISCV_V_NO_NATIVE) && !defined(SIMDE_NO_NATIVE) #if !defined(SIMDE_RISCV_V_NATIVE) && !defined(SIMDE_RISCV_V_NO_NATIVE) && !defined(SIMDE_NO_NATIVE)
#if defined(SIMDE_ARCH_RISCV_V) #if defined(SIMDE_ARCH_RISCV_V) && defined(__riscv_v_fixed_vlen)
#define SIMDE_RISCV_V_NATIVE #define SIMDE_RISCV_V_NATIVE
#endif #endif
#endif #endif
......
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