Add defines for AVX512VBMI to simde-arch.h and simde-features.h

warning C4701: potentially uninitialized local variable 'r_' used

Fixes #654

XL C/C++ supports __builtin_shufflevector, but only when using AltiVec
types, not on GCC-style vector extensions.  We could add alternate
implementations which use the same code but (for example) altivec_f32
instead of f32, but that introduces a lot of bloat into the code for
a compiler very few use *and* rewards IBM for a stupid decision which
breaks compatibility with *lots* of code.

vec_nand needs POWER8.

vec_andc needs P7 for int64x2 vectors but P6 is sufficient for int8x16
vectors.

-Wshift-negative-value is inculded with -Wextra.

In the process simplify the algorithm which generates the affine
matrix.

The Intel Intrinsics Guide shows these as SSE not SSE2, but that
doesn't really make sense since they use __m128i not __m128, and
__m128i wasn't introduced until SSE2.  At the assembly level it
does make sense, though.

This also adds a simde_x_mm_cvtsi16_si128 and simde_x_mm_cvtsi128_si16
to make implementing the load functions easier..

Fixes #650.

Fixes #642

Fixes #640

Some of these were likely disabled by accident, but others were on
purpose to avoid bugs or missing implementations.  Some have been
removed altogether.

These were causing ICEs prior to clang-12 on POWER9 when compiled
without optimizitaion.  Here is a trivial reproducer:

  typedef short i16x4 __attribute__((__vector_size__(8)));

  i16x4 shr(i16x4 v, long n) {
    return v >> n;
  }

AFAICT the problem has been fixed in clang-12, though I haven't
bothered to track down a bug report, git commit, phabricator review,
etc. so no SIMDE_BUG_* macro.

It's still in develepment, so this may have to change down the road,
but for now it works.

With -mfpu=neon, GCC won't enable the A32 functionality, only armv7.
The least unreasonable way to detect whether the functions are
available is to check for support for 16-bit floats.

This just fixes many instances of extra whitespace at the beginning of
the line.  No other changes.

Previously _MM_FROUND_TO_NEAREST_INT used round/roundf, which rounds
ties away from zero instead of toward even like it should have.

For details, see
<https://wunkolo.github.io/post/2020/11/gf2p8affineqb-int8-shifting/>.
This is a bit faster than the other implementations; for example, see
<https://godbolt.org/z/96a9ov>.

On Tremont, Intel supports 128-bit GFNI functions even though the CPU
does not support AVX-512.

According to the latest SDM (the IIG hasn't been updated), only GFNI is
required for the legacy encoded instructions.  AVX is required for
VEX encoded instructions, and AVX-512 is required for EVEX.

Basically, that maps to GFNI for 128-bit functions, AVX for 256 bit
functions, and AVX-512F for 512-bit functions, with the added caveat
that the mask/maskz functions on 128/256-bit vectors require AVX-512VL.

This is based on a question I asked on Intel's forums at:
https://community.intel.com/t5/Intel-ISA-Extensions/Requirements-for-GFNI-without-AVX-AVX-512/m-p/1228325/thread-id/6852#M6853
The relevant bits of the SDM are volume 2A, 3-442, 3-445, and 3-447.

Correct _mm_max_ps to _mm_max_pd in maxnm.h
Correct _mm_min_ps to _mm_min_pd in minnm.h

Fixes #639

There was a missing closing parenthesis.  It wasn't caught before
since we prefer the vector extension version, and most compilers
which support NEON also support vector extensions.

Cray doesn't support __builtin_assume_aligned.  This isn't quite
enough to get craycc working since we also need some changes in
Hedley which I'm working on.

It's 64-bit floats, we need to use _mm_max_pd not _mm_max_ps.

Fixes #636

Fixes #635