Commit f25dc4e7 authored by Florian Kaltenberger's avatar Florian Kaltenberger

usrp_lib: setting master clock rate to 30.72 and filter to 20MHz for all cases...

usrp_lib: setting master clock rate to 30.72 and filter to 20MHz for all cases to improve noise figure and channel response
parent 87810c27
...@@ -597,9 +597,10 @@ extern "C" { ...@@ -597,9 +597,10 @@ extern "C" {
openair0_cfg[0].rx_gain_calib_table = calib_table_b210_38; openair0_cfg[0].rx_gain_calib_table = calib_table_b210_38;
bw_gain_adjust=1; bw_gain_adjust=1;
} }
s->usrp->set_master_clock_rate(30.72e6);
switch ((int)openair0_cfg[0].sample_rate) { switch ((int)openair0_cfg[0].sample_rate) {
case 30720000: case 30720000:
s->usrp->set_master_clock_rate(30.72e6);
// from usrp_time_offset // from usrp_time_offset
openair0_cfg[0].samples_per_packet = 4096; openair0_cfg[0].samples_per_packet = 4096;
openair0_cfg[0].tx_sample_advance = 115; openair0_cfg[0].tx_sample_advance = 115;
...@@ -608,7 +609,6 @@ extern "C" { ...@@ -608,7 +609,6 @@ extern "C" {
openair0_cfg[0].tx_scheduling_advance = 11*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 11*openair0_cfg[0].samples_per_packet;
break; break;
case 23040000: case 23040000:
s->usrp->set_master_clock_rate(46.08e6);
openair0_cfg[0].samples_per_packet = 2048; openair0_cfg[0].samples_per_packet = 2048;
openair0_cfg[0].tx_sample_advance = 113; openair0_cfg[0].tx_sample_advance = 113;
openair0_cfg[0].tx_bw = 20e6; openair0_cfg[0].tx_bw = 20e6;
...@@ -616,27 +616,24 @@ extern "C" { ...@@ -616,27 +616,24 @@ extern "C" {
openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet;
break; break;
case 15360000: case 15360000:
s->usrp->set_master_clock_rate(30.72e6);
openair0_cfg[0].samples_per_packet = 2048; openair0_cfg[0].samples_per_packet = 2048;
openair0_cfg[0].tx_sample_advance = 113; openair0_cfg[0].tx_sample_advance = 113;
openair0_cfg[0].tx_bw = 10e6; openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 10e6; openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet;
break; break;
case 7680000: case 7680000:
s->usrp->set_master_clock_rate(30.72e6);
openair0_cfg[0].samples_per_packet = 1024; openair0_cfg[0].samples_per_packet = 1024;
openair0_cfg[0].tx_sample_advance = 70;//103; openair0_cfg[0].tx_sample_advance = 70;//103;
openair0_cfg[0].tx_bw = 5e6; openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 5e6; openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet;
break; break;
case 1920000: case 1920000:
s->usrp->set_master_clock_rate(30.72e6);
openair0_cfg[0].samples_per_packet = 256; openair0_cfg[0].samples_per_packet = 256;
openair0_cfg[0].tx_sample_advance = 40; openair0_cfg[0].tx_sample_advance = 40;
openair0_cfg[0].tx_bw = 1.25e6; openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 1.25e6; openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet;
break; break;
default: default:
......
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