Commit 9a7154f3 authored by Robert Schmidt's avatar Robert Schmidt

Merge remote-tracking branch 'origin/fairRR-sched-debug' into integration_2022_wk07_c

parents cfa3b0ca 11d80b93
...@@ -601,7 +601,8 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, ...@@ -601,7 +601,8 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
G = G - Q_RI - Q_CQI; G = G - Q_RI - Q_CQI;
ulsch_harq->G = G; ulsch_harq->G = G;
AssertFatal((int)G > 0, AssertFatal((int)G > 0,
"FATAL: ulsch_decoding.c G < 0 (%u) : Q_RI %u, Q_CQI %u\n",G,Q_RI,Q_CQI); "FATAL: ulsch_decoding.c G < 0 (%u) : Q_RI %u, Q_CQI %u, nb_rb %u, Q_m %u, ulsch_harq->Nsymb_pusch %u, Qprime %u\n",
G, Q_RI, Q_CQI, nb_rb, Q_m, ulsch_harq->Nsymb_pusch, Qprime);
H = G + Q_CQI; H = G + Q_CQI;
Hprime = H/Q_m; Hprime = H/Q_m;
// Demultiplexing/Deinterleaving of PUSCH/ACK/RI/CQI // Demultiplexing/Deinterleaving of PUSCH/ACK/RI/CQI
......
...@@ -220,6 +220,11 @@ void dlsch_scheduler_pre_ue_select_fairRR( ...@@ -220,6 +220,11 @@ void dlsch_scheduler_pre_ue_select_fairRR(
continue; continue;
} }
if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0
|| UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) { if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) {
continue; continue;
} }
...@@ -335,6 +340,10 @@ void dlsch_scheduler_pre_ue_select_fairRR( ...@@ -335,6 +340,10 @@ void dlsch_scheduler_pre_ue_select_fairRR(
if (rnti == NOT_A_RNTI) if (rnti == NOT_A_RNTI)
continue; continue;
if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0
|| UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) { if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) {
continue; continue;
} }
...@@ -459,6 +468,10 @@ void dlsch_scheduler_pre_ue_select_fairRR( ...@@ -459,6 +468,10 @@ void dlsch_scheduler_pre_ue_select_fairRR(
if (rnti == NOT_A_RNTI) if (rnti == NOT_A_RNTI)
continue; continue;
if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0
|| UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) { if(mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) {
continue; continue;
} }
...@@ -2241,7 +2254,8 @@ void ulsch_scheduler_pre_ue_select_fairRR( ...@@ -2241,7 +2254,8 @@ void ulsch_scheduler_pre_ue_select_fairRR(
if (UE_info->UE_template[CC_id][UE_id].configured == FALSE) if (UE_info->UE_template[CC_id][UE_id].configured == FALSE)
continue; continue;
if (UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0
|| UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue; continue;
// UL DCI // UL DCI
...@@ -2403,7 +2417,8 @@ void ulsch_scheduler_pre_ue_select_fairRR( ...@@ -2403,7 +2417,8 @@ void ulsch_scheduler_pre_ue_select_fairRR(
if (UE_info->UE_template[CC_id][UE_id].configured == FALSE) if (UE_info->UE_template[CC_id][UE_id].configured == FALSE)
continue; continue;
if (UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0
|| UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue; continue;
if ( (ulsch_ue_select[CC_id].ue_num >= ulsch_ue_max_num[CC_id]) || (cc_id_flag[CC_id] == 1) ) { if ( (ulsch_ue_select[CC_id].ue_num >= ulsch_ue_max_num[CC_id]) || (cc_id_flag[CC_id] == 1) ) {
...@@ -2769,13 +2784,12 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -2769,13 +2784,12 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 5; UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 5;
UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10;
} else { } else {
// assigne RBS( 3 RBs) // assigne RBS( 5 RBs)
/* first_rb[CC_id] = first_rb[CC_id] + 5;
first_rb[CC_id] = first_rb[CC_id] + 3; UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = 5;
UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = 3; UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 4;
UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 2;
UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10;
*/ } }
} }
} else if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ue_priority == SCH_UL_INACTIVE ) { } else if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ue_priority == SCH_UL_INACTIVE ) {
// assigne RBS( 3 RBs) // assigne RBS( 3 RBs)
......
...@@ -68,7 +68,7 @@ void *mac_stats_thread(void *param) { ...@@ -68,7 +68,7 @@ void *mac_stats_thread(void *param) {
else { else {
total_bler = (double)UE_scheduling_control->pusch_rx_error_num[CC_id] / (double)(UE_scheduling_control->pusch_rx_error_num[CC_id] + UE_scheduling_control->pusch_rx_num[CC_id]) * 100; total_bler = (double)UE_scheduling_control->pusch_rx_error_num[CC_id] / (double)(UE_scheduling_control->pusch_rx_error_num[CC_id] + UE_scheduling_control->pusch_rx_num[CC_id]) * 100;
} }
fprintf(fd,"MAC UE rnti %x : %s, PHR %d DLCQI %d PUSCH %d PUCCH %d RLC disc %d UL-stat rcv %lu err %lu bler %lf (%lf/%lf) total_bler %lf mcsoff %d pre_allocated nb_rb %d, mcs %d, bsr %u sched %u tbs %lu cnt %u , DL-stat tbs %lu cnt %u rb %u buf %u 1st %u ret %u ri %d\n", fprintf(fd,"MAC UE rnti %x : %s, PHR %d DLCQI %d PUSCH %d PUCCH %d RLC disc %d UL-stat rcv %lu err %lu bler %lf (%lf/%lf) total_bler %lf mcsoff %d pre_allocated nb_rb %d, mcs %d, bsr %u sched %u tbs %lu cnt %u , DL-stat tbs %lu cnt %u rb %u buf %u 1st %u ret %u ri %d inactivity timer %d\n",
rnti, rnti,
UE_scheduling_control->ul_out_of_sync == 0 ? "in synch" : "out of sync", UE_scheduling_control->ul_out_of_sync == 0 ? "in synch" : "out of sync",
UE_info->UE_template[CC_id][UE_id].phr_info, UE_info->UE_template[CC_id][UE_id].phr_info,
...@@ -97,7 +97,8 @@ void *mac_stats_thread(void *param) { ...@@ -97,7 +97,8 @@ void *mac_stats_thread(void *param) {
#endif #endif
UE_scheduling_control->first_cnt[CC_id], UE_scheduling_control->first_cnt[CC_id],
UE_scheduling_control->ret_cnt[CC_id], UE_scheduling_control->ret_cnt[CC_id],
UE_scheduling_control->aperiodic_ri_received[CC_id] UE_scheduling_control->aperiodic_ri_received[CC_id],
UE_scheduling_control->ul_inactivity_timer
); );
fprintf(fd," ULSCH rounds %d/%d/%d/%d, DLSCH rounds %d/%d/%d/%d, ULSCH errors %d, DLSCH errors %d\n", fprintf(fd," ULSCH rounds %d/%d/%d/%d, DLSCH rounds %d/%d/%d/%d, ULSCH errors %d, DLSCH errors %d\n",
UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_rounds[0], UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_rounds[0],
......
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