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Commit d4536d20 authored by Robert Schmidt's avatar Robert Schmidt
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Merge remote-tracking branch 'origin/centos-and-noavx2' into integration_2022_wk42b

parents e2521153 c174ba62
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CMakeLists.txt
View file @ d4536d20
......@@ -193,43 +193,56 @@ endif ()
if (CMAKE_BUILD_TYPE STREQUAL "")
set(CMAKE_BUILD_TYPE "RelWithDebInfo")
endif()
message("CMAKE_BUILD_TYPE is ${CMAKE_BUILD_TYPE}")
message(STATUS "CMAKE_BUILD_TYPE is ${CMAKE_BUILD_TYPE}")
add_list_string_option(CMAKE_BUILD_TYPE "RelWithDebInfo" "Choose the type of build, options are: None(CMAKE_CXX_FLAGS or CMAKE_C_FLAGS used) Debug Release RelWithDebInfo MinSizeRel." Debug Release RelWithDebInfo MinSizeRel)
Message("Architecture is ${CMAKE_SYSTEM_PROCESSOR}")
# in case /proc/cpuinfo exists we want to inspect available Intrinsics
# -so not to go always through SIMDE emulation
# -so to avoid AVX512 instructions generation by gcc
if(EXISTS "/proc/cpuinfo")
file(STRINGS "/proc/cpuinfo" CPUINFO REGEX flags LIMIT_COUNT 1)
message("AVX512 is ${AVX512}")
message("AVX2 is ${AVX2}")
if ("${AVX512}" STREQUAL "False")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -mno-avx512f -march=native -DSIMDE_X86_AVX2_NATIVE -DSIMDE_X86_AVX2_NATIVE -DSIMDE_X86_AVX512BW_NATIVE -DSIMDE_X86_AVX512F_NATIVE -DSIMDE_X86_AVX512VL_NATIVE -DSIMDE_X86_AVX_NATIVE -DSIMDE_X86_AVX_NATIVE -DSIMDE_X86_F16C_NATIVE -DSIMDE_X86_FMA_NATIVE -DSIMDE_X86_GFNI_NATIVE -DSIMDE_X86_MMX_NATIVE -DSIMDE_X86_PCLMUL_NATIVE -DSIMDE_X86_SSE2_NATIVE -DSIMDE_X86_SSE3_NATIVE -DSIMDE_X86_SSE4_1_NATIVE -DSIMDE_X86_SSE4_2_NATIVE -DSIMDE_X86_SSE_NATIVE -DSIMDE_X86_SSSE3_NATIVE -DSIMDE_X86_VPCLMULQDQ_NATIVE -DSIMDE_X86_XOP_HAVE_COM_ -DSIMDE_X86_XOP_NATIVE")
else()
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -mavx512bw -march=skylake-avx512 -mtune=skylake-avx512")
endif()
if (CPUINFO MATCHES "avx2" AND "${AVX2}" STREQUAL "True")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_AVX2_NATIVE -DSIMDE_X86_VPCLMULQDQ_NATIVE")
endif()
if (CPUINFO MATCHES "sse4_1")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSE4_1_NATIVE")
endif()
if (CPUINFO MATCHES "sse4_2")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSE4_2_NATIVE")
endif()
if (CPUINFO MATCHES "ssse3")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSSE3_NATIVE")
endif()
execute_process(COMMAND uname -m OUTPUT_VARIABLE CPUARCH OUTPUT_STRIP_TRAILING_WHITESPACE)
message(STATUS "CPUARCH ${CPUARCH}")
if(EXISTS "/proc/cpuinfo")
file(STRINGS "/proc/cpuinfo" CPUFLAGS REGEX flags LIMIT_COUNT 1)
else()
message(WARNING "did not find /proc/cpuinfo -- not setting any x86-specific compilation variables")
endif()
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -fno-var-tracking-assignments -march=native")
eval_boolean(AUTODETECT_AVX512 DEFINED CPUFLAGS AND CPUFLAGS MATCHES "avx512")
add_boolean_option(AVX512 ${AUTODETECT_AVX512} "Whether AVX512 intrinsics is available on the host processor")
Message("C_FLAGS_PROCESSOR is ${C_FLAGS_PROCESSOR}")
eval_boolean(AUTODETECT_AVX2 DEFINED CPUFLAGS AND CPUFLAGS MATCHES "avx2")
add_boolean_option(AVX2 ${AUTODETECT_AVX2} "Whether AVX2 intrinsics is available on the host processor")
#
# add autotools definitions that were maybe used!
if(${CPUARCH} STREQUAL "x86_64" AND DEFINED CPUFLAGS)
# The following intrinsics are assumed to be available on any x86 system
# (avx, f16c, fma, gnfi, mmx, pclmul, sse, sse2, sse3, xop)
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_AVX_NATIVE -DSIMDE_X86_AVX_NATIVE -DSIMDE_X86_F16C_NATIVE -DSIMDE_X86_FMA_NATIVE -DSIMDE_X86_GFNI_NATIVE -DSIMDE_X86_MMX_NATIVE -DSIMDE_X86_PCLMUL_NATIVE -DSIMDE_X86_SSE2_NATIVE -DSIMDE_X86_SSE3_NATIVE -DSIMDE_X86_SSE_NATIVE -DSIMDE_X86_XOP_HAVE_COM_ -DSIMDE_X86_XOP_NATIVE")
message(STATUS "AVX512 intrinsics are ${AVX512}")
if(${AVX512})
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_AVX512BW_NATIVE -DSIMDE_X86_AVX512F_NATIVE -DSIMDE_X86_AVX512VL_NATIVE -mavx512bw -march=skylake-avx512 -mtune=skylake-avx512")
else()
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -mno-avx512f -march=native")
endif()
message(STATUS "AVX2 intrinsics are ${AVX2}")
if(${AVX2})
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_AVX2_NATIVE -DSIMDE_X86_VPCLMULQDQ_NATIVE")
endif()
if (CPUINFO MATCHES "sse4_1")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSE4_1_NATIVE")
endif()
if(CPUINFO MATCHES "sse4_2")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSE4_2_NATIVE")
endif()
if(CPUINFO MATCHES "ssse3")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -DSIMDE_X86_SSSE3_NATIVE")
endif()
elseif(${CPUARCH} NOT STREQUAL "x86_64")
message(FATAL_ERROR "Cannot compile for CPU architecture ${CPUARCH}")
endif()
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -fno-var-tracking-assignments -march=native")
# add autotools definitions that were maybe used!
add_definitions("-DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP")
set(commonOpts "-pipe -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic")
......@@ -276,7 +289,7 @@ set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -ggdb2 -Wl,-rpath -Wl,${C
# set a flag for changes in the source code
# these changes are related to hardcoded path to include .h files
set(debugOpt "-ggdb2 -DMALLOC_CHECK_=3 -fno-delete-null-pointer-checks")
set(CMAKE_C_FLAGS_DEBUG "${debugOpt} -O0")
set(CMAKE_C_FLAGS_DEBUG "${debugOpt} -Og")
set(CMAKE_C_FLAGS_RELWITHDEBINFO "${debugOpt} -O2")
set(CMAKE_C_FLAGS_RELEASE "-O3")
......@@ -290,7 +303,6 @@ set(GIT_COMMIT_DATE "UNKNOWN")
find_package(Git)
if(GIT_FOUND)
message("git found: ${GIT_EXECUTABLE}")
# Get the current working branch
execute_process(
COMMAND git rev-parse --abbrev-ref HEAD
......
cmake_targets/build_oai
View file @ d4536d20
......@@ -53,8 +53,6 @@ BUILD_COVERITY_SCAN=0
DISABLE_HARDWARE_DEPENDENCY="False"
CMAKE_BUILD_TYPE="RelWithDebInfo"
CMAKE_CMD="$CMAKE"
AVX512="True"
AVX2="True"
BUILD_ECLIPSE=0
NR="False"
OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope"
......@@ -159,7 +157,7 @@ Options:
--noavx512
Disable AVX512 intrinsics whatever processor capability is
--noavx2
Disable AVX2 intrinsics if processor supports it or use SIMDE emulation
Disable AVX2 intrinsics whatever processor capability is
-k | --skip-shared-libraries
Skip build for shared libraries to reduce compilation time when building frequently for debugging purposes
--ninja
......@@ -394,11 +392,11 @@ function main() {
fi
shift 2;;
--noavx512)
AVX512="False"
CMAKE_CMD="$CMAKE_CMD -DAVX512=OFF"
echo_info "Disabling AVX512 instructions"
shift 1;;
--noavx2)
AVX2="False"
CMAKE_CMD="$CMAKE_CMD -DAVX2=OFF"
echo_info "Disabling AVX2 instructions"
shift 1;;
-k | --skip-shared-libraries)
......@@ -559,23 +557,9 @@ function main() {
if [[ ${#CMAKE_C_FLAGS[@]} > 0 ]]; then CMAKE_CMD="$CMAKE_CMD -DCMAKE_C_FLAGS=\"${CMAKE_C_FLAGS[*]}\""; fi
if [[ ${#CMAKE_CXX_FLAGS[@]} > 0 ]]; then CMAKE_CMD="$CMAKE_CMD -DCMAKE_CXX_FLAGS=\"${CMAKE_CXX_FLAGS[*]}\""; fi
# if --noavx512 is not specified the AVX512 equals "True" by default
# override AVX512 to "False" if processor does not have avx512
# this avoids having to specify --noavx512 systematically
if [ -f /proc/cpuinfo ]; then
if grep -q avx512 /proc/cpuinfo
then
echo_info "Processor has avx512 intrinsics"
else
echo_info "Processor does not have avx512 intrinsics"
echo_info "Forcing AVX512 to False"
AVX512="False"
fi
fi
# for historical reasons we build in a subdirectory cmake_targets/XYZ/build,
# e.g., cmake_targets/ran_build/build, hence the ../../..
CMAKE_CMD="$CMAKE_CMD -DAVX512=\"${AVX512[*]}\" -DAVX2=\"${AVX2[*]}\" ../../.."
CMAKE_CMD="$CMAKE_CMD ../../.."
echo_info "running $CMAKE_CMD"
eval $CMAKE_CMD
......
cmake_targets/macros.cmake
View file @ d4536d20
......@@ -96,3 +96,11 @@ macro(compile_asn1 asn1Source asn1cCmd ResultFlag)
DEPENDS ${asn1Source}
)
endmacro(compile_asn1)
macro(eval_boolean VARIABLE)
if(${ARGN})
set(${VARIABLE} ON)
else()
set(${VARIABLE} OFF)
endif()
endmacro()
cmake_targets/tools/build_helper
View file @ d4536d20
......@@ -33,7 +33,7 @@ OS_RELEASE=$(grep "^VERSION_ID=" /etc/os-release | sed "s/VERSION_ID=//" | sed "
case "$OS_DISTRO" in
fedora) OS_BASEDISTRO="fedora"; INSTALLER="dnf"; CMAKE="cmake" ;;
rhel) OS_BASEDISTRO="fedora"; INSTALLER="yum --skip-broken"; CMAKE="cmake3" ;;
centos) OS_BASEDISTRO="fedora"; INSTALLER="yum --skip-broken"; CMAKE="cmake3" ;;
centos) OS_BASEDISTRO="centos"; INSTALLER="yum --skip-broken"; CMAKE="cmake3" ;;
debian) OS_BASEDISTRO="debian"; INSTALLER="apt-get"; CMAKE="cmake" ;;
ubuntu) OS_BASEDISTRO="debian"; INSTALLER="apt-get"; CMAKE="cmake" ;;
esac
......
common/utils/LOG/log.c
View file @ d4536d20
......@@ -306,7 +306,7 @@ void log_getconfig(log_t *g_log)
for (int i=MIN_LOG_COMPONENTS; i < MAX_LOG_PREDEF_COMPONENTS; i++) {
if(g_log->log_component[i].name == NULL) {
g_log->log_component[i].name = malloc(16);
g_log->log_component[i].name = malloc(17);
sprintf((char *)g_log->log_component[i].name,"comp%i?",i);
logparams_logfile[i].paramflags = PARAMFLAG_DONOTREAD;
logparams_level[i].paramflags = PARAMFLAG_DONOTREAD;
......
openair1/PHY/INIT/nr_init.c
View file @ d4536d20
......@@ -194,9 +194,9 @@ int init_codebook_gNB(PHY_VARS_gNB *gNB) {
}
}
int llc;
int mmc;
double complex phase_sign;
int llc = 0;
int mmc = 0;
double complex phase_sign = 0;
//Table 5.2.2.2.1-6:
//Codebook for 2-layer CSI reporting using antenna ports 3000 to 2999+PCSI-RS
//Compute the code book size for generating 2 layers out of Tx antenna ports
......
openair1/PHY/LTE_TRANSPORT/dci.c
View file @ d4536d20
......@@ -205,7 +205,7 @@ void pdcch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
uint32_t length) {
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
//LOG_D(PHY, "%s(fp, subframe:%d, e, length:%d)\n", __FUNCTION__, subframe, length);
reset = 1;
// x1 is set in lte_gold_generic
......
openair1/PHY/LTE_TRANSPORT/edci.c
View file @ d4536d20
......@@ -56,7 +56,7 @@ void generate_edci_top(PHY_VARS_eNB *eNB, int frame, int subframe) {
void mpdcch_scrambling(LTE_DL_FRAME_PARMS *frame_parms, mDCI_ALLOC_t *mdci, uint16_t i, uint8_t *e, uint32_t length) {
int n;
uint8_t reset;
uint32_t x1, x2, s = 0;
uint32_t x1 = 0, x2 = 0, s = 0;
uint8_t Nacc = 4;
uint16_t j0, j, idelta;
uint16_t i0 = mdci->i0;
......@@ -266,7 +266,7 @@ void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe, int16_t amp,
int i;
int gain_lin_QPSK;
uint16_t *mpdcchtab;
uint32_t x1, x2, s = 0;
uint32_t x1 = 0, x2 = 0, s = 0;
uint8_t Nacc = 4;
uint16_t j0, j, idelta;
uint16_t i0;
......
openair1/PHY/LTE_TRANSPORT/group_hopping.c
View file @ d4536d20
......@@ -39,7 +39,7 @@ void generate_grouphop(LTE_DL_FRAME_PARMS *frame_parms)
uint8_t ns;
uint8_t reset=1;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
// This is from Section 5.5.1.3
uint32_t fss_pusch = frame_parms->Nid_cell + frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH;
......@@ -113,7 +113,7 @@ void generate_nPRS(LTE_DL_FRAME_PARMS *frame_parms)
uint16_t n=0;
uint8_t reset=1;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
// This is from Section 5.5.1.3
uint8_t Nsymb_UL = (frame_parms->Ncp_UL == NORMAL) ? 7 : 6;
uint16_t next = 0;
......
openair1/PHY/LTE_TRANSPORT/pbch.c
View file @ d4536d20
......@@ -146,7 +146,7 @@ void pbch_scrambling_fembms(LTE_DL_FRAME_PARMS *frame_parms,
{
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
// x1 is set in lte_gold_generic
......@@ -425,7 +425,7 @@ void pbch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
{
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
// x1 is set in lte_gold_generic
......
openair1/PHY/LTE_TRANSPORT/pucch_common.c
View file @ d4536d20
......@@ -41,7 +41,7 @@ void init_ncs_cell(LTE_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7])
{
uint8_t ns,l,reset=1,i,N_UL_symb;
uint32_t x1,x2,j=0,s=0;
uint32_t x1 = 0, x2 = 0, j = 0, s = 0;
N_UL_symb = (frame_parms->Ncp==0) ? 7 : 6;
x2 = frame_parms->Nid_cell;
......
openair1/PHY/LTE_UE_TRANSPORT/dci_ue.c
View file @ d4536d20
......@@ -1505,7 +1505,7 @@ void pdcch_unscrambling(LTE_DL_FRAME_PARMS *frame_parms,
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
// x1 is set in first call to lte_gold_generic
......
openair1/PHY/LTE_UE_TRANSPORT/pbch_ue.c
View file @ d4536d20
......@@ -360,7 +360,7 @@ void pbch_unscrambling(LTE_DL_FRAME_PARMS *frame_parms,
uint8_t frame_mod4) {
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
// x1 is set in first call to lte_gold_generic
x2 = frame_parms->Nid_cell; //this is c_init in 36.211 Sec 6.6.1
......@@ -564,7 +564,7 @@ void pbch_unscrambling_fembms(LTE_DL_FRAME_PARMS *frame_parms,
uint8_t frame_mod4) {
int i;
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
// x1 is set in first call to lte_gold_generic
x2 = frame_parms->Nid_cell+(1<<9); //this is c_init for FeMBMS in 36.211 Sec 6.6.1
......
openair1/PHY/NR_REFSIG/nr_gold.c
View file @ d4536d20
......@@ -23,7 +23,7 @@
void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB)
{
unsigned int x1, x2;
unsigned int x1 = 0, x2 = 0;
uint16_t Nid, i_ssb, i_ssb2;
unsigned char Lmax, l, n_hf, N_hf;
nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config;
......@@ -55,8 +55,7 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB)
void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
{
uint32_t x1, x2;
uint32_t x1 = 0, x2 = 0;
uint8_t reset;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs;
......@@ -79,8 +78,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint8_t nscid, uint32_t Nid) {
uint32_t x1, x2;
uint32_t x1 = 0, x2 = 0;
uint8_t reset;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
uint32_t ****pdsch_dmrs = gNB->nr_gold_pdsch_dmrs;
......@@ -104,7 +102,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint8_t nscid, uint32_t Nid) {
void nr_gold_pusch(PHY_VARS_gNB* gNB, int nscid, uint32_t nid) {
unsigned char ns;
unsigned int n,x1,x2;
unsigned int n = 0, x1 = 0, x2 = 0;
int reset;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
unsigned short l;
......@@ -127,7 +125,7 @@ void nr_gold_pusch(PHY_VARS_gNB* gNB, int nscid, uint32_t nid) {
void nr_init_prs(PHY_VARS_gNB* gNB)
{
unsigned int x1, x2;
unsigned int x1 = 0, x2 = 0;
uint16_t Nid;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
......
openair1/PHY/NR_REFSIG/nr_gold_ue.c
View file @ d4536d20
......@@ -23,7 +23,7 @@
void nr_gold_pbch(PHY_VARS_NR_UE* ue)
{
unsigned int n, x1, x2;
unsigned int n = 0, x1 = 0, x2 = 0;
unsigned int Nid, i_ssb, i_ssb2;
unsigned char Lmax, l, n_hf, N_hf;
uint8_t reset;
......@@ -55,7 +55,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
unsigned short nid)
{
unsigned char ns,l;
unsigned int n,x1,x2,x2tmp0;
unsigned int n = 0, x1 = 0, x2 = 0, x2tmp0 = 0;
uint8_t reset;
int pdcch_dmrs_init_length = (((ue->frame_parms.N_RB_DL<<1)*3)>>5)+1;
......@@ -78,8 +78,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
int nscid,
uint32_t nid) {
unsigned int x1,x2,x2tmp0;
unsigned int x1 = 0, x2 = 0, x2tmp0 = 0;
uint8_t reset;
int pdsch_dmrs_init_length = ((ue->frame_parms.N_RB_DL*12)>>5)+1;
......@@ -104,7 +103,7 @@ void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue,
uint16_t N_n_scid,
uint8_t n_scid)
{
uint32_t x1, x2, n;
uint32_t x1 = 0, x2 = 0, n = 0;
uint8_t reset, slot, symb;
NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
uint32_t ****pusch_dmrs = ue->nr_gold_pusch_dmrs;
......@@ -127,7 +126,7 @@ void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue,
void init_nr_gold_prs(PHY_VARS_NR_UE* ue)
{
unsigned int x1, x2;
unsigned int x1 = 0, x2 = 0;
uint16_t Nid;
NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
......
openair1/PHY/NR_TRANSPORT/nr_csi_rs.c
View file @ d4536d20
......@@ -28,7 +28,7 @@
void nr_init_csi_rs(const NR_DL_FRAME_PARMS *fp, uint32_t ***csi_rs, uint32_t Nid) {
uint32_t x1, x2;
uint32_t x1 = 0, x2 = 0;
uint8_t reset;
int csi_dmrs_init_length = ((fp->N_RB_DL<<4)>>5)+1;
for (uint8_t slot=0; slot<fp->slots_per_frame; slot++) {
......
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @ d4536d20
......@@ -47,7 +47,7 @@ void nr_pdcch_scrambling(uint32_t *in,
uint32_t scrambling_RNTI,
uint32_t *out) {
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
reset = 1;
x2 = (scrambling_RNTI<<16) + Nid;
LOG_D(PHY,"PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI);
......
openair1/PHY/NR_TRANSPORT/nr_pbch.c
View file @ d4536d20
......@@ -150,7 +150,7 @@ static void nr_pbch_scrambling(NR_gNB_PBCH *pbch,
uint8_t encoded,
uint32_t unscrambling_mask) {
uint8_t reset, offset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
uint32_t *pbch_e = pbch->pbch_e;
reset = 1;
// x1 is set in lte_gold_generic
......
openair1/PHY/NR_TRANSPORT/pucch_rx.c
View file @ d4536d20
......@@ -1254,7 +1254,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
// first compute DMRS component
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index+symb) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause
#ifdef DEBUG_NR_PUCCH_RX
printf("slot %d, start_symbol_index %d, symbol %d, dmrs_scrambling_id %d\n",
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ d4536d20
......@@ -804,7 +804,7 @@ void nr_pdcch_unscrambling(int16_t *e_rx,
int16_t *z2) {
int i;
uint8_t reset;
uint32_t x1, x2, s = 0;
uint32_t x1 = 0, x2 = 0, s = 0;
uint16_t n_id; //{0,1,...,65535}
uint32_t rnti = (uint32_t) scrambling_RNTI;
reset = 1;
......
openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
View file @ d4536d20
......@@ -312,7 +312,7 @@ static void nr_pbch_unscrambling(NR_UE_PBCH *pbch,
uint32_t pbch_a_prime,
uint32_t *pbch_a_interleaved) {
uint8_t reset, offset;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
uint8_t k=0;
reset = 1;
// x1 is set in first call to lte_gold_generic
......@@ -427,7 +427,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
&nr_ue_common_vars->rxdataF[0][(symbol_offset+1)*frame_parms->ofdm_symbol_size],frame_parms->ofdm_symbol_size*3,1,1);
#endif
// symbol refers to symbol within SSB. symbol_offset is the offset of the SSB wrt start of slot
double log2_maxh;
double log2_maxh = 0;
for (symbol=1; symbol<4; symbol++) {
const uint16_t nb_re=symbol == 2 ? 72 : 180;
......
openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
View file @ d4536d20
......@@ -62,7 +62,7 @@ void nr_pusch_codeword_scrambling_uci(uint8_t *in,
uint32_t* out)
{
uint8_t reset, b_idx;
uint32_t x1, x2, s=0, temp_out;
uint32_t x1 = 0, x2 = 0, s = 0, temp_out = 0;
reset = 1;
x2 = (n_RNTI<<15) + Nid;
......
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
View file @ d4536d20
......@@ -807,7 +807,7 @@ void nr_generate_pucch1_old(PHY_VARS_NR_UE *ue,
static inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) __attribute__((always_inline));
static inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) {
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
int i;
uint8_t c;
// c_init=nRNTI*2^15+n_id according to TS 38.211 Subclause 6.3.2.6.1
......@@ -1037,7 +1037,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
*/
//int32_t *txptr;
uint32_t re_offset=0;
uint32_t x1, x2, s=0;
uint32_t x1 = 0, x2 = 0, s = 0;
int i=0;
int m=0;
uint8_t startingSymbolIndex = pucch_pdu->start_symbol_index;
......
openair2/LAYER2/nr_rlc/nr_rlc_entity_am.c
View file @ d4536d20
......@@ -317,8 +317,8 @@ static void process_control_pdu(nr_rlc_entity_am_t *entity,
int so_end;
int range;
int prev_nack_sn = -1;
int prev_so_start;
int prev_so_end;
int prev_so_start = 0;
int prev_so_end = 0;
int tx_next_ack;
nr_rlc_sdu_segment_t *cur_wait_list;
nr_rlc_sdu_segment_t *prev_wait_list;
......
openair3/NAS/COMMON/API/NETWORK/as_message.c
View file @ d4536d20
......@@ -210,7 +210,9 @@ int as_message_encode(char* buffer, as_message_t* msg, int length)
as_nas_info_t nas_msg;
Byte_t *dataptr=NULL;
uint32_t len=0;
memset(&nas_msg, 0, sizeof(as_nas_info_t));
switch (msg->msgID) {
case AS_BROADCAST_INFO_IND:
/* Broadcast information */
......
sdr/ETHERNET/USERSPACE/LIB/eth_udp.c
View file @ d4536d20
......@@ -359,14 +359,14 @@ void *trx_eth_write_udp_cmd(udpTXelem_t *udpTXelem) {
#if defined(__x86_64__) || defined(__i386__)
__m256i *buff256 = (__m256i *)&(((int32_t*)buff[aid])[offset]);
for (int j=0; j<32; j+=8) {
buff_tx[1+j] = _mm256_slli_epi16(buff256[j],4);
buff_tx[2+j] = _mm256_slli_epi16(buff256[j+1],4);
buff_tx[3+j] = _mm256_slli_epi16(buff256[j+2],4);
buff_tx[4+j] = _mm256_slli_epi16(buff256[j+3],4);
buff_tx[5+j] = _mm256_slli_epi16(buff256[j+4],4);
buff_tx[6+j] = _mm256_slli_epi16(buff256[j+5],4);
buff_tx[7+j] = _mm256_slli_epi16(buff256[j+6],4);
buff_tx[8+j] = _mm256_slli_epi16(buff256[j+7],4);
buff_tx[1+j] = simde_mm256_slli_epi16(buff256[j],4);
buff_tx[2+j] = simde_mm256_slli_epi16(buff256[j+1],4);
buff_tx[3+j] = simde_mm256_slli_epi16(buff256[j+2],4);
buff_tx[4+j] = simde_mm256_slli_epi16(buff256[j+3],4);
buff_tx[5+j] = simde_mm256_slli_epi16(buff256[j+4],4);
buff_tx[6+j] = simde_mm256_slli_epi16(buff256[j+5],4);
buff_tx[7+j] = simde_mm256_slli_epi16(buff256[j+6],4);
buff_tx[8+j] = simde_mm256_slli_epi16(buff256[j+7],4);
}
#elif defined(__arm__)
int16x8_t *buff128 = (__int16x8_t*)&buff[aid][offset];
......
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