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OpenXG
OpenXG UE
Commits
4caf8801
Commit
4caf8801
authored
Mar 31, 2021
by
rmagueta
Browse files
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Browse Files
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Plain Diff
Rework default PDSCH time domain resource allocation tables
parent
b9d9c0b4
Changes
11
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Showing
11 changed files
with
208 additions
and
108 deletions
+208
-108
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+146
-0
openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
+9
-0
openair2/LAYER2/NR_MAC_UE/mac_proto.h
openair2/LAYER2/NR_MAC_UE/mac_proto.h
+2
-1
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+19
-82
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+18
-11
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+3
-3
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+1
-1
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band41.fr1.106PRB.usrpb210.conf
...ENERIC-NR-5GC/CONF/gnb.sa.band41.fr1.106PRB.usrpb210.conf
+4
-4
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
...ENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
+4
-4
No files found.
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @
4caf8801
...
...
@@ -118,6 +118,152 @@ const float table_38213_13_12_c3[16] = { 1, 0.5f, 1, 0.5f, 1, 0.5f, 0.5f, 0.5f
const
int32_t
table_38213_10_1_1_c2
[
5
]
=
{
0
,
0
,
4
,
2
,
1
};
// for PDSCH from TS 38.214 subclause 5.1.2.1.1
const
uint8_t
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
16
][
3
]
=
{
{
0
,
2
,
12
},
// row index 1
{
0
,
2
,
10
},
// row index 2
{
0
,
2
,
9
},
// row index 3
{
0
,
2
,
7
},
// row index 4
{
0
,
2
,
5
},
// row index 5
{
0
,
9
,
4
},
// row index 6
{
0
,
4
,
4
},
// row index 7
{
0
,
5
,
7
},
// row index 8
{
0
,
5
,
2
},
// row index 9
{
0
,
9
,
2
},
// row index 10
{
0
,
12
,
2
},
// row index 11
{
0
,
1
,
13
},
// row index 12
{
0
,
1
,
6
},
// row index 13
{
0
,
2
,
4
},
// row index 14
{
0
,
4
,
7
},
// row index 15
{
0
,
8
,
4
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
16
][
3
]
=
{
{
0
,
3
,
11
},
// row index 1
{
0
,
3
,
9
},
// row index 2
{
0
,
3
,
8
},
// row index 3
{
0
,
3
,
6
},
// row index 4
{
0
,
3
,
4
},
// row index 5
{
0
,
10
,
4
},
// row index 6
{
0
,
6
,
4
},
// row index 7
{
0
,
5
,
7
},
// row index 8
{
0
,
5
,
2
},
// row index 9
{
0
,
9
,
2
},
// row index 10
{
0
,
12
,
2
},
// row index 11
{
0
,
1
,
13
},
// row index 12
{
0
,
1
,
6
},
// row index 13
{
0
,
2
,
4
},
// row index 14
{
0
,
4
,
7
},
// row index 15
{
0
,
8
,
4
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2
[
16
][
3
]
=
{
{
0
,
2
,
6
},
// row index 1
{
0
,
2
,
10
},
// row index 2
{
0
,
2
,
9
},
// row index 3
{
0
,
2
,
7
},
// row index 4
{
0
,
2
,
5
},
// row index 5
{
0
,
6
,
4
},
// row index 6
{
0
,
4
,
4
},
// row index 7
{
0
,
5
,
6
},
// row index 8
{
0
,
5
,
2
},
// row index 9
{
0
,
9
,
2
},
// row index 10
{
0
,
10
,
2
},
// row index 11
{
0
,
1
,
11
},
// row index 12
{
0
,
1
,
6
},
// row index 13
{
0
,
2
,
4
},
// row index 14
{
0
,
4
,
6
},
// row index 15
{
0
,
8
,
4
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3
[
16
][
3
]
=
{
{
0
,
3
,
5
},
// row index 1
{
0
,
3
,
9
},
// row index 2
{
0
,
3
,
8
},
// row index 3
{
0
,
3
,
6
},
// row index 4
{
0
,
3
,
4
},
// row index 5
{
0
,
8
,
2
},
// row index 6
{
0
,
6
,
4
},
// row index 7
{
0
,
5
,
6
},
// row index 8
{
0
,
5
,
2
},
// row index 9
{
0
,
9
,
2
},
// row index 10
{
0
,
10
,
2
},
// row index 11
{
0
,
1
,
11
},
// row index 12
{
0
,
1
,
6
},
// row index 13
{
0
,
2
,
4
},
// row index 14
{
0
,
4
,
6
},
// row index 15
{
0
,
8
,
4
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2
[
16
][
3
]
=
{
{
0
,
2
,
2
},
// row index 1
{
0
,
4
,
2
},
// row index 2
{
0
,
6
,
2
},
// row index 3
{
0
,
8
,
2
},
// row index 4
{
0
,
10
,
2
},
// row index 5
{
1
,
2
,
2
},
// row index 6
{
1
,
4
,
2
},
// row index 7
{
0
,
2
,
4
},
// row index 8
{
0
,
4
,
4
},
// row index 9
{
0
,
6
,
4
},
// row index 10
{
0
,
8
,
4
},
// row index 11
{
0
,
10
,
4
},
// row index 12
{
0
,
2
,
7
},
// row index 13
{
0
,
2
,
12
},
// row index 14
{
1
,
2
,
4
},
// row index 15
{
0
,
0
,
0
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3
[
16
][
3
]
=
{
{
0
,
2
,
2
},
// row index 1
{
0
,
4
,
2
},
// row index 2
{
0
,
6
,
2
},
// row index 3
{
0
,
8
,
2
},
// row index 4
{
0
,
10
,
2
},
// row index 5
{
1
,
2
,
2
},
// row index 6
{
1
,
4
,
2
},
// row index 7
{
0
,
2
,
4
},
// row index 8
{
0
,
4
,
4
},
// row index 9
{
0
,
6
,
4
},
// row index 10
{
0
,
8
,
4
},
// row index 11
{
0
,
10
,
4
},
// row index 12
{
0
,
2
,
7
},
// row index 13
{
0
,
3
,
11
},
// row index 14
{
1
,
2
,
4
},
// row index 15
{
0
,
0
,
0
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2
[
16
][
3
]
=
{
{
0
,
2
,
2
},
// row index 1
{
0
,
4
,
2
},
// row index 2
{
0
,
6
,
2
},
// row index 3
{
0
,
8
,
2
},
// row index 4
{
0
,
10
,
2
},
// row index 5
{
0
,
0
,
0
},
// row index 6
{
0
,
0
,
0
},
// row index 7
{
0
,
2
,
4
},
// row index 8
{
0
,
4
,
4
},
// row index 9
{
0
,
6
,
4
},
// row index 10
{
0
,
8
,
4
},
// row index 11
{
0
,
10
,
4
},
// row index 12
{
0
,
2
,
7
},
// row index 13
{
0
,
2
,
12
},
// row index 14
{
0
,
0
,
6
},
// row index 15
{
0
,
2
,
6
}
// row index 16
};
const
uint8_t
table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3
[
16
][
3
]
=
{
{
0
,
2
,
2
},
// row index 1
{
0
,
4
,
2
},
// row index 2
{
0
,
6
,
2
},
// row index 3
{
0
,
8
,
2
},
// row index 4
{
0
,
10
,
2
},
// row index 5
{
0
,
0
,
0
},
// row index 6
{
0
,
0
,
0
},
// row index 7
{
0
,
2
,
4
},
// row index 8
{
0
,
4
,
4
},
// row index 9
{
0
,
6
,
4
},
// row index 10
{
0
,
8
,
4
},
// row index 11
{
0
,
10
,
4
},
// row index 12
{
0
,
2
,
7
},
// row index 13
{
0
,
3
,
11
},
// row index 14
{
0
,
0
,
6
},
// row index 15
{
0
,
2
,
6
}
// row index 16
};
const
char
*
prachfmt
[]
=
{
"0"
,
"1"
,
"2"
,
"3"
,
"A1"
,
"A2"
,
"A3"
,
"B1"
,
"B4"
,
"C0"
,
"C2"
,
"A1/B1"
,
"A2/B2"
,
"A3/B3"
};
const
char
*
duplex_mode
[]
=
{
"FDD"
,
"TDD"
};
...
...
openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
View file @
4caf8801
...
...
@@ -139,4 +139,13 @@ extern const float table_38213_13_12_c3[16];
extern
const
int32_t
table_38213_10_1_1_c2
[
5
];
extern
const
uint8_t
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2
[
16
][
3
];
extern
const
uint8_t
table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3
[
16
][
3
];
#endif //DEF_H
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @
4caf8801
...
...
@@ -178,7 +178,8 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
int8_t
nr_ue_process_dci_time_dom_resource_assignment
(
NR_UE_MAC_INST_t
*
mac
,
nfapi_nr_ue_pusch_pdu_t
*
pusch_config_pdu
,
fapi_nr_dl_config_dlsch_pdu_rel15_t
*
dlsch_config_pdu
,
uint8_t
time_domain_ind
);
uint8_t
time_domain_ind
,
bool
use_default
);
uint8_t
nr_ue_get_sdu
(
module_id_t
module_idP
,
int
CC_id
,
frame_t
frameP
,
...
...
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @
4caf8801
...
...
@@ -237,85 +237,15 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
int8_t
nr_ue_process_dci_time_dom_resource_assignment
(
NR_UE_MAC_INST_t
*
mac
,
nfapi_nr_ue_pusch_pdu_t
*
pusch_config_pdu
,
fapi_nr_dl_config_dlsch_pdu_rel15_t
*
dlsch_config_pdu
,
uint8_t
time_domain_ind
){
uint8_t
time_domain_ind
,
bool
use_default
){
int
dmrs_typeA_pos
=
mac
->
scc
->
dmrs_TypeA_Position
;
// uint8_t k_offset=0;
uint8_t
sliv_S
=
0
;
uint8_t
sliv_L
=
0
;
uint8_t
table_5_1_2_1_1_2_time_dom_res_alloc_A
[
16
][
3
]
=
{
// for PDSCH from TS 38.214 subclause 5.1.2.1.1
{
0
,(
dmrs_typeA_pos
==
0
)
?
2
:
3
,
(
dmrs_typeA_pos
==
0
)
?
12
:
11
},
// row index 1
{
0
,(
dmrs_typeA_pos
==
0
)
?
2
:
3
,
(
dmrs_typeA_pos
==
0
)
?
10
:
9
},
// row index 2
{
0
,(
dmrs_typeA_pos
==
0
)
?
2
:
3
,
(
dmrs_typeA_pos
==
0
)
?
9
:
8
},
// row index 3
{
0
,(
dmrs_typeA_pos
==
0
)
?
2
:
3
,
(
dmrs_typeA_pos
==
0
)
?
7
:
6
},
// row index 4
{
0
,(
dmrs_typeA_pos
==
0
)
?
2
:
3
,
(
dmrs_typeA_pos
==
0
)
?
5
:
4
},
// row index 5
{
0
,(
dmrs_typeA_pos
==
0
)
?
9
:
10
,(
dmrs_typeA_pos
==
0
)
?
4
:
4
},
// row index 6
{
0
,(
dmrs_typeA_pos
==
0
)
?
4
:
6
,
(
dmrs_typeA_pos
==
0
)
?
4
:
4
},
// row index 7
{
0
,
5
,
7
},
// row index 8
{
0
,
5
,
2
},
// row index 9
{
0
,
9
,
2
},
// row index 10
{
0
,
12
,
2
},
// row index 11
{
0
,
1
,
13
},
// row index 12
{
0
,
1
,
6
},
// row index 13
{
0
,
2
,
4
},
// row index 14
{
0
,
4
,
7
},
// row index 15
{
0
,
8
,
4
}
// row index 16
};
/*uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
{0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5}, // row index 1
{0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2
{0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3
{0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4
{0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5
{0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2}, // row index 6
{0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7
{0,5,6}, // row index 8
{0,5,2}, // row index 9
{0,9,2}, // row index 10
{0,10,2}, // row index 11
{0,1,11}, // row index 12
{0,1,6}, // row index 13
{0,2,4}, // row index 14
{0,4,6}, // row index 15
{0,8,4} // row index 16
};*/
/*uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{1,2,2}, // row index 6
{1,4,2}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
{1,2,4}, // row index 15
{0,0,0} // row index 16
};*/
/*uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{0,0,0}, // row index 6
{0,0,0}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
{0,0,6}, // row index 15
{0,2,6} // row index 16
};*/
uint8_t
mu_pusch
=
1
;
// definition table j Table 6.1.2.1.1-4
uint8_t
j
=
(
mu_pusch
==
3
)
?
3
:
(
mu_pusch
==
2
)
?
2
:
1
;
uint8_t
table_6_1_2_1_1_2_time_dom_res_alloc_A
[
16
][
3
]
=
{
// for PUSCH from TS 38.214 subclause 6.1.2.1.1
...
...
@@ -364,7 +294,7 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
pdsch_TimeDomainAllocationList
=
mac
->
DLbwp
[
0
]
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
->
choice
.
setup
;
else
if
(
mac
->
DLbwp
[
0
]
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
)
pdsch_TimeDomainAllocationList
=
mac
->
DLbwp
[
0
]
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
if
(
pdsch_TimeDomainAllocationList
)
{
if
(
pdsch_TimeDomainAllocationList
&&
use_default
==
false
)
{
if
(
time_domain_ind
>=
pdsch_TimeDomainAllocationList
->
list
.
count
)
{
LOG_E
(
MAC
,
"time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d
\n
"
,
...
...
@@ -387,8 +317,15 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
}
else
{
// Default configuration from tables
// k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
sliv_S
=
table_5_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
-
1
][
1
];
sliv_L
=
table_5_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
-
1
][
2
];
if
(
dmrs_typeA_pos
==
0
)
{
sliv_S
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
time_domain_ind
][
1
];
sliv_L
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
time_domain_ind
][
2
];
}
else
{
sliv_S
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
time_domain_ind
][
1
];
sliv_L
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
time_domain_ind
][
2
];
}
// k_offset = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
...
...
@@ -413,7 +350,7 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
pusch_TimeDomainAllocationList
=
mac
->
ULbwp
[
0
]
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
;
}
if
(
pusch_TimeDomainAllocationList
)
{
if
(
pusch_TimeDomainAllocationList
&&
use_default
==
false
)
{
if
(
time_domain_ind
>=
pusch_TimeDomainAllocationList
->
list
.
count
)
{
LOG_E
(
MAC
,
"time_domain_ind %d >= pusch->TimeDomainAllocationList->list.count %d
\n
"
,
time_domain_ind
,
pusch_TimeDomainAllocationList
->
list
.
count
);
...
...
@@ -430,8 +367,8 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
}
else
{
// k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
sliv_S
=
table_6_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
-
1
][
1
];
sliv_L
=
table_6_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
-
1
][
2
];
sliv_S
=
table_6_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
][
1
];
sliv_L
=
table_6_1_2_1_1_2_time_dom_res_alloc_A
[
time_domain_ind
][
2
];
// k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
...
...
@@ -678,7 +615,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
return
-
1
;
}
/* TIME_DOM_RESOURCE_ASSIGNMENT */
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
NULL
,
dlsch_config_pdu_1_0
,
dci
->
time_domain_assignment
.
val
)
<
0
)
{
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
NULL
,
dlsch_config_pdu_1_0
,
dci
->
time_domain_assignment
.
val
,
rnti
==
SI_RNTI
)
<
0
)
{
LOG_W
(
MAC
,
"[%d.%d] Invalid time_domain_assignment. Possibly due to false DCI. Ignoring DCI!
\n
"
,
frame
,
slot
);
return
-
1
;
}
...
...
@@ -845,7 +782,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
return
-
1
;
}
/* TIME_DOM_RESOURCE_ASSIGNMENT */
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
NULL
,
dlsch_config_pdu_1_1
,
dci
->
time_domain_assignment
.
val
)
<
0
)
{
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
NULL
,
dlsch_config_pdu_1_1
,
dci
->
time_domain_assignment
.
val
,
false
)
<
0
)
{
LOG_W
(
MAC
,
"[%d.%d] Invalid time_domain_assignment. Possibly due to false DCI. Ignoring DCI!
\n
"
,
frame
,
slot
);
return
-
1
;
}
...
...
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @
4caf8801
...
...
@@ -647,7 +647,7 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
return
-
1
;
}
/* TIME_DOM_RESOURCE_ASSIGNMENT */
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
pusch_config_pdu
,
NULL
,
dci
->
time_domain_assignment
.
val
)
<
0
)
{
if
(
nr_ue_process_dci_time_dom_resource_assignment
(
mac
,
pusch_config_pdu
,
NULL
,
dci
->
time_domain_assignment
.
val
,
false
)
<
0
)
{
return
-
1
;
}
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
View file @
4caf8801
...
...
@@ -316,11 +316,15 @@ void schedule_control_sib1(module_id_t module_id,
const
uint16_t
bwpSize
=
gNB_mac
->
type0_PDCCH_CSS_config
.
num_rbs
;
int
rbStart
=
gNB_mac
->
type0_PDCCH_CSS_config
.
cset_start_rb
;
// Calculate number of symbols
struct
NR_PDSCH_TimeDomainResourceAllocationList
*
tdaList
=
gNB_mac
->
sched_ctrlCommon
->
active_bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
const
int
startSymbolAndLength
=
tdaList
->
list
.
array
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
]
->
startSymbolAndLength
;
int
startSymbolIndex
,
nrOfSymbols
;
SLIV2SL
(
startSymbolAndLength
,
&
startSymbolIndex
,
&
nrOfSymbols
);
int
startSymbolIndex
=
0
;
int
nrOfSymbols
=
0
;
if
(
gNB_mac
->
common_channels
->
ServingCellConfigCommon
->
dmrs_TypeA_Position
==
0
)
{
startSymbolIndex
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
1
];
nrOfSymbols
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
2
];
}
else
{
startSymbolIndex
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
1
];
nrOfSymbols
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
2
];
}
if
(
nrOfSymbols
==
2
)
{
gNB_mac
->
sched_ctrlCommon
->
numDmrsCdmGrpsNoData
=
1
;
...
...
@@ -345,7 +349,6 @@ void schedule_control_sib1(module_id_t module_id,
gNB_mac
->
sched_ctrlCommon
->
rbSize
=
rbSize
;
gNB_mac
->
sched_ctrlCommon
->
rbStart
=
0
;
LOG_D
(
MAC
,
"SLIV = %i
\n
"
,
startSymbolAndLength
);
LOG_D
(
MAC
,
"startSymbolIndex = %i
\n
"
,
startSymbolIndex
);
LOG_D
(
MAC
,
"nrOfSymbols = %i
\n
"
,
nrOfSymbols
);
LOG_D
(
MAC
,
"rbSize = %i
\n
"
,
gNB_mac
->
sched_ctrlCommon
->
rbSize
);
...
...
@@ -526,11 +529,15 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
// Configure sched_ctrlCommon for SIB1
schedule_control_sib1
(
module_idP
,
CC_id
,
time_domain_allocation
,
mcsTableIdx
,
mcs
,
candidate_idx
,
sib1_sdu_length
);
// Calculate number of symbols
int
startSymbolIndex
,
nrOfSymbols
;
struct
NR_PDSCH_TimeDomainResourceAllocationList
*
tdaList
=
gNB_mac
->
sched_ctrlCommon
->
active_bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
const
int
startSymbolAndLength
=
tdaList
->
list
.
array
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
]
->
startSymbolAndLength
;
SLIV2SL
(
startSymbolAndLength
,
&
startSymbolIndex
,
&
nrOfSymbols
);
int
startSymbolIndex
=
0
;
int
nrOfSymbols
=
0
;
if
(
gNB_mac
->
common_channels
->
ServingCellConfigCommon
->
dmrs_TypeA_Position
==
0
)
{
startSymbolIndex
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
1
];
nrOfSymbols
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
2
];
}
else
{
startSymbolIndex
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
1
];
nrOfSymbols
=
table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3
[
gNB_mac
->
sched_ctrlCommon
->
time_domain_allocation
][
2
];
}
// Calculate number of PRB_DMRS
uint8_t
N_PRB_DMRS
=
gNB_mac
->
sched_ctrlCommon
->
numDmrsCdmGrpsNoData
*
6
;
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
4caf8801
...
...
@@ -1762,7 +1762,7 @@ void mac_remove_nr_ue(module_id_t mod_id, rnti_t rnti)
}
}
void
nr_mac_remove_ra_rnti
_ue
(
module_id_t
mod_id
,
rnti_t
rnti
)
{
void
nr_mac_remove_ra_rnti
(
module_id_t
mod_id
,
rnti_t
rnti
)
{
// Hack to remove UE in the phy (following the same procedure as in function mac_remove_nr_ue)
if
(
pthread_mutex_lock
(
&
rnti_to_remove_mutex
))
exit
(
1
);
if
(
rnti_to_remove_count
==
10
)
exit
(
1
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
4caf8801
...
...
@@ -510,7 +510,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
if
(
no_sig
)
{
LOG_W
(
NR_MAC
,
"Random Access %i failed at state %i
\n
"
,
i
,
ra
->
state
);
nr_mac_remove_ra_rnti
_ue
(
gnb_mod_idP
,
ra
->
rnti
);
nr_mac_remove_ra_rnti
(
gnb_mod_idP
,
ra
->
rnti
);
nr_clear_ra_proc
(
gnb_mod_idP
,
CC_idP
,
frameP
,
ra
);
}
else
{
...
...
@@ -545,7 +545,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
if
(
ra
->
cfra
)
{
LOG_I
(
NR_MAC
,
"(ue %i, rnti 0x%04x) CFRA procedure succeeded!
\n
"
,
UE_id
,
ra
->
rnti
);
nr_mac_remove_ra_rnti
_ue
(
gnb_mod_idP
,
ra
->
rnti
);
nr_mac_remove_ra_rnti
(
gnb_mod_idP
,
ra
->
rnti
);
nr_clear_ra_proc
(
gnb_mod_idP
,
CC_idP
,
frameP
,
ra
);
UE_info
->
active
[
UE_id
]
=
true
;
...
...
@@ -581,7 +581,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
continue
;
LOG_W
(
NR_MAC
,
"Random Access %i failed at state %i
\n
"
,
i
,
ra
->
state
);
nr_mac_remove_ra_rnti
_ue
(
gnb_mod_idP
,
ra
->
rnti
);
nr_mac_remove_ra_rnti
(
gnb_mod_idP
,
ra
->
rnti
);
nr_clear_ra_proc
(
gnb_mod_idP
,
CC_idP
,
frameP
,
ra
);
}
}
...
...
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
4caf8801
...
...
@@ -318,7 +318,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *secon
void
mac_remove_nr_ue
(
module_id_t
mod_id
,
rnti_t
rnti
);
void
nr_mac_remove_ra_rnti
_ue
(
module_id_t
mod_id
,
rnti_t
rnti
);
void
nr_mac_remove_ra_rnti
(
module_id_t
mod_id
,
rnti_t
rnti
);
int
allocate_nr_CCEs
(
gNB_MAC_INST
*
nr_mac
,
NR_BWP_Downlink_t
*
bwp
,
...
...
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band41.fr1.106PRB.usrpb210.conf
View file @
4caf8801
...
...
@@ -64,13 +64,13 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0
=
0
;
#this is SS=
2,L=12
initialDLBWPstartSymbolAndLength_0
=
53
;
#this is SS=
1,L=13
initialDLBWPstartSymbolAndLength_0
=
40
;
initialDLBWPk0_1
=
0
;
initialDLBWPmappingType_1
=
0
;
#this is SS=2,L=1
0
initialDLBWPstartSymbolAndLength_1
=
81
;
#this is SS=2,L=1
2
initialDLBWPstartSymbolAndLength_1
=
53
;
initialDLBWPk0_2
=
0
;
initialDLBWPmappingType_2
=
0
;
...
...
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf
View file @
4caf8801
...
...
@@ -64,13 +64,13 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0
=
0
;
#this is SS=
2,L=12
initialDLBWPstartSymbolAndLength_0
=
53
;
#this is SS=
1,L=13
initialDLBWPstartSymbolAndLength_0
=
40
;
initialDLBWPk0_1
=
0
;
initialDLBWPmappingType_1
=
0
;
#this is SS=2,L=1
0
initialDLBWPstartSymbolAndLength_1
=
81
;
#this is SS=2,L=1
2
initialDLBWPstartSymbolAndLength_1
=
53
;
initialDLBWPk0_2
=
0
;
initialDLBWPmappingType_2
=
0
;
...
...
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